Claims:1. A method of communication between a first controller of a electronic trip unit (ETU) and a second controller of the ETU, said method comprising the steps of:
configuring the first controller as a master controller;
configuring the second controller as a slave controller;
configuring, at the second controller, a Direct Memory Access (DMA) to enable the DMA to receive an initial part of a frame comprising start of frame and data length;
receiving, from the first controller, at the second controller, the initial part of the frame;
reconfiguring, at the second controller, the Direct Memory Access (DMA) based on the initial part of the frame to enable the DMA to receive remaining part of the frame; and
receiving, at the second controller, the remaining part of the frame.

2. The method of claim 1, wherein the frame comprises a first identifier indicative of type of frame, a second identifier indicative of type of data, the data length, actual frame data, and cyclic redundancy check (CRC).

3. The method of claim 2, wherein the type of frame is selected from any or a combination of query, and response.

4. The method of claim 2, wherein the type of data is selected from any or a combination of metering related data, record relating data, and settings relating data.

5. The method of claim 1, wherein upon reception of the complete frame at the second controller, cyclic redundancy check (CRC) is performed.

6. The method of claim 1, wherein the first controller and the second controller are selected from any or a combination of microcontroller or microprocessor.

7. The method of claim 1, wherein the master controller is operatively coupled with a plurality of slave controllers.

8. The method of claim 1, wherein Serial Peripheral Interface (SPI) communication protocol is used between the first and the second controller.

9. A system for communication between a first controller of an electronic trip unit (ETU) and a second controller of the ETU, said system comprising:
a master controller configuration module configured to configure the first controller as a master controller;
a slave controller configuration module configured to configure the second controller as a slave controller;
an initial DMA configuration module configured to configure, at the second controller, a Direct Memory Access (DMA) to enable the DMA to receive an initial part of a frame comprising start of frame and data length;
an initial frame receive module configured to receive, from the first controller, at the second controller, the initial part of the frame;
a DMA reconfiguration module configured to reconfigure, at the second controller, the Direct Memory Access (DMA) based on the initial part of the frame to enable the DMA to receive remaining part of the frame; and
a remaining frame receive module configured to receive, at the second controller, the remaining part of the frame.

10. The system of claim 9, wherein the frame comprises a first identifier indicative of type of frame, a second identifier indicative of type of data, the data length, actual frame data, and cyclic redundancy check (CRC).

11. The system of claim 9, wherein upon reception of the complete frame at the second controller, cyclic redundancy check (CRC) is performed.

12. The system of claim 9, wherein the first controller and the second controller are selected from any or a combination of microcontroller or microprocessor.

13. The system of claim 9, wherein Serial Peripheral Interface (SPI) communication protocol is used between the first and the second controller.

14. The system of claim 9, wherein the first controller is main controller of the ETU and second controller is the display controller of the ETU. , Description:TECHNICAL FIELD
[0001] The present disclosure generally relates to the field of circuit breakers. In particular, the present disclosure pertains to an inter-controller communication system and method for serial communication using Direct Memory Access (DMA) in circuit breakers.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Circuit breakers are used to provide electrical protections by discontinuing electrical supply to loads when the electrical parameters supplied to the load cross respective predefined thresholds that are sensed by electronic trip units (ETU). These ETU’s provide a variety of protection such as current protection, voltage protection, and frequency protection. Settings for the various protections offered can be done through rotary switches, dip switches, and, display navigation. Also these electronic trip units are capable of communicating with the external world (HMI, SCADA or various modules) using protocols such as CAN bus, MODBUS, etc. As the microcontroller based ETU is capable of providing all the above-mentioned features, it may therefore use more than one microcontroller or microprocessor for performing the operations listed above.
[0004] In an exemplary scenario, one microcontroller or microprocessor can be used to perform breaker critical operations such as fault sensing, giving trip command to the breaker in case of fault, generating trip records, and calculating metering data, whereas another microcontroller or microprocessor may be used for providing user interface such as display navigation. As the data is generated in one microcontroller or microprocessor, it needs to be communicated to another microcontroller or microprocessor so that a user can view the data as and when required.
[0005] Various methods for communication and data exchange in the field of circuit breakers are described in prior arts such as U.S. Patent No. 7,444,440 B2 describes “Method and device for providing high data rate for a serial peripheral interface”, wherein an improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller based products and other components and devices to achieve a higher serial transmit and receive data rate. Another U.S. Patent No. 8,386,662 B2 describes “Method for a DMA-compatible peripheral", wherein the method includes preparing, in memory, a data structure comprising the peripheral configuration data and the data to be transmitted from the memory to said peripheral, and implementing an operation to transfer said data to the peripheral registers implemented in memory according to an incremental DMA mode from variable addresses of the data of said structure to the variable addresses of the different peripheral registers, the initialization phase of the peripheral control registers being completed during said DMA transfer operation.
[0006] Cited prior arts in general talk about use of direct memory access (DMA) to transfer data from SPI special function register to controller buffer or vice-versa, which reduces the microcontroller CPU usage and increases communication speed. Existing arts also disclose simultaneous configuration of SPI registers during DMA transfer to reduce communication time.
[0007] However, none of the methods suggested solves the problem when length of the data being sent from a master device varies, and slave device does not know the exact data length of data it has to receive, specifically when the data is being sent from the master device at a frequency instead of being queried from the slave device. Also, existing prior arts do not talk about any frame format for communication and also fail to solve the problem when the length of data to be sent from the master device varies.
[0008] There is therefore a need for an enhanced data exchange method to be used in circuit breakers, where data being sent from the master device varies and the slave device knows the exact length of data it has to receive, specifically when the data is being sent from the master device at a frequency instead of being queried from the slave device.
[0009] All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
[0010] In some embodiments, the numbers expressing quantities of ingredients, properties such as concentration, reaction conditions, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term “about.” Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
[0011] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0012] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.

OBJECTS OF THE INVENTION
[0013] An object of the present disclosure is to provide a unique frame format for communication of wide variety of data that can differ in length.
[0014] Another object of the present disclosure is to providea system and method for receiving data of variable length efficiently in a slave device by dynamically configuring DMA for reception of data in lesser time than required for transfer of one byte from a master device to the slave device.
[0015] Another object of the present disclosure is toprovide reduced number of interrupts and configure a processor efficient design by incorporating DMA and handshaking signal for communication between master and slave devices.
[0016] Another object of the present disclosure is to provide a system and method that disallows communication over single frame size, thereby enhancing bandwidth.
[0017] Another object of the present disclosure is to provide a system andmethod for allowing microcontrollers and/or microprocessors to share data in a single frame without breaking it into number of frames.
[0018] Another object of the present disclosure is to provide a means to avoid additional payload that is required on a communication protocol in case data gets divided into multiple frames.

SUMMARY
[0019] Aspects of present disclosure relate to a method for communication between two or more integrated circuits e.g. two or more microcontrollers and/or microprocessors in an electronic trip unit (ETU) using the proposed frame format of variable data length through serial peripheral interface(SPI) protocol. In ETU’s, data generated in one microcontroller and/or microprocessor needs to be communicated to another controller/processor (collectively referred to as microcontroller or microprocessor or simply as controller hereinafter), and can be a time critical activity. Thus, high speed SPI protocol incorporating unique proprietary communication frame format, and using DMA for transfer of data between SPI receive buffer register and RAM location for time bound and reliable communication of wide variety of data from one controller to another has been disclosed.
[0020] In an aspect, the proposed method allows sharing of information or data between integrated circuits such as microcontrollers and/or microprocessors used in an electronic trip unit (ETU) using a unique proprietary frame format or protocol having different frame sizes(due to varying data length) by dynamically configuring DMA for reception of data in lesser time than required for transfer of one byte as per the data length. In another aspect, the proposed method removes the need to stick to fixed frame size, and allows microcontrollers and/or microprocessors to share data in a single frame without breaking it into number of frames, and helps avoid additional payload required on the communication protocol in case the data gets divided into multiple frames.
[0021] In an exemplary aspect, the present disclosure relates toan improved data exchange methodology between communication module (i.e. hardwired engine) such as SPI / I2C, etc. and data exchange module such as DMA of an integrated circuit such as microcontroller or microprocessor etc. at slave or reception side, by dynamically configuring/reconfiguring the data exchange module (such as direct memory access (DMA)) of unique proprietary protocol having unequal communication frame sizes due to varying data length present in each frame of electronic trip unit (ETU) of circuit breakers in lesser time than required for transfer of one byte. The proposed system comprises a first microcontroller/microprocessor that generates data and can be responsible for data processing, measurement and fault sensing etc., and a second microcontroller/microprocessor that stores data generated by the first microcontroller and provides user interface, etc.
[0022] In a further exemplary aspect, the present disclosure also discloses Serial Peripheral Interface (SPI) protocol for inter-controller or processor communication, and suggests a unique frame format for communication of data between master (main controller) and slave (display controller). In an aspect, the frame format includes a frame identifier 1(FI-1) for identification of type of frame (Query/Response), frame identifier 2 (FI-2) for type of data (Metering/Records/Protection settings etc.), data length that specifies length of data, actual data, and cyclic redundancy check (CRC). Furthermore, the communication incorporates DMA for transfer of data from SPI receive buffer register of master controller to RAM location at slave controller. In order to initiate transmission from the slave device to the master device, a handshaking signal can be used to synchronize clock between the master and the slave controller.
[0023] In an aspect, the present disclosure provides a method of communication between a first controller of an electronic trip unit (ETU) and a second controller of the ETU, wherein method comprises the steps of configuring the first controller as a master controller; configuring the second controller as a slave controller; configuring, at the second controller, a Direct Memory Access (DMA) to enable the DMA to receive an initial part of a frame comprising start of frame and data length; receiving, from the first controller, at the second controller, the initial part of the frame; reconfiguring, at the second controller, the Direct Memory Access (DMA) based on the initial part of the frame to enable the DMA to receive remaining part of the frame; and receiving, at the second controller, the remaining part of the frame.
[0024] In an aspect, the frame can include a first identifier indicative of type of frame, a second identifier indicative of type of data, the data length, actual frame data, and cyclic redundancy check (CRC).In another aspect, the type of frame can be selected from any or a combination of query, and response. In yet another aspect, the type of data can be selected from any or a combination of metering related data, record relating data, and settings relating data. In an aspect, upon reception of the complete frame at the second controller, cyclic redundancy check (CRC) can be performed. In another aspect, the first controller and the second controller can be selected from any or a combination of microcontroller or microprocessor. In yet another aspect, the master controller can be operatively coupled with a plurality of slave controllers. In yet another aspect, Serial Peripheral Interface (SPI) or I2C communication protocol can be used between the first and the second controller.
[0025] The present disclosure further relates to a system for communication between a first controller of an electronic trip unit (ETU) and a second controller of the ETU, wherein system can include a master controller configuration module configured to configure the first controller as a master controller; a slave controller configuration module configured to configure the second controller as a slave controller; an initial DMA configuration module configured to configure, at the second controller, a Direct Memory Access (DMA) to enable the DMA to receive an initial part of a frame comprising start of frame and data length; an initial frame receive module configured to receive, from the first controller, at the second controller, the initial part of the frame; a DMA reconfiguration module configured to reconfigure, at the second controller, the Direct Memory Access (DMA) based on the initial part of the frame to enable the DMA to receive remaining part of the frame; and a remaining frame receive module configured to receive, at the second controller, the remaining part of the frame.
[0026] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In the Figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label with a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
[0028] FIG.1 illustrates an exemplary block diagram showing communication interface between main controller and display controller in accordance with an embodiment of the present disclosure.
[0029] FIG. 2 illustrates exemplary functional modules of inter-controller communication system in accordance to an embodiment of present disclosure.
[0030] FIG. 3 illustrates the proposed inter-controller communication frame format in accordance with an embodiment of the present disclosure.
[0031] FIG. 4 illustrates an exemplary flow diagram showing inter-controller communication in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0032] Embodiments of the present disclosure include various steps, which will be described below. The steps may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, steps may be performed by a combination of hardware, software, and firmware and/or by human operators.
[0033] Embodiments of the present disclosure may be provided as a computer program product, which may include a machine-readable storage medium tangibly embodying thereon instructions, which may be used to program a computer (or other electronic devices) to perform a process. The machine-readable medium may include, but is not limited to, fixed (hard) drives, magnetic tape, floppy diskettes, optical disks, compact disc read-only memories (CD-ROMs), and magneto-optical disks, semiconductor memories, such as ROMs, PROMs, random access memories (RAMs), programmable read-only memories (PROMs), erasable PROMs (EPROMs), electrically erasable PROMs (EEPROMs), flash memory, magnetic or optical cards, or other type of media/machine-readable medium suitable for storing electronic instructions (e.g., computer programming code, such as software or firmware).
[0034] If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0035] All components of electronic tripping unit described herein can be arranged in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0036] Although the present disclosure has been described with the system and method for vehicle license plate detection and recognition it should be appreciated that the same has been done merely to illustrate the disclosure in an exemplary manner and any other purpose or function for which the explained structure or configuration can be used, is covered within the scope of the present disclosure.
[0037] Various methods described herein may be practiced by combining one or more machine-readable storage media containing the code according to the present disclosure with appropriate standard computer hardware to execute the code contained therein. An apparatus for practicing various embodiments of the present disclosure may involve one or more computers (or one or more processors within a single computer) and storage systems containing or having network access to computer program(s) coded in accordance with various methods described herein, and the method steps of the disclosure could be accomplished by modules, routines, subroutines, or subparts of a computer program product. Various terms as used herein are shown below. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
[0038] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the disclosure to those of ordinary skill in the art. Moreover, all statements herein reciting embodiments of the disclosure, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future (i.e., any elements developed that perform the same function, regardless of structure).
[0039] Thus, for example, it will be appreciated by those of ordinary skill in the art that the diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodying this disclosure. The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing associated software. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the entity implementing this disclosure. Those of ordinary skill in the art further understand that the exemplary hardware, software, processes, methods, and/or operating systems described herein are for illustrative purposes and, thus, are not intended to be limited to any particular named.
[0040] Aspects of present disclosure relate to a method for communication between two or more integrated circuits e.g. two or more microcontrollers and/or microprocessors in an electronic trip unit (ETU) using the proposed frame format of variable data length through serial peripheral interface (SPI) protocol. In ETU’s, data generated in one microcontroller and/or microprocessor needs to be communicated to another controller/processor (collectively referred to as microcontroller or microprocessor or simply as controller hereinafter), and can be a time critical activity. Thus, high speed SPI protocol incorporating unique proprietary communication frame format, and using DMA for transfer of data between SPI receive buffer register and RAM location for time bound and reliable communication of wide variety of data from one controller to another has been disclosed.
[0041] In an aspect, the proposed method allows sharing of information or data between integrated circuits such as microcontrollers and/or microprocessors used in an electronic trip unit (ETU) using a unique proprietary frame format or protocol having different frame sizes (due to varying data length) by dynamically configuring DMA for reception of data in lesser time than required for transfer of one byte as per the data length. In another aspect, the proposed method removes the need to stick to fixed frame size, and allows microcontrollers and/or microprocessors to share data in a single frame without breaking it into number of frames, and helps avoid additional payload required on the communication protocol in case the data gets divided into multiple frames.
[0042] In an exemplary aspect, the present disclosure relates to an improved data exchange methodology between communication module (i.e. hardwired engine) such as SPI / I2C, etc. and data exchange module such as DMA of an integrated circuit such as microcontroller or microprocessor etc. at slave or reception side, by dynamically configuring/reconfiguring the data exchange module (such as direct memory access (DMA)) of unique proprietary protocol having unequal communication frame sizes due to varying data length present in each frame of electronic trip unit (ETU) of circuit breakers in lesser time than required for transfer of one byte. The proposed system comprises a first microcontroller/microprocessor that generates data and can be responsible for data processing, measurement and fault sensing etc., and a second microcontroller/microprocessor that stores data generated by the first microcontroller and provides user interface, etc.
[0043] In a further exemplary aspect, the present disclosure also discloses Serial Peripheral Interface (SPI) protocol for inter-controller or processor communication, and suggests a unique frame format for communication of data between master (main controller) and slave (display controller). In an aspect, the frame format includes a frame identifier 1(FI-1) for identification of type of frame (Query/Response), frame identifier 2 (FI-2) for type of data (Metering/Records/Protection settings etc.), data length that specifies length of data, actual data, and cyclic redundancy check (CRC). Furthermore, the communication incorporates DMA for transfer of data from SPI receive buffer register of master controller to RAM location at slave controller. In order to initiate transmission from the slave device to the master device, a handshaking signal can be used to synchronize clock between the master and the slave controller.
[0044] In an aspect, the present disclosure provides a method of communication between a first controller of an electronic trip unit (ETU) and a second controller of the ETU, wherein method comprises the steps of configuring the first controller as a master controller; configuring the second controller as a slave controller; configuring, at the second controller, a Direct Memory Access (DMA) to enable the DMA to receive an initial part of a frame comprising start of frame and data length; receiving, from the first controller, at the second controller, the initial part of the frame; reconfiguring, at the second controller, the Direct Memory Access (DMA) based on the initial part of the frame to enable the DMA to receive remaining part of the frame; and receiving, at the second controller, the remaining part of the frame.
[0045] In an aspect, the frame can include a first identifier indicative of type of frame, a second identifier indicative of type of data, the data length, actual frame data, and cyclic redundancy check (CRC).In another aspect, the type of frame can be selected from any or a combination of query, and response. In yet another aspect, the type of data can be selected from any or a combination of metering related data, record relating data, and settings relating data. In an aspect, upon reception of the complete frame at the second controller, cyclic redundancy check (CRC) can be performed. In another aspect, the first controller and the second controller can be selected from any or a combination of microcontroller or microprocessor. In yet another aspect, the master controller can be operatively coupled with a plurality of slave controllers. In yet another aspect, Serial Peripheral Interface (SPI) or I2C communication protocol can be used between the first and the second controller.
[0046] The present disclosure further relates to a system for communication between a first controller of an electronic trip unit (ETU) and a second controller of the ETU, wherein system can include a master controller configuration module configured to configure the first controller as a master controller; a slave controller configuration module configured to configure the second controller as a slave controller; an initial DMA configuration module configured to configure, at the second controller, a Direct Memory Access (DMA) to enable the DMA to receive an initial part of a frame comprising start of frame and data length; an initial frame receive module configured to receive, from the first controller, at the second controller, the initial part of the frame; a DMA reconfiguration module configured to reconfigure, at the second controller, the Direct Memory Access (DMA) based on the initial part of the frame to enable the DMA to receive remaining part of the frame; and a remaining frame receive module configured to receive, at the second controller, the remaining part of the frame.
[0047] FIG.1 illustrates an exemplary block diagram 100 of serial peripheral interface (SPI) communication interface between main controller 102 and one or more display controller(s) 104 in accordance with an embodiment of the present disclosure. As shown, SPI communication protocol uses four logic signals Master Output Slave Input (MOSI), Master Input Slave Output (MISO), Serial Clock (SCLK), and Slave Select (SS), wherein the main controller 102 can act as a master device, and the display controller 104 can act as a slave device. Although the present representation of FIG. 1 has been illustrated with respect to one slave device 104, any number of slave devices 104 can be configured and be operatively coupled with the master device 102, all of which possible implementations are well within the scope of the present disclosure.
[0048] Although the present disclosure has been described with respect to SPI communication protocol being used, any other appropriate protocol such as I2C (for ‘Inter-Integrated Circuit’, protocol) can also be configured, all of which possible embodiments are well within the scope of the present disclosure. Both protocols are well-suited for communications between integrated circuits, for slow communication with on-board peripherals.SPI is a single-master communication protocol. This means that one central device initiates all the communications with the slaves. When the SPI master wishes to send data to a slave and/or request information from it, it selects slave by pulling the corresponding SS line low and it activates the clock signal at a clock frequency usable by the master and the slave. The master generates information onto MOSI line while it samples the MISO line. On the other hand, I²C is a multi-master protocol that uses 2 signal lines. The two I²C signals are called ‘serial data’ (SDA) and ‘serial clock’ (SCL). There is no need of chip select (slave select) or arbitration logic. Virtually any number of slaves and any number of masters can be connected onto these 2 signal lines and communicate between each other using a protocol.
[0049] In an aspect, a typical electronic trip unit can include a main controller 102 that can be configured to sense fault, issue trip command, and generate metering data, whereas display controller 104 can be responsible for providing user interface. Data generated in the main controller 102 can be stored in the display controller 104 and hence the need of communicating data from the main controller 102 to the display controller 104 using SPI/I2C protocol, for instance.
[0050] In another embodiment, a wide variety of data needs to be communicated from master 102 to slave device 104 or vice-versa. The data varies in size, and also the action to be taken on each data differs. A unique frame format can be used so as to differentiate the type of data and for ease of action. Also, as the data length varies with the type of data, an efficient method or process can be carried out to receive data of variable length from the master 102 using DMA (Direct Memory Access). Serial Peripheral Interface (SPI) protocol in general gives an interrupt whenever one byte of data gets transmitted or received. For example, in case the speed of SPI communication between master 102 and slave 104 can be 250Kbps, then every 40us one byte of data can be transmitted or received. Thus, every 40us one interrupt can be received and can increase CPU usage. The direct memory access (DMA) can be used for transferring the data from the SPI peripheral to the RAM buffer in the slave 104 (i.e. a display controller) and vice-versa such that instead of every 40us an interrupt needs to be processed after DMA transfer gets completed that can be after complete reception of data frame. The process can reduce the processor usage so that the controller can be free for other critical activities.
[0051] FIG. 2 illustrates exemplary functional modules of inter-controller communication system 200 in accordance to an embodiment of present disclosure. In an aspect, the proposed system 200 can be configured for communication between a first controller of an electronic trip unit (ETU) of a circuit breaker and a second controller of the ETU, wherein system 200 can include a master controller configuration module 202 that can be configured to configure the first controller as a master controller, and a slave controller configuration module 204 that can be configured to configure the second controller as a slave controller.
[0052] In an aspect, upon configuration of the main/master controller and the slave/display controllers, system 200 of the present disclosure can include an initial DMA configuration module 206 that can be configured to configure, at the second/slave controller, a Direct Memory Access (DMA) to enable the DMA to receive an initial part of a frame comprising start of frame and data length. Therefore, the DMA can first be configured so as to receive a first/initial part of the frame that includes the start of frame indicator along with the length indicator the data of the frame.
[0053] System 200 can further include an initial frame receive module 208 configured to receive, from the first/master controller, at the second/slave controller, the initial part of the frame, and a DMA reconfiguration module 210 configured to reconfigure, at the second controller, the Direct Memory Access (DMA) based on the initial part of the frame to enable the DMA to receive remaining part of the frame. The DMA can therefore again be configured by the module 210 so that, based on the length of the data indicator received in the initial frame, the DMA can be dynamically prepared in lesser time than required for transfer of one byte so as to receive the remaining frame. Therefore DMA configuration would be different if the data length is shorter when compared with when the data length is longer.
[0054] System 200 can further include a remaining frame receive module 212 that can be configured to receive, at the second controller, the remaining part of the frame, for which the DMA has been appropriately configured.
[0055] In an aspect and also with respect to FIG. 3, the proposed frame structure 300 comprises a first identifier 302 indicative of type of frame, a second identifier 304 indicative of type of data, the data length 306, actual frame data 308, and cyclic redundancy check (CRC) 310.
[0056] In an aspect, upon reception of the complete frame 300 at the second controller, cyclic redundancy check (CRC) can be performed. In yet another aspect, the first controller and the second controller can be selected from any or a combination of microcontroller or microprocessor. Furthermore, Serial Peripheral Interface (SPI) communication protocol can be used between the first and the second controller. In an aspect, the first controller can be the main controller of the ETU, and the second controller can be display controller of the ETU of the circuit breaker.
[0057] In an aspect, the proposed system allows to share information or data between the integrated circuits like microcontrollers or microprocessors used in ETU with unique proprietary frame format 300 or protocol (SPI or I2C) having different frame size due to varying data length by dynamically configuring DMA for reception of data in lesser time than required for transfer of one byte as per the data length. Thus, therefore no need to stick to the fixed frame size. This also allows the microcontrollers or microprocessors to share data in single frame without breaking it into number of frames, which helps avoid additional payload that is otherwise required on the communication protocol if the data is getting divided into multiple frames. The proposed system therefore allows the microcontrollers and/or microprocessors to share data in a single frame without breaking it into number of frames.
[0058] In an aspect, the proposed system can further incorporate handshaking signal being exchanged between the master and the slave devices, wherein the handshaking can be used when the slave device wants to send data to the master and needs to request for clock from the master and when the slave has finished the transmission of data, so that master can stop sending the clock signal and can process the frame received from slave. Alternately, Handshaking signal can be used to indicate the completion of DMA configuration in slave device so that the master can send the remaining frame.
[0059] FIG. 3 illustrates a typical inter controller communication frame format in accordance with an embodiment of the present disclosure. As shown, a unique frame format 300 for communication of data between master and slave can be presented, wherein the frame format can include frame identifier_1 302 for identifying type of frame that can be either query or response frame, identifier_2 304 for identifying type of data that can be metering data, record relating data, protection data or settings data, etc. Format 300 can further include data length 306 that specifies the length of data, actual data 308, and cyclic redundancy check (CRC) 310 that can do data validation at the end of data reception and the data can be shared in a single frame without breaking it into number of frames. The CRC error detecting code can also detect any accidental change if the same happens in raw data.
[0060] In an embodiment, data such as current, voltage, frequency, power metering can be communicated to slave device either based on query or at regular intervals. Before receiving any data from the master, slave needs to configure the DMA to receive the particular number of bytes from the master, and transfer them to the RAM buffer of the slave. Whenever the data from the sender gets communicated, receiver does not know the length of data to be received, and therefore the receiver can initially be configured to receive a partial frame consisting of start of frame and data length. In another embodiment, the communication incorporates DMA for transfer of data from SPI receive buffer register of the master to the RAM location of the slave, and in order to initiate transmission from the slave to the master, a handshaking signal can be used to synchronize clock between master and slave controller.
[0061] FIG. 4 illustrates an exemplary flow diagram 400 showing inter-controller communication in accordance with an embodiment of the present disclosure. As shown, the proposed method includes the steps of, at step 402, configuring a first controller as a master controller, and at step 404, configuring the second controller as a slave controller. At step 406, the method includes configuring, at the second controller, a Direct Memory Access (DMA) to enable the DMA to receive an initial part of a frame comprising start of frame and data length. At step 408, the method can include receiving, from the first controller, at the second controller, the initial part of the frame. At step 410, the method can include reconfiguring, at the second controller, the Direct Memory Access (DMA) based on the initial part of the frame to enable the DMA to receive remaining part of the frame; and finally at step 412, the method can include receiving, at the second controller, the remaining part of the frame.
[0062] The aforementioned exemplary embodiment can be presented as teaching examples related to the system and method for enhanced data exchange over serial communication using DMA in circuit breakers.
[0063] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refers to at least one of something selected from the group consisting of A, B, C ….and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc. The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.
[0064] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE INVENTION
[0065] The present disclosure provides a unique communication frame format for communication of wide variety of data that can differ in length and action to be taken.
[0066] The present disclosure provides a system and method for receiving data of variable length efficiently in the slave by dynamically configuring DMA for reception of data in lesser time than required for transfer of one byte from master device to slave.
[0067] The present disclosure provides reduced number of interrupts and processor efficient design by incorporating DMA and handshaking signal for communication between master and slave devices.
[0068] The present disclosure provides a system and method that disallow communication over single frame size, thereby enhancing bandwidth.
[0069] The present disclosure provides a system and method for allowing microcontrollers or microprocessors to share data in a single frame without breaking it into number of frames.
[0070] The present disclosure provides a means to avoid additional payload required on the communication protocol in case data gets divided into multiple frames.