CROSS-REFERENCE TO RELATED APPLICATIONS AND PRIORITY
[001] The present application does not claim priority from any patent application.
TECHNICAL FIELD
[002] The present disclosure in general relates to the field of hardware logic/ electronic design/ digital circuits verification. More particularly, the present invention relates to control the course of a functional simulation of Design Under Verification or System Under Verification (DUV/SUV) based on user inputs.
BACKGROUND [003] Integrated Circuit Design (ICD) or Chip Design is a branch of electronics engineering. ICD deals with encompassing the particular logic and circuit design techniques required for designing integrated circuits, or ICs. Initially, the integrated circuits contained only a few transistors. However, the number of transistors in the integrated circuits has increased dramatically since then. The term "large scale integration" (LSI) was first used to describe this theoretical concept, which further gave rise to the terms "small-scale integration" (SSI), "medium-scale integration" (MSI), "very-large-scale integration" (VLSI), and "ultra-large-scale integration" (ULSI). The development of VLSI started with hundreds of thousands of transistors in the early 1980s, and has continued beyond ten billion transistors as of now. [004] Modern ICs are immensely complicated. The complexity of modern IC design and market pressure for producing designs rapidly has led to the extensive use of automated design tools in process of IC designing. In short, the design of an IC using Electronic Design Automation (EDA) is the process of design, verification and testing of the instructions that the IC has to carry out. [005] Electronic Design Automation (EDA) and Electronic Computer-Aided Design (ECAD) is a category of tools that is used to design electronic systems such as integrated circuits as well as printed circuit boards. Designers use these tools that work together in a flow to design and analyze the entire semiconductor chips. EDA tools are essential for designing modern semiconductor chips which have billions of components. The EDA tools help chip design with programming languages that compiled them to
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silicon. Due to immediate result, there was a considerable increase in the complexity of the chips that could be designed, with improved access to design verification tools that are based on Logic Simulation. A chip designed using this process is easier to layout and more likely to function correctly, since the design of the chip could be simulated more thoroughly prior to construction. Although the languages and tools have evolved, this general approach of specifying the desired behaviour in a textual programming language and letting the tools derive the detailed physical design has remained the basis of digital IC design even today. [006] A Simulation (or "sim") is an attempt to model a real-life or hypothetical situation on a computer to study the working of the system. Predictions may be made about the behaviour of the system, by changing variables in the simulation. It is a tool to virtually investigate the behaviour of the system under study. [007] A Logic simulation is the use of simulation software for predicting the behaviour of digital circuits and Hardware Description Languages (HDL). It simulates the logic before it is built. Simulations have the advantage of providing a familiar look and feel to the user in that it is constructed from the same language and symbols used in design. Simulation is a natural way for the designer to get feedback on their design, by allowing the user to interact directly with the design. Logic simulation may be used as part of the Functional Verification process in designing hardware.
[008] Functional verification is the process followed for verifying whether the logic design conforms to the design specification. In everyday terms, functional verification asserts whether the proposed design do what is intended. This is a complex task, and takes the majority of time and effort in largest electronic system design projects.
[009] Hardware Description language (HDL) is a specialized computer language used for describing the structure and behaviour of electronic circuits, and most commonly, digital logic circuits. A hardware description language enables a precise, formal description of an electronic circuit which allows for the automated analysis and simulation of an electronic circuit. A hardware description language is much like a programming language such as C Programming language. HDL is a textual description language consisting of expressions, statements and control structures. One important difference between most programming languages and HDLs is that HDLs
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explicitly include the notion of time. The key advantage of a HDL, when used for systems design, is that it allows the behaviour of the required system to be described (modelled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires). With time, VHDL and Verilog emerged as the dominant HDLs in the electronics industry, while older and less capable HDLs gradually disappeared. Over the years, much effort has been invested in improving HDLs. The latest iteration of Verilog, formally known as System Verilog, introduces many new features (classes, random variables, and properties/assertions) to address the growing need for better testbench randomization, design hierarchy, and reuse. [0010] A testbench is an (often virtual) environment used to verify the correctness or soundness of a design or model. In the context of firmware or hardware engineering, a testbench refers to an environment in which the design/system/product under development is verified with the aid of software and hardware tools. The suite of verification tools is designed specifically for the design/system/product under verification. Testbench, commonly referred as verification environment (or just environment) contains a set of components such as bus functional models (BFMs), bus monitors, memory modules, and interconnect of such components with the Design Under Verification (DUV).
[0011] A simulation environment is typically composed of several types of components. The Generator generates input vectors that are used to search for anomalies that exist between the intent (specifications) and the implementation (HDL Code). Modern generators create directed-random and random stimuli that are statistically driven to verify random parts of the design. The randomness is important to achieve a high distribution over the huge space of the available input stimuli. To this end, users of these generators intentionally under-specify the requirements for the generated tests. It is the role of the generator to randomly fill this gap. This allows the generator to create inputs that reveal bugs not being searched by the user. Generators also bias the stimuli towards design corner cases to further stress the logic. Biasing and randomness serve different goals and there are trade-offs between them. As a result, different generators have a different mix of these characteristics. Since the input for the design must be valid (legal) and many targets (such as biasing) should be maintained, many generators use the constraint satisfaction problem (CSP) technique to solve the complex verification
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requirements. The legality of the design inputs and the biasing arsenal are modelled. The model-based generators use this model to produce the correct stimuli for the target design.
[0012] Drivers translate the stimuli produced by the generator into the actual inputs for the design under verification. Generators create inputs at a high level of abstraction, as transactions and drivers convert this input into actual design inputs as defined in the specification of the design's interface.
[0013] A Monitor converts the state of the design and its outputs to a transaction abstraction level so it can be stored in a scoreboard’s database to be checked later on.
[0014] The Scoreboard/Checker validates that the contents of the scoreboard are legal. There are cases where the generator creates expected results, in addition to the inputs. In these cases, the checker must validate that the actual results match the expected ones.
[0015] An Arbitration Manager is configured to manage all the above components together.
[0016] The simulator produces the outputs of the design, based on the design’s current state (the state of the flip-flops) and the injected inputs. The simulator has a description of the design net-list. This description is created by synthesizing the HDL to a low gate level net-list. [0017] Simulation based verification is widely used to "simulate" the design, since this method scales up very easily. Stimulus is targeted to exercise each line in the HDL code. A testbench is built to functionally verify the design by providing meaningful scenarios to check that given certain input, the design performs to the specification.
[0018] The level of effort required to debug and then verify the design is proportional to the maturity of the design. That is, early in the design’s life, bugs and incorrect behaviour are usually found quickly. As the design matures, the simulation requires more time and resources to run, and errors will take progressively longer to be found.
[0019] One of the most critical tasks in developing a new hardware such as Integrated Circuit (IC) chips, Field-Programmable Gate Arrays (FPGA), Application-Specific Integrated Circuits (ASIC), System On Chips (SOC) etc. is to verify them for different
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design/function/performance specifications. These specifications may be predefined by the customer of the chips or can be an industry standard too. Another challenge faced by the verification team of this hardware is to debug the failures (if any) that arises during the process of verification using the log file(s) and identify the root cause of the failure.
[0020] An input packets entering a Design Under Verification /System Under Verification (DUV/SUV) verifies the DUV/SUV by performing a simulation. However, the simulation may run for a long time before its completion. In this case, an error may occur at certain point during the simulation. In case of occurrence of the errors, a user may have to re-run the entire simulation from the initial point, after fixing the errors. Also, the user might want to make changes in the simulation at the certain point or to control the simulation. In this case, the user may have to wait for the completion of the simulation. Once the simulation completes, the user may make changes in the simulation again and then re-run the simulation. Thus, the user might have to spend lot of time till the completion of the simulation. Currently, there is no standard way to control this kind of simulation debug cycle and reduce the human effort spent.
SUMMARY
[0021] This summary is provided to introduce aspects related to systems and methods for interactively controlling the course of a functional simulation and the aspects are further described below in the detailed description. This summary is not intended to identify essential features of the claimed subject matter nor is it intended for use in determining or limiting the scope of the claimed subject matter.
[0022] In one embodiment, a system for interactively controlling the course of a functional simulation based on user inputs is illustrated. The system may comprise a Design Under Verification or System Under Verification (DUV/ SUV) and a testbench configured to communicate with the DUV/ SUV. The DUV/ SUV may be configured to process a set of input data/packets generated by a “stimulus generation unit” of the testbench. The set of input data/packets indicates a stimulus. The set of input data/packets may be configured to simulate and verify the DUV/SUV based on a target test case, from a set of test cases. The testbench further comprises an “event identification unit”, an “event notification unit” and a “stimulus modifier unit”. The “event identification unit” may be configured to identify occurrence of an event, at runtime, during simulation
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associated with the target test case. The “event identification unit” may be further configured to pause the simulation upon identification of the event. The “event notification unit” of the testbench may be configured to transmit a message to a user. The message may indicate the occurrence of the event at runtime during the simulation. The “event notification unit” may be further configured to receive one or more user inputs. The one or more inputs indicate response to the message. The “stimulus modifier unit” of the testbench may be configured to update the “stimulus generation unit” to generate the new stimulus based on the one or more user inputs received at the “event notification unit”. The “stimulus modifier unit” may be further configured to resume the paused simulation, thereby interactively controlling the course of a functional simulation of DUV/SUV.
[0023] In another embodiment, a method for interactively controlling the course of a functional simulation based on user inputs is illustrated. The method may comprise generating, by a “stimulus generation unit”, a set of input data/packets as a stimulus to verify a Design Under Verification or System Under Verification (DUV/ SUV) based on a target test case, from a set of test cases. The method may further comprise identifying, by an “event identification unit”, an event at runtime during simulation associated with the target test case. The simulation, associated with the target test case, may be paused upon identification of the event. Further, the method may comprise transmitting, by an “event notification unit”, a message to a user. The message may indicate occurrence of the event. Furthermore, the method may comprise receiving, by the “event notification unit”, one or more user inputs in response to the message. The method may further comprise updating the “stimulus generation unit”, by a “stimulus modifier unit”, to generate a new stimulus based on the one or more user inputs. Further, the method may comprise resuming, by the “stimulus modifier unit”, the paused simulation, with the new stimulus based on the one or more user inputs, thereby interactively controlling the course of a functional simulation of DUV/SUV.
[0024] In yet another implementation, a computer program product having embodied computer program for interactively controlling the course of a functional simulation based on user inputs is disclosed. In one embodiment, the program may comprise a program code for generating a set of input data/packets as a stimulus to verify a Design Under Verification or System Under Verification (DUV/SUV) based on a target test case
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from a set of test cases. Further, the program may comprise a program code for identifying occurrence of an event, at runtime, during simulation associated with the target test case. The simulation, associated with the target test case, may be paused upon identification of the event. Furthermore, the program may comprise a program code for transmitting a message to a user. The message may indicate occurrence of the event. The program may further comprise a program code for receiving one or more user inputs in response to the message. Further, the program may comprise a program code for generating a new stimulus based on the one or more user inputs. Furthermore, the program may comprise a program code for resuming the paused simulation, with the new stimulus based on the one or more user inputs, thereby interactively controlling the course of a functional simulation of DUV/SUV.
BRIEF DESCRIPTION OF DRAWINGS
[0025] The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to refer like features and components.
[0026] Figure 1 illustrates an overview of a system configured to control the course of a functional simulation of Design Under Verification or a System Under Verification (DUV/ SUV), in accordance with an embodiment of the present subject matter.
[0027] Figure 2 illustrates components of the system for interactively controlling the course of a functional simulation of DUV/SUV, in accordance with an embodiment of the present subject matter.
[0028] Figure 3 illustrates a flow diagram to control the course of a functional simulation of DUV/SUV, in accordance with an embodiment of the present subject matter.
DETAILED DESCRIPTION
[0029] The present system facilitates/ provides the means for interactively controlling the course of a functional simulation of Design Under Verification/ System Under Verification (DUV/ SUV). The course of the functional simulation of DUV/SUV may be
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controlled based on the user inputs. The DUV/ SUV may correspond to a design of an electronic circuit or a design of an integrated chip written in a Hardware Description Language (HDL). The system comprises a DUV/SUV and a testbench configured to communicate with the DUV/SUV.
[0030] In one embodiment, the testbench may enable a “stimulus generation unit” to generate a set of input data/packets. The set of input data/packets may correspond to a stimulus. The set of input data/packets may be configured to verify and simulate the DUV/ SUV based on a target test case, from a set of test cases. In one aspect, the DUV/SUV may be configured to process the set of input data/packets received from the testbench. Further, the testbench may enable an “event identification unit” to identify an event at runtime during the simulation, associated with a target test case. The event may be associated with a user defined condition at runtime of the simulation. Further, the event may be a predefined error, a pre-defined number of errors, a predefined number of stimulus generated, a normal completion of transactions and the like. Upon identifying the event, the “event identification unit” may pause the simulation.
[0031] Once the simulation is paused, the testbench may enable an “event notification unit”. The “event notification unit” may be configured to transmit a message to a user. In one embodiment, the message may indicate occurrence of the event at runtime during the simulation. In another embodiment, the message may correspond to a request for one or more user inputs at runtime during the simulation. Further, the “event notification unit” may be configured to wait for a pre-defined time interval to receive the one or more user inputs. The one or more inputs are received using either a “$system” system function call or a “C-DPI (Direct Programming Interface)” function call in a System Verilog code. In one embodiment, in case if no user input is received before the pre-defined time interval, the “event notification unit” may be further configured to end the simulation.
[0032] Upon receiving the one or more user inputs, the testbench may enable the “stimulus modifier unit” to update the “stimulus generation unit” to generate a new stimulus based on the one or more inputs. Once the new stimulus is generated, the “stimulus modifier unit” may be further configured to resume the paused simulation. In other words, the “stimulus modifier unit” may be configured to update the “stimulus generation unit” to generate a new simulation sequence on-the-fly and pass the new
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simulation sequence to the paused simulation to resume it. In one aspect, the new sequence may correspond to the new stimulus.
[0033] Referring now to Figure 1, an overview of a system 102 configured to control the course of a functional simulation of Design Under Verification or System Under Verification (DUV/ SUV) 104 is illustrated. The system 102 includes a testbench 106 configured to communicate with a DUV/ SUV 104. Further, the testbench 106 may be connected to a database 110. In one embodiment, the DUV/SUV may process a set of input data/packets. The processing of the set of input data/packets may correspond to simulation of a target test case, from a set of test cases.
[0034] In one embodiment, the testbench 106 is configured to generate and transmit a number of input data/packets to the DUV/SUV 104 in order to verify the DUV/SUV 104 based on the target test case, from the set of test cases.
[0035] In one embodiment, the testbench 106 may be configured to identify an event. Once the event is identified, the testbench 106 may be configured to pause the simulation, associated with the target test case. Further, the testbench 106 may transmit a message to a user. The message may indicate the occurrence of the event. Furthermore, the testbench 106 may receive one or more user inputs in response to the message. In one embodiment, the testbench 106 may wait for a pre-defined time interval to receive the one or more user inputs.
[0036] Once the one or more user inputs are received, the testbench 106 may generate a new stimulus based on the one or more user inputs. The new stimulus may correspond to new course of the simulation. The testbench 106 may resume the paused simulation, associated with the target test case, with the new stimulus based on the one or more user inputs. In one aspect, the course of the simulation may change due to the one or more user inputs. In one embodiment, if the one or more user inputs are not received before the pre-defined time interval, the testbench 106 may terminate the paused simulation.
[0037] In one embodiment, the testbench 106 may generate log data based on the simulation of the target test case. Further, the testbench 106 may store the log data in the database 110. The process of controlling the course of the functional simulation of Device Under Verification or System Under Verification (DUV/ SUV) 104 is further elaborated with respect to figure 2.
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[0038] Referring now to Figure 2, the system 102 is illustrated in accordance with an embodiment of the present subject matter. In one embodiment, the system 102 comprises the DUV/ SUV 104 connected to the testbench 106. Further, the testbench 106 may be connected to the database 110. The testbench 106 may include a “stimulus generation unit” 208, an “event identification unit” 210, an “event notification unit” 212, a “stimulus modifier unit” 214.
[0039] In one embodiment, based on the configuration inputs provided by a user, the “stimulus generation unit” 208 may be configured to generate a set of input data/packets. The set of input data/packets may correspond to a stimulus. Once the set of input data/packets is generated, the testbench 106 may be configured to transmit the set of input data/packets to the DUV/ SUV 104. In one implementation, the “stimulus generation unit” 208 of the testbench 106 may transmit the set of input data/packets to the DUV/SUV 104. The DUV/ SUV 104 may be configured to process the set of input data/packets. The processing of the set of input data/packets may correspond to simulation, associated with a target test case, from a set of test cases.
[0040] Further, the “event identification unit” 210 may be configured to identify an event at runtime during the simulation. The event may be any user defined condition like a predefined error, a predefined number of errors, a predefined number of stimulus generated, a normal completion of transactions and the like. Once the event is identified, the “event identification unit” 210 may pause the simulation associated with the target test case.
[0041] Once the simulation is paused, the “event notification unit” 212 may be configured to transmit a message to a user. The message may be an email message. The message may indicate the occurrence of the event at runtime during the simulation. In one aspect, the message may be configured to inform the user regarding the occurrence of the event. In another aspect, the message may correspond to a request for receiving one or more inputs from the user.
[0042] Once the message is transmitted, the “event notification unit” 212 may be configured to wait, for a pre-defined time interval, to receive the one or more user inputs from the user. In one aspect, the “event notification unit” 212 may receive the one or more user inputs before the pre-defined time interval. The one or more user inputs may be
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received as a response to the message. In one embodiment, the “event notification unit” 212 may receive the one or more user inputs using either a “$system” system function or a “C-DPI (Direct programming Interface)” function. The one or more user inputs may correspond to read all error registers, write to a specific register, read from a specific register, read status registers, read counters and the like. In another aspect, if no inputs are received from the user before the pre-defined time interval, the “event notification unit” 212 may be further configured to end the paused simulation associated with the target test case.
[0043] In one embodiment, the “event notification unit” 212 may use the “$system” system function to receive the one or more user inputs. The “$system” system function may invoke a Linux command “read”. In one example, the “event notification unit” 212 may receive the user input using a format “rd_reg