Claims:1. A system (100) for calibrating a voltage control oscillator (VCO), the system comprising:
a voltage control oscillator (VCO) (110) integrated in a phase-locked loop (PLL), the VCO comprising:
a switched VCO core (202) having one or more inductors (206) of different values; and
a switched capacitor (204) having one or more capacitors (208) of different values; and
a microcontroller (114) coupled to the PLL, the microcontroller configured to:
perform verification, upon activation of the PLL at a first time interval to perform calibration;
initialize any or a combination of dividers (104, 112) and charge pump current;
perform selection of any or a combination of switched VCO core, switched capacitors and digital to analogue (DAC) current, wherein the selection of switched VCO core, switched capacitors and DAC current is performed to obtain desired frequency with optimum phase noise; and
store, in a memory operatively coupled to the microcontroller, a set of values of the calibrated data,
wherein upon activation of the PLL at a second time interval, the stored set of values are loaded in an appropriate register of the PLL to facilitate agile frequency switching with the lowest phase noise.
2. The system as claimed in claim 1, wherein the optimized set of values is loaded in the appropriate register of PLL without the overhead to facilitate in faster and low phase noise signal.
3. The system as claimed in claim 1, wherein the one-time calibration is used to extract the VCO setting and store in the memory of the microcontroller to achieve the frequency agility.
4. The system as claimed in claim 1, wherein the dividers comprise reference frequency divider (104) and an integer-fractional divider (112), wherein the reference frequency divider (104) coupled to a reference source (102) to divide the received reference frequency signal to generate a first output signal, and the integer-fractional divider (112) coupled to the VCO to generate a second output signal.
5. The system as claimed in claim 1, wherein the PLL comprises a phase frequency detector (PFD) (106) that compares the first output signal of the reference frequency divider (104) and the second output signal of the integer-fractional divider (112) to generate an error signal, the error signal pertaining to phase difference of the first output signal and the second output signal.
6. The system as claimed in claim 1, wherein the phase frequency detector comprises the charge pump that generates an amount of charge equivalent to the error signal provided by the PFD.
7. The system as claimed in claim 1, wherein a loop filter (108) coupled to the PFD, the loop filter filters the generated error signal.
8. The system as claimed in claim 1, wherein the VCO (110) coupled to the loop filter, the VCO receives the filtered signal called tuning voltage (Vtune) from the loop filter to generate the final output signal.
9. The system as claimed in claim 1, wherein the switched VCO core (202), switched capacitor (204), a fixed capacitor (210) and varactor diode-based capacitor (212) are configured in the VCO (110).
10. A method (400) for calibrating a voltage control oscillator (VCO), the method comprising:
performing (402), at a microcontroller, verification, upon the activation of phase-locked loop (PLL) at a first time interval to perform calibration, the VCO integrated in the PLL, wherein the VCO comprises a switched VCO core having one or more inductors of different values; and a switched capacitors having one or more capacitors of different values;
initializing (404), at the microcontroller any or a combination of dividers and charge pump current;
performing (406), at the microcontroller, selection of any or a combination of switched VCO core, switched capacitors and digital to analogue (DAC) current, wherein the selection of switched VCO core, switched capacitors and DAC current is performed to obtain desired frequency with optimum phase noise; and
storing (408), in a memory operatively coupled to the microcontroller, a set of values of the calibrated data, wherein upon activation of the PLL in a second time interval, the stored set of values are loaded in appropriate registers of the PLL, to facilitate agile frequency switching with the lowest phase noise.
, Description:TECHNICAL FIELD
[001] The present disclosure relates, in general, to phase lock loops (PLL) circuits and more specifically, relates to a system and method for low phase noise and agile variable frequency synthesizer.

BACKGROUND
[002] Frequency source is one of the critical subsystems in communication, radar, electronic warfare and navigation system. The change in technology requires a highly precise, stable, tuneable, and agile with very good spectral purity carrier signal for the transmitter and local oscillator signal for the receivers. The performance of the frequency source is to be maintained under all the operational conditions which in turn provide improved performance of the system in terms of sensitivity, high dynamic range and operational flexibility. To build a low phase noise, fast switching and agile frequency source, a lot of techniques, circuits and programming algorithms have been used by means of optimising the loop filters, clock speed, calibration techniques and switching of voltage control oscillators (VCOs) and the like.
[003] Few existing systems in the field of frequency source may include calibration techniques for frequency synthesizers, which calibrate VCO and thus to get the settings to lock at the desired frequency. This method uses external calibration unit hardware which requires the N divider output and R divider output as input to it. However, the VCO is required to be calibrated each time before switching the frequency. Another technique may use integrated VCO having an improved tuning range over the process and temperature variations, the integrated VCO for the improved tuning range and stability. This method is implemented at the substrate level by controlling the tuning voltage of VCO.
[004] Further, another technique may include a method and system for improving frequency source frequency accuracy and frequency stability. A time average frequency direct period synthesis (TAF–DPS) based circuits and a method to improve the electronic system’s frequency accuracy and enhance its stability is disclosed in this application. This system creates circuit architecture and a calculation scheme for compensating the source's frequency error. This method uses field programmable gate array (FPGA)/application specific integrated circuit (ASIC). However, the existing systems may require multiple time calibration, additional hardware, circuits and semiconductor level substrate as mentioned above.
[005] Frequency synthesizers are an integral part of any communication or radar systems for any application. It is expected of these sub-systems to have an agile frequency switching capability with the lowest possible phase noise. The components used in the frequency synthesizers are very much susceptible to environmental parameters such as temperature and random vibrations. To mitigate these problems in frequency generation, various existing methods are being used. One such existing method is to let the auto-tuning of the VCO happen each time the frequency is hopped, however, this can adversely affect the lock time of the PLL. Thus, the frequency switching time can be large which is unacceptable for the hard time systems.
[006] Therefore, there is a need in the art to provide a means that enables one-time calibration and tuning in a distinct board and achieves low switching time with optimum phase noise of the signal.

OBJECTS OF THE PRESENT DISCLOSURE
[007] An object of the present disclosure relates, in general, to phase lock loops (PLL) circuits and more specifically, relates to a system and method for low phase noise and agile variable frequency synthesizer.
[008] Another object of the present disclosure achieves low phase noise with fast frequency switching over the temperature by self-calibration and programming.
[009] Another object of the present disclosure provides a system that reduces the requirement of extra resources other than the basic blocks of PLL frequency synthesizers.
[0010] Another object of the present disclosure provides self-calibration of the PLL by micro-controller.
[0011] Another object of the present disclosure provides a system that enables one-time calibration, optimization of overheads of programming registers to enhance and reduce stabilization and lock time of PLL.
[0012] Yet another object of the present disclosure achieves uniform performance across production lots of PLL chips having habitual fabrication tolerances.

SUMMARY
[0013] The present disclosure relates, in general, to phase lock loops (PLL) circuits and more specifically, relates to a system and method for low phase noise and agile variable frequency synthesizer. The frequency synthesizers are required in almost all communication or radar application. It is very important to have a very stable and low phase noise source, which can generate the signal under harsh environmental conditions without any degradation of the performance. A method and flow discussed in the present disclosure provides a flow to self-calibrate a voltage control oscillator (VCO) and get the VCO settings to achieve low switching time along with the optimum good phase noise without using any extra hardware other than the basic PLL synthesizers building blocks.
[0014] In an aspect, the present disclosure provides a system for calibrating the VCO, the system including a voltage control oscillator (VCO) integrated in a phase-locked loop (PLL) chip/ integrated circuit (IC), the VCO including a switched VCO core having one or more inductors of different values; and a switched capacitor bank having one or more capacitors of different values; and a microcontroller coupled to the PLL, the microcontroller configured to verify the activation of the PLL at a first time interval to perform calibration, initialize any or a combination of dividers and charge pump current, perform selection of any or a combination of switched VCO core, switched capacitors and digital to analogue (DAC) current, wherein the selection of switched VCO core, switched capacitors and DAC current is performed to obtain desired frequency with optimum phase noise; and store, in a memory operatively coupled to the microcontroller, a set of values of the calibrated data, wherein upon activation of the PLL at a second time interval, the stored set of values are loaded in appropriate registers of the PLL to facilitate agile frequency switching with the lowest phase noise.
[0015] In an embodiment, the optimized set of values is loaded in the appropriate register of PLL without the overhead to facilitate in faster and low phase noise signal.
[0016] In another embodiment, the one-time calibration is used to extract the VCO setting and store in the memory of the microcontroller to achieve the frequency agility.
[0017] In another embodiment, the dividers include reference frequency divider and an integer-fractional divider, wherein the reference frequency divider coupled to a reference source to divide the received reference frequency signal to generate a first output signal, and the integer-fractional divider coupled to the VCO to generate a second output signal.
[0018] In another embodiment, the PLL comprises a phase frequency detector (PFD) compares the first output signal of the reference frequency divider and the second output signal of an integer-fractional divider to generate an error signal, the error signal pertaining to phase difference of the first output signal and the second output signal.
[0019] In another embodiment, the phase frequency detector comprises the charge pump that generates an amount of charge equivalent to the error signal provided by the PFD.
[0020] In another embodiment, PLL comprises a loop filter coupled to the PFD, the loop filter filters the generated error signal.
[0021] In another embodiment, a VCO coupled to the loop filter, the VCO receives the filtered signal called tuning voltage (Vtune) from the loop filter to generate the final output signal.
[0022] In another embodiment, the switched VCO core, the switched capacitor, fixed capacitor and varactor diode-based capacitor are configured in the VCO.
[0023] In an aspect, the present disclosure provides a method for calibrating a voltage control oscillator (VCO), the method includes verifying, at a microcontroller, the activation of phase-locked loop (PLL) at a first time interval to perform calibration, the VCO integrated in the PLL, wherein the VCO comprises a switched VCO core having one or more inductors of different values; and a switched capacitors bank having one or more capacitors of different values, initializing, at the microcontroller any or a combination of dividers and charge pump current, performing, at the microcontroller, selection of any or a combination of switched VCO core, switched capacitors and digital to analogue (DAC) current, wherein the selection of switched VCO core, switched capacitors and DAC current is performed to obtain desired frequency with optimum phase noise; and storing, in a memory operatively coupled to the microcontroller, a set of values of the calibrated data, wherein upon activation of the PLL in a second time interval, the stored set of values are loaded in appropriate registers of the PLL, to facilitate agile frequency switching with the lowest phase noise.
[0024] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The following drawings form part of the present specification and are included to further illustrate aspects of the present disclosure. The disclosure may be better understood by reference to the drawings in combination with the detailed description of the specific embodiments presented herein.
[0026] FIG. 1A illustrates an exemplary functional component of phase lock loop (PLL) based frequency synthesizer, in accordance with an embodiment of the present disclosure.
[0027] FIG. 1B illustrates an exemplary view of tank circuit of the VCO, in accordance with an embodiment of the present disclosure.
[0028] FIG. 2 illustrates an exemplary flow chart of the calibration process of the VCO, in accordance with an embodiment of the present disclosure.
[0029] FIG. 3A illustrates an exemplary graphical view of the phase noise performance by using the VCO settings without the calibration feature, in accordance with an embodiment of the present disclosure.
[0030] FIG. 3B illustrates an exemplary graphical view of the phase noise performance by using the VCO settings with the calibration feature, in accordance with an embodiment of the present disclosure.
[0031] FIG. 4 illustrates an exemplary flow diagram of the method for calibrating a voltage control oscillator (VCO), in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0032] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0033] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0034] The present disclosure relates, in general, to phase lock loops (PLL) circuits and more specifically, relates to a system and method for low phase noise and agile variable frequency synthesizer. The present disclosure achieves low phase noise with fast frequency switching over the temperature by self-calibration and programming. The self-calibration of the PLL is performed by a microcontroller.
[0035] The frequency synthesizers are required in almost all communication or radar application. It is very important to have a very stable and low phase noise source, which can generate the signal under harsh environmental conditions without any degradation of the performance. A method and flow discussed in the present disclosure provides a flow to self-calibrate a voltage control oscillator (VCO) and get the VCO settings to achieve low switching time along with the optimum good phase noise without using any extra hardware other than the basic PLL synthesizers building blocks. The present disclosure can be described in enabling detail in the following examples, which may represent more than one embodiment of the present disclosure.
[0036] FIG. 1A illustrates an exemplary functional component of phase lock loop (PLL) based frequency synthesizer, in accordance with an embodiment of the present disclosure.
[0037] Referring to FIG. 1A, PLL based frequency synthesizer 100 (also referred to as system 100, herein) configured to achieve low phase noise with fast frequency switching over the temperature by self-calibration and programming. The system 100 can include reference source 102, reference frequency divider 104 also interchangeably referred to as R divider 104, phase-frequency detector (PFD) 106, loop filter 108, VCO 110, integer-fractional divider 112 also interchangeably referred to as N divider, and a microcontroller 114. The present disclosure offers to achieve uniform performance across production lots of PLL chips having habitual fabrication tolerances.
[0038] Frequency synthesizers are required in almost all communication or radar application. It is very important to have a very stable and low phase noise source, which can generate the signal under harsh environmental conditions without any degradation of the performance. A method and flow discussed in the present disclosure provides a flow to self-calibrate the VCO and get the VCO settings to achieve low switching time along with the optimum good phase noise without using any extra hardware other than the basic PLL synthesizers building blocks.
[0039] In an exemplary embodiment, reference frequency divider 104, integer-fractional divider 112, PFD 106, and VCO 110 are part of the integrated PLL chip. The reference source 102, loop filter 108 and microcontroller 114 are external parts. In an embodiment, the reference source 102 configured to generate a highly stable and low phase noise frequency signal which is of very low frequency as compared to the final signal. The reference frequency divider 104 configured to divide the reference frequency to meet the resolution required to generate the final signal at VCO 110. In another embodiment, the reference frequency divider 104 coupled to the reference source 102 to divide the received reference frequency signal to generate a first output signal and the integer-fractional divider 112 coupled to the VCO 110 to generate a second output signal. In another embodiment, the PFD 106 can compare the first output signal of the reference frequency divider 104 and the second output signal of integer-fractional divider 112 and can generate an error signal with respect to the phase difference among the signals. A charge pump generates an amount of charge equivalent to the error signal provided by the PFD 106. The error signal generated by the PFD 106 is filtered by the loop filter 108 and is fed to the VCO 110 as the tuning voltage to generate the final output signal. VCO 110 coupled to the loop filter, the VCO receives the filtered signal called tuning voltage (Vtune) from the loop filter to generate the final output signal.
[0040] The microcontroller 114 can be used to control the settings of N divider 112, R divider 104 and various other settings of the PLL chip.
[0041] In an exemplary implementation, the VCO 110 integrated in the PLL 100, where the VCO 110 is a broadband oscillator having switched VCO core 202 having one or more inductors (206-1, 206-2 to 206-n (which are collectively referred to as 206 hereinafter, and are explained in FIG. 1B in detail below)) of different values and a switched capacitor bank 204 also interchangeably referred to as switched capacitors 204 having one or more capacitors (208-1, 208-2 to 208-n (which are collectively referred to as 208 hereinafter, and are explained in FIG. 1B in detail below)) of different values (as illustrated in FIG. 1B and described in detail below). The microcontroller 114 coupled to the PLL, the microcontroller 110 configured to perform verification, upon activation of the PLL at a first time interval to perform calibration. The microcontroller 114 initializes any or a combination of dividers and charge pump current and perform a selection of any or a combination of switched VCO core 202, switched capacitors 204 and digital to analogue (DAC) current, wherein the selection of switched VCO core 202, switched capacitors 204 and DAC current is performed to obtain desired frequency with optimum phase noise.
[0042] In another embodiment, the set of values of the calibrated data are stored in a memory coupled to the microcontroller, wherein upon activation of the PLL at a second time interval, the stored set of values are loaded in appropriate registers of the PLL to facilitate agile frequency switching with the lowest phase noise.
[0043] FIG. 1B illustrates an exemplary view of the tank circuit of the VCO, in accordance with an embodiment of the present disclosure. As shown in FIG. 1B, the VCO 110 is the broadband oscillator having switched VCO core 202 and switched capacitor bank 204. In an embodiment, the switched VCO core 202 can include one or more inductors 206 of different values. In another embodiment, the switched capacitor bank 204 can include different values of one or more capacitors 208. The output frequency band (m x n) is chosen based on the combination of VCO cores 202 of n numbers and switched capacitor bank 204 of m numbers and the fixed capacitor 210.
[0044] The fine-tuning of frequency within the band is achieved by varying the small capacitance value of varactor diode-based capacitor 212 by applying voltage. The switched VCO core 202, switched capacitor bank 204, fixed capacitor 210 and varactor diode-based capacitor 212 are internal to the VCO 110, which is and integrated part of the PLL chip.
[0045] In military and aerospace applications, the error tolerance is next to none and the variation of the environmental parameters is large. In these conditions it is required to have a such a system which can hold for the complete mission time without any degradation in its performance. Frequency synthesizers are integral part of any communication or radar systems for any of the application. It is expected of these sub-systems to have an agile frequency switching capability with the lowest possible phase noise. The components used in the frequency synthesizers are very much susceptible to the environmental parameters such as temperature and random vibrations. To mitigate these problems in the frequency generation, various existing methods are used. One such existing method is to let the auto-tuning of the VCO happen each time the frequency is hopped, however this method can adversely affect the lock time of the PLL. Thus, the frequency switching time can be large which is unacceptable for the hard time systems. The present disclosure addresses the above-mentioned problem by achieving highest capability of the good phase noise.
[0046] The embodiments of the present disclosure described above provide several advantages. One or more of the embodiments provide achieves low phase noise with fast frequency switching over the temperature by self-calibration and programming. System 100 reduces the requirement of extra resources other than the basic blocks of PLL frequency synthesizers. The present disclosure provides self-calibration of the PLL by micro-controller 114. System 100 enables one-time calibration, optimization of overheads of programming registers to enhance and reduce stabilization and lock time of PLL. Further, the present disclosure achieves uniform performance across production lots of PLL chips having habitual fabrication tolerances.
[0047] In another embodiment, the microprocessor may be micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, and/or any device that manipulates signals analog and/or digital based on operational instructions. Memory may be a single memory device or a plurality of memory devices. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, and/or any device that stores digital information.
[0048] FIG. 2 illustrates an exemplary flow chart of the calibration process 200 of the VCO, in accordance with an embodiment of the present disclosure.
[0049] As shown in FIG. 2, the flow chart depicts various steps towards the calibration procedure. At block 302, as soon as the PLL board is powered ON, verification is done for whether the board is ON for the first time, at block 304, if it is ON for the first time then the calibration process is started. At block 306, the initialization of dividers and charge pump current is carried out. At block 308, auto-calibration is done for the selection of the VCO cores, capacitors and DAC current, where the selection of core, capacitor bank of VCO and DAC current is performed to get desired frequency with optimum phase noise.
[0050] At block 310, wait for the calibration is necessary as the VCO takes more time to calibrate in no assist mode. At block 312, once the calibration is done the read back operation is carried out for VCO settings and at block 314, the read back registers stored in the flash memory of the microcontroller. At block 316, these stored values are kept in such a manner that it can be directly loaded into the PLL register whenever the PLL board is switched ON for the second time. The optimized register values are loaded in an appropriate register of PLL without the overhead to achieve a faster and low phase noise signal.
[0051] The one-time self-calibration technique used to read back the VCO setting and keep them in the flash memory of the microcontroller to achieve frequency agility. Thereby, reducing the overheads and calibration cycle time to get faster switching time. The calibration process is used to achieve uniform performance across production lots of PLL chips having habitual fabrication tolerances.
[0052] FIG. 3A illustrates an exemplary graphical view of the phase noise performance by using the VCO settings without the calibration feature, in accordance with an embodiment of the present disclosure. As shown on FIG. 3A, the frequency spectrum 318 and phase noise plot 320 of are the plots of PLL without the VCO calibration process. As illustrated in FIG. 3A. The frequency is not locked and it has multiple spurious and degraded phase noise performance.
[0053] FIG. 3B illustrates an exemplary graphical view of the phase noise performance by using the VCO settings with the calibration feature, in accordance with an embodiment of the present disclosure. As shown on FIG. 3B, the frequency spectrum 322 and phase noise plot 324 are the plots after the calibration process. Corresponding phase noise plot 324 is found to be stable and clean as compared to phase noise plot 320.
[0054] FIG. 4 illustrates an exemplary flow diagram of the method 400 for calibrating a voltage control oscillator (VCO), in accordance with an embodiment of the present disclosure.
[0055] Referring to FIG. 4, at block 402, the microcontroller can perform verification, upon the activation of phase-locked loop (PLL) at a first time interval to perform calibration, the VCO integrated in the PLL, wherein the VCO comprises a switched VCO core having one or more inductors of different values; and a switched capacitor having one or more capacitors of different values.
[0056] At block at block 404, initializing, at the microcontroller any or a combination of dividers and charge pump current. At block 406, performing, at the microcontroller, selection of any or a combination of switched VCO core, switched capacitors and digital to analogue (DAC) current, wherein the selection of switched VCO core, switched capacitors and DAC current is performed to obtain desired frequency with optimum phase noise.
[0057] At block 408, storing, in a memory operatively coupled to the microcontroller, a set of values of the calibrated data, wherein upon activation of the PLL in a second time interval, the stored set of values are loaded in appropriate registers of the PLL, to facilitate agile frequency switching with the lowest phase noise.
[0058] It will be apparent to those skilled in the art that the system 100 of the disclosure may be provided using some or all of the mentioned features and components without departing from the scope of the present disclosure. While various embodiments of the present disclosure have been illustrated and described herein, it will be clear that the disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the scope of the disclosure, as described in the claims.

ADVANTAGES OF THE PRESENT DISCLOSURE
[0059] The present disclosure achieves low phase noise with fast frequency switching over the temperature by self-calibration and programming.
[0060] The present disclosure provides a system that reduces the requirement of extra resources other than the basic blocks of PLL frequency synthesizers.
[0061] The present disclosure provides self-calibration of the PLL by micro-controller.
[0062] The present disclosure provides a system that enables onetime calibration, optimization of overheads of programming registers to enhance and reduce stabilization and lock time of PLL
[0063] The present disclosure achieves uniform performance across production lots of PLL chips having habitual fabrication tolerances.