Claims:WE CLAIM:
1. A method for memory initialization at a first circuitry, comprising:
identifying a portion of the first circuitry configured as a first memory device;
detecting a start of a power-off state for a power domain within the first circuitry including the first memory device;
performing a write operation to write data of a pre-determined pattern to the first memory device upon detecting the start of the power-off state; and
providing the data stored at the first memory device for a reading operation after the power-off state ends.

2. The method of claim 1, where the detection of a start of the power-off state comprises detecting a transition edge of at least one of: an isolation enable signal, a reset signal, and a power disable signal.

3. The method of claim 1, wherein the first circuitry is configured to emulate a behavior of a second circuitry that includes a second memory device, and wherein the pre-determined pattern is configured to emulate a content of the second memory device when a power domain including the second memory device transits from a power-on state to a power-off state.

4. The method of claim 3, wherein the first circuitry includes a field-programmable gate array (FPGA), and the second circuitry includes at least one of an application-specific integrated circuit (ASIC) and a system-on-chip (SoC).

5. The method of claim 1, further comprising:
determining a range of addresses associated with memory locations within the first memory device; and
writing the data to each of the memory locations associated with the range of addresses.

6. The method of claim 1, wherein the data is written to each of the memory locations sequentially.

7. The method of claim 1, wherein the first memory device includes a first port for the reading operation and a second port for the writing operation.

8. A first integrated circuit comprising a plurality of transistors configured to:
identify a portion of the first integrated circuit configured as a first memory device;
detect a start of a power-off state for a power domain within the first integrated circuit including the first memory device;
perform a write operation to write data of a pre-determined pattern to the first memory device upon detecting the start of the power-off state; and
provide the data stored at the first memory device for a reading operation after the power-off state ends.

9. The first integrated circuit of claim 8, where the detection of a start of the power-off state comprises detecting a transition edge of at least one of: an isolation enable signal, a reset signal, and a power disable signal.

10. The first integrated circuit of claim 8, wherein the first integrated circuit is configured to emulate a behavior of a second integrated circuit that includes a second memory device, and wherein the pre-determined pattern is configured to emulate a content of the second memory device when a power domain including the second memory device transits from a power-on state to a power-off state.

11. The first integrated circuit of claim 10, wherein the first integrated circuit includes a field-programmable gate array (FPGA), and the second integrated circuit includes an application-specific integrated circuit (ASIC).

12. The first integrated circuit of claim 8, further configured to:
determine a range of addresses associated with memory locations within the first memory device; and
write the data to each of the memory locations associated with the range of addresses.

13. The first integrated circuit of claim 8, wherein the data is written to each of the memory locations sequentially.

14. The first integrated circuit of claim 8, wherein the first memory device includes a first port for the reading operation and a second port for the writing operation.

Dated this 15th day of February, 2016

R Ramya Rao
Of K&S Partners
Agent for the Applicant
, Description:TECHNICAL FIELD
This disclosure relates generally to integrated circuit technologies, and more particularly, to methods and systems for memory initialization of an integrated circuit.