The present disclosure relates to noise reduction. In particular, the present disclosure pertains to a system and method for noise reduction in wireless communication utilizing an equalizer having an adaptive decision feedback equalizer and a decoder in a single format.

BACKGROUND OF THE INVENTION
The background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
Chip or microchip or integrated circuit is an electronic semiconductor wafer that includes thousands of capacitors, resistors, transistors and other electronic components. Currently, designing of electronic chip is much focused towards low processing power, smaller in size therefore covering low area, and high speed etc. Conventional systems use different segregated modules to perform various tasks such as differential amplifier, filters, noise reduction, recovering original data stream module, equalizer, and decoder are placed in an isolated form to execute various applications such as data stream communication over a channel.
Often, communication of data stream over a wireless channel suffers from signal distortion, noises e.g. intersymbol interference (ISI) and hence delivered data stream becomes less reliable. Noise is an unwanted data stream that is introduced in the original data stream (transmitted by a sender) and degrades the quality of originally transmitted signal. It becomes essential at receiver end to recover the original signal from the noisy signal.
Fig. 1 illustrates an existing communication system. Existing communication system utilizes two separate ICs, one being used as decision feedback equalizer 112, while other as a decoder 118. As illustrated, an encoder 102 encodes an input data stream bi and outputs encoded data stream Ci, at time index n, dn,o, dn,1….dn,m-1, an interleaver 104 (used in conjunction with error correcting codes) receives encoded Ci and performs interleaving operation over the Ci and provides interleaved bits output to a symbol mapping block 106 to group interleaved bits (xn) into one of 2m symbols, wherein xn can be transmitted to a ISI channel 108 together with additive white Gaussian noise (AWGN). Output of ISI channel 108 is provided to an adder 110 that also receives a noise sequence wn, wherein adder 110 performs addition operation on ISI channel 108 output stream and wn, and outputs ZN that is input into a decision feedback equalizer 112. Decision feedback equalizer (DFE) 112 that works in an iterative manner, comprises feed forward filter (HFF) 112-1, feed backward filter (HBF) 112-2, an adder 112-3 and a slicer 112-4. Channel output Zn can be expressed by equation:
(1)
Where, hk-baseband discrete time channel response
xN-interleaved bits
k-bit index
wN-noise sequence
In first iteration, adder 110 output Zn is input into a feed forward filter (HFF) 112-1, HFF 112-1 processes Zn and provides its output y_n^FFto an adder 112-3, wherein adder 112-3 after processing y_n^FF, outputs x ^_n. to a slicer 112-4. In next or second iteration, adder 112-3 receives input from HFF 112-1 and (HBF) 112-2, wherein HBF 112-2 processes received slicer 112-4 output. Adder 112-3, performs an add operation on received y_n^FF and HBF 112-2 output, and processes the added stream in a similar fashion as described in first iteration. Furthermore, DFE 112 output is fed into symbol de-mapping block 114 that demaps the stream and outputs series of consecutive bits. Symbol de-mapping block 114 provides consecutive bits output to a de-interleaver 116 that outputs C ^_i to a decoder 118 to decode the stream and output estimated bits . b ^_i. Estimated output x ^_n (estimated bits), computed by DFE is expressed as below equation:
(2)
Where k-bit index
H_k^FF - forward path transfer function
H_k^FB - reverse path transfer function
zn-k-updated channel output
x ~_(n-k)-past hard decision output from slicer
Conventional system, as depicted in Fig.1, uses separate equalizer and decoder based on hard output. Data stream transmission based upon the hard output cannot be changed or modified after processing. Existing system depicts that DFE 112 and decoder 118 are deployed on two separate chips, therefore separate area, processing power, more etc. are required, wherein separate requirements of both the chips degrades the overall system performance. Also, more number of ICs in the circuit enhances noise/ISI in a communication channel.
Thus there exist a need for utilizing a least mean square mechanism together with adaptive decision feedback equalizer to reduce bit error rate (BER)/noise. A single package of an equalizer and the decoder can be created to improve BER and enhance overall system performance. Furthermore, data stream transmission can be based upon the soft input soft output (SISO) and hence data stream can be controlled during processing.
As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all Markush groups used in the appended claims.

OBJECTS OF THE INVENTION
An object of the present disclosure is to overcome one or more disadvantages associated with conventional systems and methods for reducing bit error rate (BER)/noise/ISI.
Another object of the present disclosure is to create equalizer having an adaptive decision feedback equalizer and a decoder in a single format with a forward error correction to remove residual errors and to enable selective channel with time variation.
Another object of the present disclosure is to prevent bit overflow.
Another object of the present disclosure is to control output of soft input soft output (SISO) decoder.
Another object of the present disclosure is to utilize the single package and perform circuit operations with low power and also occupy lesser area.

SUMMARY
The present disclosure relates to noise reduction. In particular, the present disclosure pertains to a system and method for noise reduction in wireless communication utilizing an equalizer having an adaptive decision feedback equalizer and a decoder in a single format.
In an aspect, the present disclosures relates to an adaptive decision feedback equalizer for generating an improved signal by reducing a bit error rate (BER)/noise, the adaptive decision feedback equalizer includes: an output signal receive module configured to receive an output signal generated by a decoder and a property of a desired signal; an error determination module configured to determine presence of an error in the output signal by identifying the filter coefficient weights associated with the received output signal; a weight updation module configured to update the filter coefficient weights by using a Least Mean Square (LMS) algorithm to adapt with the property of the desired signal, wherein the LMS modifies the filter coefficient weights with gradient-based method to generate convergence of the received output signal with reduced bit error rate (BER)/noise; and a signal generation module configured to generate the improved signal having reduced bit error rate (BER)/noise.
In an aspect, the equalizer and the decoder can be in a single format with a forward error correction to remove residual errors and to enable selective channel with time variation.
In an aspect, the LMS algorithm can utilize an estimate of a gradient vector from the filter coefficient weights.
In an aspect, the decoder can be preferably a soft-in soft-out (SISO) decoder.
In an aspect, the equalizer can include a feed forward filter, a feedback filter, an adder, a log logarithmic ratio (LLR) mapper, and a de-interleaver.
In an aspect, the present disclosures relates to an adaptive decision feedback equalizer, for generating an improved signal by receiving an output signal generated by a decoder and a property of a desired signal; determining presence of an error in the output signal by identifying the filter coefficient weights associated with the received output signal; updating the filter coefficient weights by using a Least Mean Square (LMS) algorithm to adapt with the property of the desired signal, wherein the LMS modifies the filter coefficient weights with gradient-based method to generate convergence of the received output signal with reduced bit error rate (BER)/noise; and generating the improved signal having reduced bit error rate (BER)/noise.
Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF DRAWINGS
The diagrams are for illustration only, which thus is not a limitation of the present disclosure, and wherein:
FIG. 1 illustrates an existing communication system.
FIG. 2 illustrates a block diagram of a linear turbo equalizer in accordance with an embodiment of the present disclosure.
FIG. 3A illustrates least mean square architecture in accordance with an embodiment of the present disclosure.
FIG. 3B illustrates a block diagram of a transversal wiener filter in accordance with an embodiment of the present disclosure.
FIG. 4A illustrates an adaptive filter based on LMS in accordance with an embodiment of the present disclosure.
FIG. 4B illustrates exemplary functional modules for reducing BER/noise in accordance with an embodiment of the present disclosure.
FIGs. 5A and 5B illustrates an exemplary error calculation output in accordance with an embodiment of the present disclosure.
FIG. 6 illustrates an exemplary behavioral simulation result for weight updation module in accordance with an embodiment of the present disclosure.
FIG. 7A illustrates block diagram for LLR unit in accordance with an embodiment of the present disclosure.
FIG. 7B illustrates behavioral simulation result for SISO decoder in accordance with an embodiment of the present disclosure.
FIG. 7C illustrates RTL view of SISO Decoder accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF DRAWINGS
In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details.
Embodiments of the present invention include various steps, which will be described below. The steps may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, steps may be performed by a combination of hardware, software, and firmware and/or by human operators.
Various methods described herein may be practiced by combining one or more machine-readable storage media containing the code according to the present invention with appropriate standard computer hardware to execute the code contained therein. An apparatus for practicing various embodiments of the present invention may involve one or more computers (or one or more processors within a single computer) and storage systems containing or having network access to computer program(s) coded in accordance with various methods described herein, and the method steps of the invention could be accomplished by modules, routines, subroutines, or subparts of a computer program product.
If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
The present disclosure relates to noise reduction. In particular, the present disclosure pertains to a system and method for noise reduction in wireless communication utilizing an equalizer having an adaptive decision feedback equalizer and a decoder in a single format.
In an aspect, the present disclosures relates to an adaptive decision feedback equalizer for generating an improved signal by reducing a bit error rate (BER)/noise, the adaptive decision feedback equalizer includes: an output signal receive module configured to receive an output signal generated by a decoder and a property of a desired signal; an error determination module configured to determine presence of an error in the output signal by identifying the filter coefficient weights associated with the received output signal; a weight updating module configured to update the filter coefficient weights by using a Least Mean Square (LMS) algorithm to adapt with the property of the desired signal, wherein the LMS modifies the filter coefficient weights with gradient-based method to generate convergence of the received output signal with reduced bit error rate (BER)/noise; and a signal generation module configured to generate the improved signal having reduced bit error rate (BER)/noise.
In an aspect, the equalizer and the decoder can be in a single format with a forward error correction to remove residual errors and to enable selective channel with time variation.
In an aspect, the LMS algorithm can utilize an estimate of a gradient vector from the filter coefficient weights.
In an aspect, the decoder can be preferably a soft-in soft-out (SISO) decoder.
In an aspect, the equalizer can include a feed forward filter, a feedback filter, an adder, a log logarithmic ratio (LLR) mapper, and a de-interleaver.
In an aspect, the present disclosures relates to an adaptive decision feedback equalizer, for generating an improved signal by receiving an output signal generated by a decoder and a property of a desired signal; determining presence of an error in the output signal by identifying the filter coefficient weights associated with the received output signal; updating the filter coefficient weights by using a Least Mean Square (LMS) algorithm to adapt with the property of the desired signal, wherein the LMS modifies the filter coefficient weights with gradient-based method to generate convergence of the received output signal with reduced bit error rate (BER)/noise; and generating the improved signal having reduced bit error rate (BER)/noise.
FIG. 2 illustrates a block diagram of a linear turbo equalizer in accordance with an embodiment of the present disclosure. FIG.2 illustrates a SISO equalizer module 202 and a SISO decoder module 204 that can work in an iterative fashion. In first iteration, SISO equalizer module 202 that includes a HFF 112-1 can receive an input Zn and outputs data stream that is fed into an adder 112-3. Output yn from the adder 112-3 can be fed into LLR (log likelihood ratio) mapping/mapper block 206 to output data stream. In an aspect, output of LLR mapping block 206 can be provided to a de-interleaver 116 that can correct the burst errors, de-interleaver 116 processed stream can be provided as input to SISO decoder 208 (of SISO decoder module 204). In an aspect, SISO decoder module 204 can include SISO decoder 208 to receive output of de-interleaver 116 to provide two output data streams, wherein first data stream can be received as output b ^_i and other output stream can be fed into interleaver 104 to correct error codes present in the stream. Interleaver output can be processed to average symbol mapping block 210, wherein output x ¯_n of average symbol mapping block 210 can be fed into HFB 112-2 (forms part of SISO equalizer module 202) to process the received stream.
In a second iteration, HFB 112-2 can process the received stream and feds into the adder 112-3, wherein adder 112-3, upon receiving outputs of HFF 112-1 and HFB 112-2, performs an add operation and outputs a data stream yn that can function as described with respect to the first iteration.
In an aspect, two major parts of receiver that is SISO decoder 208 and SISO equalizer 202 that iteratively exchanges information can be referred as linear turbo equalizer.
In an aspect, least mean square mechanism (LMS) can be implemented with adaptive decision feedback equalizer to enable a signal generation module to improve BER.
In an aspect, module 202 can function on received N coded bits. Soft symbols/information x ¯_n from previous iteration of the decoder 204 can be processed in the feedback filter 112-2 of the SISO equalizer. Soft information n can be defined as given below.
(3)
Where ZN-K-updated channel output
x ¯_(n-k) -Soft symbol for bit index k
In an aspect, can be set as zero to generate the estimated symbols( x) ^_n. Symbol-to bit (STOB) mapper can perform conversion of to a LLR on dn,k, wherein dn,k can be defined by (dn,k ), where k = 0, 1,… m -1 is the bit index within a symbol.
In an aspect, LLR information can be iteratively exchanged between SISO equalizer 202 and SISO decoder module 204, wherein updated LLR information from the SISO equalizer 202 can be received by the SISO decoder 204 as input to produce a reliability metric (expressed by below equation) on the coded bits and reliability metric can be expressed by below equation:
(4)
Where dn,k-desired response at n-k index
( x) ^_n.-estimated symbol
K-constraint length
In an aspect, total law of probability can be expressed as:
, (5)
Where dn-desired response at nth index
In an aspect, adaptive equalizer module 202 and SISO decoder module 204 can be deployed in a single format with a forward error correction to remove residual errors and to enable selective channel with time variation.
According to an embodiment, error correcting codes such as turbo codes can be utilized to reduce noise such as intersymbol interference (ISI) and bit error rate (BER). In an aspect, decoder, equalizer, error correction circuit to reduce residual errors and other electronic components can be packaged in one format.
FIG. 3A illustrates least mean square architecture in accordance with an embodiment of the present disclosure.
In an aspect, block 302 can receive channel input and an error stream, block 304 can receive binary to symbol bit (BTOS) input and the error stream, wherein first modified error stream as an output of block 302 can be received into block 306, and second modified error stream as an output of block 304 (can be received into block 308).. In an aspect, feed forward step size operation and feedback step size operation can be performed at block 306 and block 308 respectively and corresponding outputs of block 306 and 308 can be received by adder 312 and 314. In an aspect, LMS can be executed in an iterative manner.
In first iteration, outputs of adder 312 and adder 314 can be processed by decision feedback filter (DFF) 318 and DFF 320 respectively. In an aspect, DFF 318 output can be fed into a multiplexer 310, wherein multiplexer 310 can also receive wf(0). In a similar fashion, DFF 320 output can be fed into the multiplexer 316, wherein multiplexer 310 can also receive wb(0).
In second iteration, based on DFF 318 output and wf(0), multiplexed stream can be generated from 310 that can be fed into adder 312. In third iteration, adder 312 output can again be provided to DFF 318 and process continues for next iterations. In a similar fashion, adder 314, multiplexer 316, and DFF 320 can execute.
In an aspect, filter coefficient can be updated by using step size as least mean square (LMS), and convergence can be expressed by below equation:
(6)
(7)
Where, µa-step-size parameter for feed forward filter
µb-step-size parameter for feedback filter
Wf(n+1)-updated pth order feed forward filter at index n+1
Wf(n)- pth order feed forward filter at index n
Wb(n+1)- updated qth order feedback filter at index n+1
Wb(n)- qth order feedback filter at index n
x(n)-input symbols for feed forward filter
v(n)- input symbols for feedback filter
e*(n)-mean square error
In an aspect, LMS can modify/update filter coefficient by utilizing time with gradient-based mechanism, LMS can also perform convergence of original input stream. In an aspect, LMS can be an iterative mechanism that gives minimum mean square error and executes error correction in the feed forward filter (FFF), feedback filter (FBF), weight vector therefore reduces ISI and channel error.
FIG. 3B illustrates a block diagram of a transversal wiener filter in accordance with an embodiment of the present disclosure. As illustrated, an input X(n) can be fed into a wiener filter 352-1 and a multiplier 354-1, output from 352-1 can be fed into a multiplier 354-2 and a wiener filter 352-2. In a similar fashion multiple wiener filters and multipliers can be configured. In an aspect, each multiplier can also receive weight vector for instance multiplier 354-1 can receive weight vector w0, multiplier 354-1 can receive weight vector w1.
In an aspect, output from each multiplier (354-1, 354-2,….354-n) can be received by an adder 356 to perform an add operation and provide output y(n). Output y(n) can be received by another adder 358 to add y(n) stream and a decision data d(n) and output an error stream e(n).
In an exemplary aspect, tap weight vector, stream input, filter output, error stream, performance matrix, and autocorrelation can be expressed by below equations:
tap weight vector (8)
Stream input X(n)=?[x(n),x(n-1),x(n-2)……..x(n-N+1)] ?^T (9)
Where X(n)-updated input vector
Filter output (10)
Where, yn-output received sequence code
w ¯^T-transposed tap weight vector
x ¯(n)-input vector
Error stream (11)
Where, dn-index time
Performance function , (12)
Where E[e2(n)]-power of error stream
E[d2(n)]-power of desired function
W ¯^T-transposed tap weight vector
R-autocorrelation matrix of filter input
-tap weight vector
-cross-correlation vectors between and d(n)
Furthermore, autocorrelation matrix of the filter input and can be cross-correlation vectors between and d(n).
In an aspect, equalizer coefficients, in case of changing channel characteristics can track channel variations. Furthermore, an adaptive filter can be used to implement a desired filter by finding the filter coefficients that relate to producing the least mean squares and cost function, wherein cost function can be expressed by below equation:
C(n)=E{e2(n)} (13)
Where E[e2(n)]-statistical expected value of square error signal
In an aspect, e(n) can modify the convergence in future as e(n) is based on soft information, e(n) can be expressed by below equation
(14)
Where d*(n)- mean square desired response function
wh- coefficient
In an aspect, values of r and R can be identified by below equations:
(15)
(16)
Where R(n)-matrices
r(n)-matrices
xh(n)-coefficient
In an aspect, updating filter equation for next stage can be expressed by below equation:
(16)
Where µ- step size parameter
W(n+1)-ordered filter at index n+1
W(n)- ordered filter at index n
E{.}-statistical expectation
Another representation of Equation 17 can be:
(18)
In an aspect, LMS mechanism can be started with an arbitrary or undefined value W(0) and for the weight vector at n=0 coming corrections of the weight vector can be minimum value of the mean squared error (MSE). Updated value of filter coefficient for feed forward filter and feed backward filter can be illustrated by equations 6 and 7. Further, w(n) and W(n) are referred interchangeably.
FIG. 4A illustrates an adaptive filter based on LMS in accordance with an embodiment of the present disclosure.
In an aspect, input sample xn can be provided to an error computation block 402 and weight update block 404, wherein block 404 can receive xn through two n1D weights. Block 402 can receive a desired stream dn and provides error stream to block 404 through weight n_1D. After processing the received streams through n1D and update it at block 404, computed new weights n_2 D can be transmitted to the block 402.
FIG. 4B illustrates exemplary functional modules for reducing BER/noise in accordance with an embodiment of the present disclosure. In an aspect, adaptive decision feedback equalizer can reduce BER and generates an improved signal. Decoder output data stream/signal together with at least one property of a desired signal can be received by an output signal receive module 452 configured at the equalizer. An error determination/computation module 454 can be employed to determine error in the received signal, wherein error can be determined by identifying filter coefficients of received signal. Weight updation/computation module 456 can update the received filter coefficient weights by using LMS, wherein LMS can modify the filter coefficient time with gradient-based method to generate convergence of received signal with reduced BER. Signal generation module 458 can be employed to generate reduced BER signal.
In an aspect, p/4- differential quadrature phase-shift keying (DQPSK) modem can be implemented to transmit two bits per symbol and therefore provide twice the bandwidth efficiency of binary phase shift keying. DQPSK can also have less envelope variation due to (+,-) 900 and (+,-) 2700 phase transition. DQPSK can be modulated without a coherent phase reference.
In an aspect, at the modulator, phase at time instant t = kT is fk which can be evaluated as
fk = fk-1 + ?fk, (19)
Where fk – 1 -phase at time t = (k-1)T
?fk-phase change due to I and Q bits at t = kT
In an aspect, transmitted in-phase signal Ik and quadrature signal Qk can be expressed as:
Ik = cos (fk) = cos (fk-1+ fk) = Ik-1cos(?fk ) -- Qk-1sin(?fk)Qk = sin(fk) = sin( k--1 + ?fk) Ik-1sin( ?fk) + Qk-1cos( ?fk) (20)

In an aspect, in case of phase reference error k occurs at equalizer output, received in phase and quadrature component can be expresses as,
IRk = cos (?fk + fk) (21)
QRk = sin (?fk + fk) (22)
Where I and Q are mutual information
Rk-Autocorrelation matrix of filter input bit
FIGs. 5A and 5B illustrates an exemplary error calculation output in accordance with an embodiment of the present disclosure. Behavioral simulation result and register-transfer level (RTL) view of error calculation module is depicted.
FIG. 6 illustrates an exemplary behavioral simulation result for weight updation module in accordance with an embodiment of the present disclosure.
In an aspect, weight updation module can update the equalizer weights based on previous weights, equalizer input and error signal. Real and imaginary part of equalizer weights can be exemplary represented in 32.28 formats. To substantiate the principle and working of disclosure, simulation was performed in Xilinx ISE Design Suite 13.2 software and design was implemented on Xilinx XC6VLX130T Vertex FPGA with achievable design frequency of 1.25 GHz.
FIG. 7A illustrates block diagram for LLR unit in accordance with an embodiment of the present disclosure. In an aspect, LLR unit includes a plurality of multiplexers arranged in such a manner so that input stream can be decoded. LLR output for each symbol can be expressed by following equation:
???? ???? =??????????,=1* (????( ????) +???? (????,????-1) +????+1( ????+1) – ??????????,????=-1* (???? (????) +????( ????,????-1) +????+1(????+1)) (23)
Where Lk-log likelihood ratio/probability
Uk-data bit
??????????,=1- max value at present state for data bit
????-forward recursion
Sk- present state
????-transition probability
????-1-previous state
????+1-future state
????+1-backward recursion
In an aspect, ????) +???? (????,-1) can be provided by forward recursion unit and corresponding ????+1 (????+1) values provided by RAM, are utilized to compute the LLR values.
FIG. 7B illustrates behavioral simulation result for SISO decoder in accordance with an embodiment of the present disclosure. Simulation was performed on 5vsx35tff665-3, speed grade -3, minimum time period 4.659ns (maximum frequency: 214.615MHz), minimum input arrival time before clock: 2.141ns, maximum output required time after clock: 17.657ns, number of Slice registers - 300 out of 21760 (approximately 1%), number of slice LUTs - 1317 out of 21760 (approximately 6%), number used as Logic – 1173 out of 21760 (approximately 5%), number used as memory - 144 out of 8320 (approximately 1%), number used as RAM -144, number of bit slices used - 1317, number with an unused Flip Flop - 1017 out of 1317 (approximately 77%), number with an unused LUT - 0 out of 1317, number of fully used bit slices - 300 out of 1317 (approximately 22%), number of IOs – 28, number of bonded IOBs - 28 out of 360 (approximately 7%), number of BUFG/BUFGCTRLs: 1 out of 32 (approximately 3%), maximum combinational path delay - No path found, clock period - 1.107ns (frequency: 903.076MHz), total number of paths/ destination ports - 14 / 5, delay - 1.107ns (Levels of Logic = 1), source: fsm1/state1_FFd2 (FF), destination: fsm1/state1_FFd3 (FF), source clock - Counter1/obar_3 rising, destination clock: counter1/obar_3 rising, and data path - fsm1/state1_FFd2 to fsm1/state1_FFd3.
FIG. 7C illustrates RTL view of SISO Decoder accordance with an embodiment of the present disclosure.
It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refers to at least one of something selected from the group consisting of A, B, C ….and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc..

ADVANTAGES OF THE INVENTION
The present disclosure overcomes one or more disadvantages associated with conventional systems and methods for reducing bit error rate/noise/ISI.
The present disclosure creates a single IC package including a decoder and a decision feedback equalizer.
The present disclosure prevents bit overflow.
The present disclosure controls output of soft input soft output (SISO) decoder.
The present disclosure utilizes the single package and performs circuit operations with low power and also occupies lesser area.

Claims:1. An adaptive decision feedback equalizer for generating an improved signal by reducing a bit error rate (BER)/noise, said adaptive decision feedback equalizer comprising:
an output signal receive module configured to receive an output signal generated by a decoder and a property of a desired signal;
an error determination module configured to determine presence of an error in the output signal by identifying the filter coefficient weights associated with the received output signal;
a weight updating module configured to update the filter coefficient weights by using a Least Mean Square (LMS) algorithm to adapt with the property of the desired signal, wherein the LMS modifies the filter coefficient weights with gradient-based method to generate convergence of the received output signal with reduced bit error rate (BER)/noise; and
a signal generation module configured to generate the improved signal having reduced bit error rate (BER)/noise.
2. The adaptive decision feedback equalizer as claimed in claim 1, wherein the equalizer and the decoder are in a single format with a forward error correction to remove residual errors and to enable selective channel with time variation.
3. The adaptive decision feedback equalizer as claimed in claim 1, wherein the LMS algorithm utilizes an estimate of a gradient vector from the filter coefficient weights.
4. The adaptive decision feedback equalizer as claimed in claim 1, wherein the decoder is preferably a soft-in soft-out (SISO) decoder.
5. The adaptive decision feedback equalizer as claimed in claim 1, wherein the equalizer comprising a feed forward filter, a feedback filter, an adder, a log logarithmic ratio (LLR) mapper, and a de-interleaver.
6. A method, by an adaptive decision feedback equalizer, for generating an improved signal, the method comprising the steps of receiving an output signal generated by a decoder and a property of a desired signal; determining presence of an error in the output signal by identifying the filter coefficient weights associated with the received output signal; updating the filter coefficient weights by using a Least Mean Square (LMS) algorithm to adapt with the property of the desired signal, wherein the LMS modifies the filter coefficient weights with gradient-based method to generate convergence of the received output signal with reduced bit error rate (BER)/noise; and generating the improved signal having reduced bit error rate (BER)/noise.
7. The method of claim 6, wherein the equalizer and the decoder are in a single format with a forward error correction to remove residual errors and to enable selective channel with time variation.
8. The method of claim 6, wherein the LMS algorithm utilizes the estimates of the gradient vector from the filter coefficient weights.
9. The method of claim 6, wherein the decoder is preferably a soft-in soft-out (SISO) decoder.
10. The method of claim 6, wherein the equalizer and the decoder are in a single format with a forward error correction to remove residual errors and to enable selective channel with time variation.