Generally, the invention relates to an offset correction. More specifically, the invention relates to a system and method for performing offset correction in an electronic circuit.

Background
[002] Latches and amplifiers are basic building blocks for various analog circuits. One major limitation of the analog circuits is offset that occurs from process, environment, and operation variations. In order to maintain overall performance of system, the offset introduced by such circuits must be neutralized. Moreover, for neutralizing offset introduced by such circuits, an offset correction scheme must be design taking into consideration two critical parameters that includes resolution of the offset correction scheme and range of the offset correction scheme. The offset correction schemes may be broadly categorized into two categories i.e., an analog circuit offset correction scheme and a digital circuit offset correction scheme. Despite the fact that the analog circuit offset correction scheme have a high resolution and range, they are difficult to design and require extensive calibration and verification to ensure correct functionality. On the contrary, the digital circuit offset correction scheme may be relatively easy to design but there is trade-off between resolution and range for a given number of bits used for calibration code.
[003] At present, various offset correction schemes have been proposed for the analog circuits. Examples of some of the existing offset correction schemes may include implementation of skewed differential pair circuit and implementation of multiple Digital to Analog Convertor (DAC) on the analog circuits for offset correction. The major problem of implementing the skewed differential pair circuit is a variation of offset correction range (resolution) across Process Voltage Temperature (PVT). Further, additional parasitic capacitance may be required on the output, as a result of which speed of amplifiers and latches may be reduced. Further, implementation of individual DAC on each amplifier or latch of the analog circuits may consume more power and occupies larger area.
[004] Therefore, there is a need of an efficient and reliable offset correction scheme that offers a deterministic offset correction range without incurring additional parasitic capacitance, additional power, or large area.

SUMMARY OF INVENTION
[005] In one embodiment, a method for performing offset correction in an electronic circuit that includes at least one of an amplifier or a latch is disclosed. The method may include receiving a positive reference voltage signal, a negative reference voltage signal, and an offset code. The method may further include multiplexing the positive reference voltage and the negative reference voltage based on the offset code to generate a reference voltage. The method may further include performing an offset correction based on the reference voltage. The method may further include determining if the offset is within a pre-defined threshold range. The method may further include iteratively adjusting the offset code in response to the determination to generate an accurate reference voltage. The method may further include performing an offset correction based on the accurate reference voltage.
[006] In another embodiment, an offset correction circuit for performing offset correction in an electronic circuit that includes at least one of an amplifier or a latch is disclosed. The offset correction circuit may be configured to receive a positive reference voltage signal, a negative reference voltage signal, and an offset code. The offset correction circuit may be further configured to multiplex the positive reference voltage and the negative reference voltage based on the offset code to generate a reference voltage. Further, the electronic circuit coupled to the offset correction circuit may be configured to perform an offset correction based on the reference voltage and determine if the offset is within a pre-defined threshold range. In response to the determination, the offset correction circuit may be further configured to iteratively adjust the offset code to generate an accurate reference voltage. Further, the electronic circuit coupled to the offset correction circuit may be configured to perform the offset correction based on the accurate reference voltage.
[007] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS
[008] The present application can be best understood by reference to the following description taken in conjunction with the accompanying drawing figures, in which like parts may be referred to by like numerals.
[009] FIG. 1 illustrate a generic structure of an electronic circuit, in accordance with an exemplary embodiment of the present disclosure.
[010] FIG. 2 illustrates a prior art for performing an offset correction in an electronic circuit by implementing a skewed differential pair circuit within the electronic circuit, in accordance with an exemplary embodiment of the present disclosure.
[011] FIG. 3 is a graph for the skewed differential pair electronic circuit depicting variation of offset correction range across PVT (a process, a voltage, or a temperature), in accordance with an exemplary embodiment of the present disclosure.
[012] FIG. 4 illustrates another prior art for performing offset correction in an electronic circuit by implementing Digital-to-Analog Convertor (DAC) within the electronic circuit, in accordance with an exemplary embodiment of the present disclosure.
[013] FIG. 5 illustrate a system for performing offset correction in an electronic circuit via an offset correction circuit, in accordance with some embodiment of the present disclosure.
[014] FIGS. 6A and 6B illustrate two different configurations of a multiplexer switch of an offset correction circuit, in accordance with an exemplary embodiment of the present disclosure.
[015] FIG. 7 illustrate a system for performing offset correction in a bipolar junction transistor (BJT) differential pair electronic circuit via an offset correction circuit, in accordance with some embodiment of the present disclosure.
[016] FIG. 8 illustrates a flowchart of a method for performing offset correction in the electronic circuit, in accordance with some embodiments of the present disclosure.
[017] FIG. 9 illustrates a graph depicting an offset correction range across PVT for an offset correction circuit, in accordance with some embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE DRAWINGS
[018] The following description is presented to enable a person of ordinary skill in the art to make and use the invention and is provided in the context of particular applications and their requirements. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Moreover, in the following description, numerous details are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the invention might be practiced without the use of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail. Thus, the invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
[019] While the invention is described in terms of particular examples and illustrative figures, those of ordinary skill in the art will recognize that the invention is not limited to the examples or figures described. Those skilled in the art will recognize that the operations of the various embodiments may be implemented using hardware, software, firmware, or combinations thereof, as appropriate. For example, some processes can be carried out using processors or other digital circuitry under the control of software, firmware, or hard-wired logic. (The term “logic” herein refers to fixed hardware, programmable logic and/or an appropriate combination thereof, as would be recognized by one skilled in the art to carry out the recited functions.) Software and firmware can be stored on computer-readable storage media. Some other processes can be implemented using analog circuitry, as is well known to one of ordinary skill in the art. Additionally, memory or other storage, as well as communication components, may be employed in embodiments of the invention.
[020] Referring now to Fig. 1, a generic structure of an electronic circuit 100 is illustrated, in accordance with some embodiments. The electronic circuit 100 may include at least one of an amplifier or a latch. In an embodiment, the electronic circuit 100 may be a differential pair amplifier electronic circuit that may be constructed using at least two identical transistors (for example, using at least two BJTs or at least two field-effect transistors (FETs)). It will be apparent to a person skilled in the art that the differential pair amplifier electronic circuit may be constructed either using a p-type transistor, a n-type transistor, or a combination thereof. As represented in the present FIG. 1, the differential pair amplifier electronic circuit may be constructed using at least two metal-oxide-semiconductor field-effect transistors (MOSFET). For example, MP[N:0] and MN[N:0], respectively. Hence, the differential pair amplifier electronic circuit may also be referred as a MOSFET type differential pair amplifier electronic circuit
[021] In an embodiment, the differential pair amplifier electronic circuit may include at least two inputs, for example, a positive input voltage (VINP) and a reference voltage (VREF). In addition the differential pair amplifier electronic circuit may further include at least two outputs, for example, a positive output voltage (VOUTP) and a negative output voltage (VOUTN). As depicted via present FIG. 1, left side of the of the differential pair amplifier electronic circuit i.e., the VINP, may be connected to at least one p-type MOSFET (for example, MP[N:0]). Moreover, right side of the differential pair amplifier electronic circuit, i.e., VREF may be connected to at least one n-type MOSFET (for example, MN[N:0]). The VOUTN and the VOUTP of the differential pair amplifier electronic circuit may be outputs of the at least one of the amplifier or the latch.
[022] Further, the differential pair amplifier electronic circuit may include a load and a tail. Upper ends of the at least two MOSFETs (i.e., upper end of the p-type MOSFET and the n-type MOSFET) may be connected to the load of the differential pair amplifier electronic circuit. In addition, lower ends of the at least two MOSFETs (i.e., lower end of the p-type MOSFET and the n-type MOSFET) may be connected to the tail of the differential pair amplifier electronic circuit.
[023] As will be appreciated, the tail and the load of the differential pair amplifier electronic circuit may be used to bias the at least one of the amplifier or the latch. It should be noted that, for an ideal differential pair electronic circuit, a current flowing through the VINP side of the differential pair electronic circuit must be equal to a current flowing in the VREF side of the differential pair electronic circuit. However, in practical, various manufacturing imperfections in the differential pair electronic circuit may introduce an offset in the at least one of the amplifier and the latch. Currently, many schemes exist in prior art to address the offset issue in the at least one of the amplifier and the latch of the differential pair electronic circuit. These existing schemes may be broadly classified into two implementations and are explained in greater detail in conjunction with FIG.–2 - FIG. 4.
[024] Referring now to Fig. 2, a prior art for performing offset correction within an electronic circuit 200 by implementing a skewed differential pair circuit in the electronic circuit 200 is illustrated, in accordance with an exemplary embodiment of the present disclosure. As depicted via present FIG. 2, the electronic circuit 200 may include two inputs, i.e., a VINP and a VREF. Further, the electronic circuit 200 may include two outputs, i.e., VOUTP and VOUTN. In present embodiment, left side of the electronic circuit 200, i.e., the VINP may be connected to two p-type MOSFET (i.e., MP[N:1] and MP[0]). In addition, right side of the electronic circuit 200, i.e., the VREF may be connected to two n-type MOSFET (i.e., MN[N:1] and MN[0]). In order to perform offset correction in the electronic circuit 200, , a strength each of the two p-type MOSFET and each of the two n-type MPSFET are skewed using an MP offset (MPOFS) device and an MN offset (MNOFS) device, respectively. By introducing this skew, the offset introduced during manufacturing of the electronic circuit 200 may be removed. In other words, offset correction scheme depicted via the present FIG. 2, uses two parallel differential MOSFET pairs (for example, one pair of p-type MOSFET and one pair of n-type MOSFET) that are intentionally skewed to balance outputs, i.e., a VOUTN and a VOUTP of the electronic circuit 200.
[025] Moreover, current flowing through each differential MOSFET pairs may then be increased or decreased until any offset present in the electronic circuit 200 is sufficiently cancelled. Additionally, the offset in the electronic circuit 200 may be cancelled using a suitable offset code (also referred as ofscode) that is generated by a logic block 202. However, the offset correction scheme depicted via the present FIG. 2 suffers from variation of offset correction range (resolution) across a process, a voltage, and a temperature (PVT). The variation of the offset correction range across the PVT is explained via a graph in conjunction with FIG. 3.
[026] Referring now to Fig. 3, a variation of the offset correction range across the PVT for the skewed differential pair circuit is illustrated via a graph 300, in accordance with an exemplary embodiment of the present disclosure. The graph 300 depicts the offset correction range across PVT for 5-bit offset code. In the graph 300, ‘X-axis’ of the graph 300 represents an offset code (ofscode) setting range that may be lies between 0 to 30. Further, ‘Y-axis’ of the graph 300 represents the offset correction range from -100 millivolt (mV) to +100mv.
[027] In reference to FIG. the graph 300 shows that upon implementing the skewed differential pair circuit in the electronic circuit 200, the offset correction range varies across the PVT. As depicted via the graph 300, the offset correction range may vary from ±50mV to ±90mV across the PVT based on the offset code. In other words, in reference to the FIG. 2, in the p-type MOSFET (MP[N:1]) and the n-type MOSFET (MN[N:1]), a value of “N” must be chosen in such a way that, the chosen value for “N” may meet both resolution and range across the PVT. However, this may increase a parasitic capacitance on the outputs, i.e., the VOUTN and the VOUTP of the skewed differential pair circuit, as a result of which speed of the at least one of the amplifier and the latch may be reduced.
[028] Referring now to Fig. 4, another prior art for performing offset correction in an electronic circuit 400 by implementing a digital-to-analog converter (DAC) in the electronic circuit 400 is illustrated, in accordance with an exemplary embodiment of the present disclosure. In reference to FIG. 1, the electronic circuit 400 may correspond to the electronic circuit 100. In present FIG. 4, an offset correction scheme for performing the offset correction in the electronic circuit 400 may use a DAC 402. In this offset correction scheme, the DAC 402 may be implemented on VREF input side of the electronic circuit 400. In an embodiment, the electronic circuit 400 may correspond to a differential pair electronic circuit. In order to perform the offset correction via the offset correction scheme disclosed in the present FIG. 4, a suitable offset code may be applied to the DAC 402. Upon applying the suitable offset code to the DAC 402 the DAC 402 may adjust the VREF input side of the electronic circuit 400 such that any offset present in at least one of an amplifier or a latch of the electronic circuit 400 may be removed. It should be noted that, the offset code applied to the DAC 402 may be iteratively adjusted to determine the suitable offset code for performing the offset correction in the electronic circuit 400.
[029] Unlike the offset correction scheme using the skewed differential pair circuit of the FIG. 2, the offset correction scheme implementing the DAC 402 of the present FIG. 4 may not suffer the variation across the PVT. However, this offset correction scheme requires higher area penalty since each of the at least one of the amplifier or the latch may requires a separate DAC. More specifically, in a system where there may be a several amplifiers or latches, for example, in a Double Data Rate (DDR) system, a High Bandwidth Memory (HBM), an image sensor read path, a memory read path, etc., implementation of several DACs may result in increased area thereby consuming additional power. Therefore, due to drawbacks in existing offset correction schemes as described above in reference to FIG. 2 – FIG.4, an offset correction circuit has been developed and is explained in greater detail in conjunction with subsequent FIG.5 to FIG. 9 of the present disclosure.
[030] Referring now to Fig. 5, a system 500 for performing offset correction in an electronic circuit 502 via an offset correction circuit 504 is illustrated, in accordance with some embodiment of the present disclosure. The electronic circuit 502 may include at least one of an amplifier or a latch. In an embodiment, the electronic circuit 502 of the present FIG. 5 may be analogous to the electronic circuit 100 of the FIG. 1. Since the electronic circuit 502 of the present FIG. 5 is analogous to the electronic circuit 100 of the FIG. 1, hence the electronic circuit 502 may correspond to the MOSFET type differential pair amplifier electronic circuit. As will be appreciated, construction of the MOSFET type differential pair amplifier electronic circuit, i.e., the electronic circuit 100 has been already discussed in conjunction with the FIG.1.
[031] The offset correction circuit 504 may include a multiplexer switch 506 (SW[N:0]) that is electronically coupled to each of the at least one of the amplifier or the latch of the electronic circuit 502.The multiplexer switch 506 may include at least two reference voltages i.e., a positive reference voltage (VREFP) and a negative reference voltage (VREFN). The offset correction circuit 504 may receive the VREFP, the VREFN, and an offset code (OFSCODE[K:0]). Further, upon receiving the VREP, the VREFN, and the offset code, the multiplexer switch 506 of the offset correction circuit 504 may multiplex the VREFP and the VREFN based on the offset code to generate a reference voltage (VREF[N:0]).
[032] Once the reference voltage is generated, the multiplexer switch 506 may provide the reference voltage as an input to the electronic circuit 502. Upon receiving the reference voltage, the electronic circuit 502 may perform an offset correction based on the reference voltage. In order to perform the offset correction, after applying the reference voltage received as the input from the multiplexer switch 506, the electronic circuit 502 may determine if the offset is within a pre-defined threshold range. Based on the determination, the offset correction circuit 504 may further iteratively adjust the offset code in response to the determination to generate an accurate reference voltage. It should be noted that, the accurate reference voltage may correspond to a voltage based on which any offset present in the electronic circuit 502 may be cancelled.
[033] In some embodiments, the offset correction circuit 504 may generate the reference voltage or the accurate reference voltage by selecting one of the VREFP or the VREFN based on the offset code.
[034] Once the accurate reference voltage is generated, the electronic circuit 502 may perform the offset correction for balancing a load in the electronic circuit 502. In addition to the generation of the accurate reference voltage, in order to perform the offset correction, the offset correction circuit 504 may determine a correction range for the electronic circuit 502. The correction range may be determined based on a difference between the VREFP and the VREFN. It may be noted that, the determined correction range remains substantially within a predefined threshold across the PVT in the electronic circuit 502. It may also be noted that, a bandwidth of the at least one of the amplifier or the latch remain substantially same as that without using the offset correction circuit 504. In other words, the bandwidth of an amplifier or a latch with the offset correction circuit described in the various embodiments discussed herein is about the same as the bandwidth of the amplifier or the latch if no offset correction circuit were used.
[035] By way of an example, the accurate reference voltage VREF[N:0] may be generated through the multiplexer switch 506 (SW[N:0]) which selects either the VREFP or the VREFN depending on the offset code (OFSCODE[K:0]). For example, when value of the offset code is M, then MN[0:M] may be connected to the VREFN and MN[M+1:N] may be connected to the VREFP.
[036] Referring now to FIGs. 6A and 6B, two different configurations of a multiplexer switch of an offset correction circuit is illustrated, in accordance with some embodiments. In reference to FIG. 5, the multiplexer switch of the offset correction circuit may correspond to the multiplexer switch 506 of the offset correction circuit 504. In first configuration the multiplexer switch 506 may be configured using at least two similar N-type metal-oxide-semiconductor (NMOS) circuits, as depicted in the FIG. 6A.
[037] In second configuration, the multiplexer switch 506 of the offset correction circuit 504 may be configured using transmission gate that includes a combination of at least one parallel pair of NMOS and at least one parallel pair of P-type metal-oxide-semiconductor (PMOS) circuits, as depicted in FIG. 6B.
[038] Referring now to FIG. 7, a system 700 for performing offset correction in a bipolar junction transistor (BJT) differential pair electronic circuit 702 via an offset correction circuit 704 is illustrated, in accordance with some embodiment of the present disclosure. In an embodiment, in order to perform the offset correction, the offset correction circuit 704 may be implemented in the BJT type differential pair amplifier electronic circuit 702. It should be noted that the offset correction circuit 704 may be analogous to the offset correction circuit 502. As depicted via the present FIG. 7, the offset correction circuit 704 may include a multiplexer switch 706 (SW[N:0]) that is electronically coupled to each of the at least one of the amplifier or the latch of the BJT type differential pair amplifier electronic circuit 702. As will be appreciated, in order to the perform offset correction in the BJT type differential pair electronic circuit 702 via the offset correction circuit 704, a similar process for the offset correction may be followed as described above for the MOSFET type differential pair amplifier electronic circuit 500 in reference to the FIG.5.
[039] Referring now to FIG. 8, a method 800 for performing offset correction in an electronic circuit is illustrated via a flowchart, in accordance with some embodiments. In reference to FIG. 5, the electronic circuit may correspond to the electronic circuit 502. Moreover, the offset correction in the electronic circuit 502 may be performed by the offset correction circuit 504. In an embodiment, the electronic circuit may include at least one of an amplifier or a latch. In order to perform offset correction, initially at step 802, a positive reference voltage, a negative reference voltage signal, and an offset code may be received. In reference to FIG. 5, the positive reference voltage, the negative reference voltage, and the offset code may correspond to the VREFP, the VREF, and the OFSCODE [K:0]. Further, at step 804, the positive reference voltage and the negative reference voltage may be multiplexed based on the offset code. In an embodiment, the positive reference voltage and the negative reference voltage may be multiplexed to generate a reference voltage.
[040] Upon generating the reference voltage, at step 806, an offset correction may be performed based on the reference voltage. It may be noted that, the offset correction may be performed by the electronic circuit 500. After performing the offset correction based on the reference voltage, at step 808, a check may be performed to determine if the offset is within a pre-defined threshold range.
[041] Based on the check performed, at step 810, the offset code may be iteratively adjusted in response to the determination to generate an accurate reference voltage. In other words, the offset code may be iteratively adjusted until the accurate reference voltage for cancelling the offset in the electronic circuit is determined. In an embodiment, the reference voltage or the accurate reference voltage may be generated by selecting one of the positive reference voltage or the negative reference voltage based on the offset code.
[042] Upon determining the accurate reference voltage by iteratively adjusting the offset code, at step 812, the offset correction may be performed based on the accurate reference voltage. Additionally, for performing the offset correction, a correction range may be determined. The correction range may be determined based on a difference between the positive reference voltage and the negative reference voltage. It may be noted that, the correction range remains substantially within a predefined threshold across a process, a voltage, or a temperature in the electronic circuit. Moreover, a bandwidth of the at least one of the amplifier or the latch may remain substantially same as that without using the offset correction circuit.
[043] Referring now to FIG. 9, a graph 900 depicting an offset correction range across PVT for an offset correction circuit is illustrated, in accordance with some embodiments. In reference to FIG. 5, the offset correction circuit 704 may correspond to the offset correction circuit 504. In the graph 900, ‘X-axis’ of the graph 900 represents an offset code (ofscode) setting range that may lie between 0 to 30. Further, ‘Y-axis’ of the graph 900 represents the offset correction range ranging from -50 millivolt (mV) to +50mV.
[044] As mentioned above in FIG. 8, the correction range is determined based on the difference between the positive reference voltage and the negative reference voltage. With reference to FIG. 9, the offset correction range across the PVT for the offset correction circuit 504 may be VREFP-VREFN=100mV. Therefore, as seen from the graph 900 the determined correction range remains substantially within the predefined threshold across the PVT in the electronic circuit 502.
[045] Various embodiments provide method and system for performing offset correction in an electronic circuit that includes at least one of an amplifier or a latch. The disclosed method and system may receive a positive reference voltage signal, a negative reference voltage signal, and an offset code. Further, the disclosed method and system may multiplex the positive reference voltage and the negative reference voltage based on the offset code to generate a reference voltage. Moreover, the disclosed method and system may perform an offset correction based on the reference voltage. Further, the disclosed method and system may determine if the offset is within a pre-defined threshold range. Thereafter, the disclosed method and system may iteratively adjust the offset code in response to the determination to generate an accurate reference voltage. Lastly, disclosed method and system performing an offset correction based on the accurate reference voltage.
[046] The disclosed method and the system provide an offset correction circuit that may provide some advantages. For example, the disclosed offset correction circuit may rectify all drawbacks that are present in legacy offset correction schemes. In addition, the disclosed offset correction circuit may be able to maintains a correction range within the predefined threshold across the PVT, thereby eliminating a need of additional parasitic capacitance on output nodes of a differential pair amplifier electronic circuit. Additionally, the disclosed offset correction circuit may not require individual DAC for each of the at least one of the amplifier and the latch of the differential pair amplifier electronic circuit, thus occupies significantly less area and consumes no additional power.
[047] It will be appreciated that, for clarity purposes, the above description has described embodiments of the invention with reference to different functional units and different combinations of logic gates. However, it will be apparent that any suitable distribution of functionality between different functional units and different combinations of logic gates may be used without detracting from the invention. For example, functionality illustrated to be performed by separate logic gates may be performed by the same logic gate. Hence, references to specific functional units are only to be seen as references to suitable means for providing the described functionality, rather than indicative of a strict logical or physical structure or organization.
[048] Although the present invention has been described in connection with some embodiments, it is not intended to be limited to the specific form set forth herein. Rather, the scope of the present invention is limited only by the claims. Additionally, although a feature may appear to be described in connection with particular embodiments, one skilled in the art would recognize that various features of the described embodiments may be combined in accordance with the invention.
[049] Furthermore, although individually listed, a plurality of means, elements or process steps may be implemented by, for example, a single unit or processor. Additionally, although individual features may be included in different claims, these may possibly be advantageously combined, and the inclusion in different claims does not imply that a combination of features is not feasible and/or advantageous. Also, the inclusion of a feature in one category of claims does not imply a limitation to this category, but rather the feature may be equally applicable to other claim categories, as appropriate.

CLAIMS

We claim:

1. A method (800) of performing offset correction in an electronic circuit (502) that includes at least one of an amplifier or a latch, the method (800) comprising:
receiving (802), by an offset correction circuit (504), a positive reference voltage signal, a negative reference voltage signal, and an offset code;
multiplexing (804), by the offset correction circuit (504), the positive reference voltage and the negative reference voltage based on the offset code to generate a reference voltage;
performing (806), by the electronic circuit (502), an offset correction based on the reference voltage;
determining (808), by the electronic circuit (502), if the offset is within a pre-defined threshold range;
iteratively adjusting (810), by the offset correction circuit (504), the offset code in response to the determination to generate an accurate reference voltage; and
performing (812), by the electronic circuit (502), an offset correction based on the accurate reference voltage.

2. The method (800) as claimed in claim 1, wherein the offset correction circuit (504) comprises a multiplexer switch (506) electronically coupled to each of the at least one of the amplifier or the latch.

3. The method (800) as claimed in claim 1, wherein generating the reference voltage or generating the accurate reference voltage comprises:
selecting one of the positive reference voltage or the negative reference voltage based on the offset code.

4. The method (800) as claimed in claim 1, comprising:
determining, for the electronic circuit (502), a correction range for the offset cancelation based on a difference between the positive reference voltage and the negative reference voltage.

5. The method (800) as claimed in claim 4, wherein the correction range remains substantially within a predefined threshold across a process, a voltage, or a temperature in the electronic circuit (502).

6. The method (800) as claimed in claim 4, wherein a bandwidth of the at least one of the amplifier or the latch remain substantially same as that without using the offset correction circuit (504).

7. An offset correction circuit (504) for performing offset correction in an electronic circuit (502) that includes at least one of an amplifier or a latch, the offset correction circuit (504) is configured to:
receive (802) a positive reference voltage signal, a negative reference voltage signal, and an offset code;
multiplex (804) the positive reference voltage and the negative reference voltage based on the offset code to generate a reference voltage;
perform (806), by the electronic circuit (502), an offset correction based on the reference voltage;
determine (808), by the electronic circuit (502), if the offset is within a pre-defined threshold range;
iteratively adjust (810) the offset code in response to the determination to generate an accurate reference voltage; and
perform (812), by the electronic circuit (502), the offset correction based on the accurate reference voltage.

8. The offset correction circuit (504) as claimed in claim 7, wherein the offset correction circuit (504) comprises a multiplexer switch (506) electronically coupled to each of the at least one of the amplifier or the latch.

9. The offset correction circuit (504) as claimed in claim 7, wherein, to generate the reference voltage or generate the accurate reference voltage, the offset correction circuit (504) is configured to:
select one of the positive reference voltage or the negative reference voltage based on the offset code.

10. The offset correction circuit (504) as claimed in claim 7, configured to:
determine, for the electronic circuit (502), a correction range for the offset cancelation based on a difference between the positive reference voltage and the negative reference voltage, wherein the correction range remains substantially within a predefined threshold across a process, a voltage, or a temperature in the electronic circuit (504).