Claims:1. A system (100) for real-time data management for radar signal processing, said system comprising:
an analogue to digital converter (ADC) (102) that receives a set of signals from a plurality of receive channels and converts the received set of signals to digital set of signals;
a generator (106) generates corresponding unique identifier (ID) for each of the received digital set of signals, wherein said unique ID associated with each of the digital set of signals used as address into a memory (108), the unique ID is associated with each of the received digital set of signals in addition to flags;
a processor (110) operatively coupled to the memory, the processor (110) configured to:
receive the digital set of signals associated with unique ID; and
uniquely identifies the digital set of signals with corresponding channel number, pulse number and range bin number, wherein the processed data is received at an output unit (112) to distribute output set of data for other subsystems.
2. The system as claimed in claim 1, wherein the digital set of signals comprise plurality of input channels, each input channel comprises plurality of pulse repetition intervals, each pulse repetition intervals comprises a plurality of range bins.
3. The system as claimed in claim 1, wherein the digital set of signals defines to the output of digital pulse compression stage in radar receive chain.
4. The system as claimed in claim 1, wherein the unique ID is formed by concatenating the pulse number, range bin number and an input channel number in any of the order.
5. The system as claimed in claim 1, wherein said processor (110) comprises Field Programmable Gate Array (FPGA).
6. The system as claimed in claim 1, wherein the digital set of signals is stored in any or a combination of FPGA memory or external memory.
7. The system as claimed in claim 1, wherein said processor (110) configured to process the digital set of signals associated with unique ID in any or a combination of parallel and pipelined manner.
8. The system as claimed in claim 7, wherein the processing of the digital set of signals associated with unique ID enable easy data referencing and facilitates conditional and selective processing.
9. The system as claimed in claim 1, wherein the processor coupled to the integrated logic analyzer (114) to monitor and debug error conditions based on unique ID associated with the digital set of signals.
10. A method (300) for real-time data management for radar signal processing, said method comprising:
receiving (302), at an analogue to digital converter (ADC), a set of signals and converts the received set of signals to digital set of signals;
generating (304), at a generator, corresponding unique identifier (ID) for each of the digital set of signals, wherein the unique ID associated with each of the digital set of signals is used as address into a memory; and
analysing (306), at a processor, the digital set of signals uniquely with corresponding channel number, pulse number and range bin number, the processed data is received at an output unit to distribute output set of data for other subsystems.

, Description:TECHNICAL FIELD
[0001] The present disclosure relates, in general, to radar system, and more specifically, relates to a system and method for real-time data management for radar signal processing.

BACKGROUND
[0002] The set of radar data is organized as a two-dimensional (2D) array with multiple lines of data. A 2D cross-point analysis is performed on each set of data to detect objects in a range of the radar system. A set of candidate objects is identified by performing an initial one-dimensional (1D) analysis on a line of data along a first axis of the set of data to determine a candidate location of each candidate object along the first axis, however, the set of candidate objects may include false objects. The set of candidate objects is pruned by performing a cross 1D analysis of the data along a second axis of the set of data at a position corresponding to each candidate location along the first axis to select a set of most likely candidate objects from the set of candidate objects.
[0003] Few existing schemes known in the art make data distribution cumbersome and implementation of algorithms difficult as referencing a sample solely depends on the counter or other arrangements. These conditions make it very difficult for the designer to navigate and distribute the data as per the architecture. Also, it is very difficult to capture instances when the repetition sequence is too long as a number of samples that can be captured by the integrated logic analyser is limited.
[0004] Therefore, there is a need in the art to provide a simple and efficient means that enables a reliable data referencing scheme suitable for real-time data management for radar signal processing.

OBJECTS OF THE PRESENT DISCLOSURE
[0005] An object of the present disclosure relates, in general, to radar system, and more specifically, relates to a system and method for real-time data management for radar signal processing.
[0006] Another object of the present disclosure provides a system that provides a unique ID based hardware description language (HDL) architecture memory mapping scheme for data storage and retrieval suitable for parallel and pipelined architectures in pulsed doppler radar signal processing.
[0007] Another object of the present disclosure provides signal processing algorithms that can be realized in parallel and pipelined architecture with easy data referencing.
[0008] Another object of the present disclosure facilitates conditional and selective data processing.
[0009] Another object of the present disclosure provides a system that enables an easier way to implement the signal processing algorithms and debug the application
[0010] Another object of the present disclosure provides a system that provides a unique ID that is associated with every incoming sample in addition to the flags.
[0011] Another object of the present disclosure provides a system that is convenient for data retrieval and data management.
[0012] Yet another object of the present disclosure provides a system that enables the associated unique ID is used as address for storing the data samples into the memory.

SUMMARY
[0013] The present disclosure relates, in general, to radar system, and more specifically, relates to a system and method for real-time data management for radar signal processing. The present disclosure relates to a unique identifier (ID) based parallel and pipelined Hardware description language (HDL) architecture for pulsed doppler radar signal processing. The pulsed doppler radar receives an ensemble of data. A single ensemble consists of echoes received for multiple pulse repetition intervals. The incoming data need to be organised and buffered into the memory for performing signal processing algorithms. The processing can be parallel or pipelined but requires reliable memory referencing scheme.
[0014] The unique ID based memory mapping scheme is suitable for parallel and pipelined software architectures in pulsed doppler radar signal processing, where a unique ID is associated with every incoming sample in addition to the flags. The unique memory mapping system where the associated unique ID is used as an address for storing the data samples into the memory. This unique ID is associated with the sample throughout the processing, which makes it easier to implement the signal processing algorithms and debug the application.
[0015] In an aspect, the present disclosure provides a system for real-time data management for radar signal processing, the system includes an analogue to digital converter (ADC) receives a set of signals from a plurality of receive channels and converts the received set of signals to a digital set of signals, a generator generates corresponding unique identifier (ID) for each of the received digital set of signals, wherein the unique ID associated with each of the digital set of signals used as address for memory, the unique ID is associated with each of the received digital set of signals in addition to flags and a processor operatively coupled to the memory, the processor configured to receive the digital set of signals associated with unique ID and uniquely identifies the digital set of signals with corresponding channel number, pulse number and range bin number, the processed data is received at an output unit to distribute output set of data for other subsystems.
[0016] According to an embodiment, the digital set of signals can include plurality of input channels, each input channel can include a plurality of pulse repetition intervals, each pulse repetition intervals can include a plurality of range bins.
[0017] According to an embodiment, the unique ID is formed by concatenating the pulse number, range bin number and an input channel number in any of the order.
[0018] According to an embodiment, the processor can include Field Programmable Gate Array (FPGA).
[0019] According to an embodiment, the digital set of signals is stored in any or a combination of FPGA memory or external memory.
[0020] According to an embodiment, the processor configured to process the digital set of signals associated with unique ID in any or a combination of parallel and pipelined manner.
[0021] According to an embodiment, the processing of the digital set of signals associated with unique ID enable easy data referencing and facilitates conditional and selective processing.
[0022] According to an embodiment, the processor coupled to an integrated logic analyzer to monitor and debug the digital set of signals.
[0023] In an aspect, the present disclosure provides a method for real-time data management for radar signal processing, the method includes receiving, at an analogue to digital converter (ADC), a set of signals and converts the received set of signals to digital set of signals, generating, at a generator, corresponding unique identifier (ID) for each of the digital set of signals, wherein the unique ID associated with each of the digital set of signals used as address into a memory; and analysing, at a processor, the received digital set of signals uniquely with corresponding channel number, pulse number and range bin number, the processed data is received at an output unit to distribute output set of data for other subsystems.
[0024] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The following drawings form part of the present specification and are included to further illustrate aspects of the present disclosure. The disclosure may be better understood by reference to the drawings in combination with the detailed description of the specific embodiments presented herein.
[0026] FIG. 1A illustrates a basic architecture for radar signal processing.
[0027] FIG. 1B illustrates a schematic view of ensemble of data.
[0028] FIG. 1C illustrates signal processing architecture of the system.
[0029] FIG. 2A illustrates an exemplary unique ID based radar signal processing scheme of system, in accordance with an embodiment of the present disclosure.
[0030] FIG. 2B illustrates an exemplary unique ID formation, in accordance with an embodiment of the present disclosure.
[0031] FIG. 3 illustrates an exemplary method for real-time data management for radar signal processing, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0032] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0033] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0034] FIG. 1A illustrates a basic architecture for radar signal processing.
[0035] Referring to FIG. 1A, pulse-Doppler radar (also referred to as system 100, herein) configured to propagate radar pulses generated by a transmitter and can receive a set of signals also interchangeably referred to as echo pulses for input to a receiver. The pulse-Doppler radar is a radar system that determines the range to a target using pulse-timing techniques and uses the Doppler effect of the returned signal to determine the target object's velocity.
[0036] System 100 can include analogue to digital converter (ADC) (102-1 to 102-N (which are collectively referred to as ADC 102, herein), multiplexer 104, memory 108 (also interchangeably referred to as buffer 108, herein), processor 110 and output buffer/unit 112. The radar can receive echoes from one or more receive channels (also referred to as receive channels, herein). These received echoes are down-converted, digitized and fed to the signal processor for processing is illustrated in FIG. 1A. The radar signal processing broadly covers the processing of the received echoes for target detection and extraction of target information like range, azimuth, elevation, doppler and the likes.
[0037] FIG. 1B illustrates a schematic view of ensemble of data. The receive channels receives an ensemble of data for every beam as illustrated in FIG. 1B. The ensemble can be processed with various algorithms to extract relevant information.
[0038] Radar signal processing can be of two types:
• On-fly processing: The incoming data need not be archived for processing. It is processed in real time. In this processing, pipeline delay may be minimal.
• Ensemble processing: The incoming ensemble data need to be archived before processing. The archived data is accessed as per the decided architecture during the processing stages.
[0039] The pulsed doppler radar requires ensemble processing since the signal processing algorithms are performed on the complete ensemble data, where the ensemble data can include number of pulses, number of range bins and number of channels.
[0040] FIG. 1C illustrates signal processing architecture of the system. The signal processing architecture of the system is shown in FIG. 1C include parallel and pipelined architecture. The parallel and pipelined architecture requires a reliable data referencing scheme.
[0041] Conventional schemes make data distribution cumbersome and implementation of algorithms is also difficult as referencing a sample solely depends on the counter or other arrangements. These conditions make it very difficult for the designer to navigate and distribute the data as per the architecture. Also, it is very difficult to capture instances when the repetition sequence is too long as the number of samples that can be captured by an integrated logic analyser 114 is limited. Therefore, a reliable memory mapping scheme suitable for data retrieval and management for radar signal processing on a Field Programmable Gate Arrays (FPGA) based platform is desired.
[0042] The present disclosure relates, in general, to radar system, and more specifically, relates to a system and method for real-time data management for radar signal processing. A method is devised to access, distribute and manage the incoming data. The present disclosure relates to a unique identifier (ID) based parallel and pipelined hardware description language (HDL) architecture for pulsed doppler radar signal processing. Every sample is associated with a unique ID which served the purpose of address and identifier, where the unique ID is used as address for memory access. The pulsed doppler radar receives an ensemble of data. A single ensemble consists of echoes received for multiple pulse repetition intervals. The incoming data need to be organised and buffered into the memory for performing signal processing algorithms. The processing can be parallel or pipelined but requires reliable memory referencing scheme.
[0043] The unique ID based memory mapping scheme is suitable for parallel and pipelined software architectures in pulsed doppler radar signal processing, where the unique ID is associated with every incoming sample in addition to the flags. The unique memory mapping system where the associated unique ID is used as an address for storing the data samples into the memory. This unique ID is associated with the sample throughout the processing, which makes it easier to implement the signal processing algorithms and debug the application. The present disclosure can be described in enabling detail in the following examples, which may represent more than one embodiment of the present disclosure.
[0044] FIG. 2A illustrates an exemplary unique ID based radar signal processing scheme of system, in accordance with an embodiment of the present disclosure.
[0045] Referring to FIG. 2A, system 100 configured to propagate radar pulses and can receive a set of signals also interchangeably referred to as echo pulses for input to the receiver. The radar can receive echoes from the receive channels. The proposed system 100 can include ADC (102-1 to 102-N (which are collectively referred to as ADC 102, herein), multiplexer 104, generator 106 (also interchangeably referred to as unique ID generator 106), memory 108 (also interchangeably referred to as buffer 108, herein), processor 110 and output buffer 112. The system 100 can be devised to access, distribute and manage the incoming data.
[0046] In an exemplary embodiment, the pulsed doppler radar receives the ensemble of data also called as dwell or burst data. The single ensemble consists of echoes received for multiple pulse repetition intervals. The incoming data also interchangeably referred to as a digital set of signals need to be organised and buffered into memory 108 for performing signal processing algorithms. The incoming data defines to the output of digital pulse compression stage in radar receive chain. The processing can be parallel or pipelined but requires reliable memory referencing scheme. The unique ID based memory mapping scheme suitable for parallel and pipelined software architectures in pulsed doppler radar signal processing is proposed. The unique ID is associated with every incoming sample in addition to the flags.
[0047] In an embodiment, the ADC 102 can receive the set of signals from the receive channels and convert the received set of signals to the digital set of signals. The digital set of signals can include a plurality of input channels, each input channel comprises a plurality of pulse repetition intervals, each pulse repetition interval comprises a plurality of range bins. The multiplexer 104 receives the digital set of signals and is conveyed to generator 106. The generator 106 is configured to receive the digital set of signals, the generator 106 can generate a corresponding unique ID for each of the digital set of signals, where the unique ID associated with each of the digital set of signals is used as an address into the memory 108. The unique ID is associated with each of the received digital set of signals in addition to flags. For example, every sample is associated with the unique ID which served the purpose of address and identifier, the address is replaced by the unique ID.
[0048] The processor 110 operatively coupled to the memory 108, the processor 110 configured to receive the digital set of signals associated with the unique ID. The processor 110 uniquely identifies the digital set of signals with corresponding channel number, pulse number and range bin number. The processed data is received by the output buffer/unit 112 to distribute the output set of data for the other subsystems.
[0049] Every incoming sample is assigned with the unique ID and archived into memory 108 with the associated unique ID serving the purpose of the memory address. During the signal processing stages, every sample is uniquely identified with its channel number, pulse number and range bin number. The processor 110 is operatively coupled to the integrated logic analyzer 114 to monitor and debug error conditions. It eases navigation to anticipated events during debugging the system.
[0050] In an exemplary embodiment, the unique ID can be formed by concatenating the pulse number, the range bin number and the input channel number, the unique ID can be associated with the sample throughout the processing. For example, ensemble of data can include 4 channels, 128 pulses and 2048 range bins, where the Unique ID = (pulse_no) & (range_bin) & (channel_no).
[0051] The processor 110 that can be in communication with each of the memory 108, and input/output units. The processor 110 may include a microprocessor or other devices capable of being programmed or configured to perform computations and instruction processing in accordance with the disclosure. In an exemplary embodiment, the processor may be field programmable gate arrays (FPGA). Such other devices may include microcontrollers, digital signal processors (DSP), complex programmable logic device (CPLD), application-specific integrated circuits (ASIC), discrete gate logic, and/or other assimilated circuits, hardware or firmware in lieu of or in addition to a microprocessor. The digital set of signals can be stored in any or a combination of FPGA memory or external memory.
[0052] FIG. 2B illustrates an exemplary unique ID formation, in accordance with an embodiment of the present disclosure.
[0053] Referring to FIG. 2B, the ensemble data also referred to as digital set of signals can include 4 channels, 128 pulses and 2048 range bins. The unique ID formation is illustrated in FIG. 2B includes a 20-bit long unique ID that is formed specifying the channel number, pulse repetition time and range bin. As shown in FIG. 2B, out of 20 bits, 2 bits (bit 0 and bit 1) are assigned to the channel number, 11 bits (bit 2 to bit 12) are assigned to range bin number and 7 bits (bit 13 to bit 19) are assigned to pulse repetition number. For example, 2 bits (bit 0 and bit 1) are assigned to the 4 channels, 7 bits (bit 13 to bit 19) are assigned to 128 pulses and 11 bits (bit 2 to bit 12) are assigned to 2048 range bins. The unique ID can be formed by concatenating channel number, pulse number and range bin number in any order.
[0054] Every incoming sample is assigned with the unique ID and archived into the memory 108 with the associated unique ID serving the purpose of memory address. During the signal processing stages, every sample is uniquely identified with its channel number, pulse number and range bin number by the processor 110. Signal processing algorithms can be realized in parallel and pipelined architecture with easy data referencing. This also facilitates in conditional and selective processing. It eases navigation to anticipated events during debugging the system.
[0055] The embodiments of the present disclosure described above provide several advantages. The one or more of the embodiments provides the system 100 that enables unique ID based HDL architecture memory mapping scheme for data storage and retrieval suitable for parallel and pipelined architectures in pulsed doppler radar signal processing. The present disclosure provides signal processing algorithms that can be realized in parallel and pipelined architecture with easy data referencing. The present disclosure facilitates conditional and selective processing. The system 100 enables easier way to implement the signal processing algorithms and debug the application. The system provides a unique ID that is associated with every incoming sample in addition to the flags. The system 100 is convenient for data retrieval and data management. The associated unique ID is used as address for storing the data samples into the memory.
[0056] FIG. 3 illustrates an exemplary method 300 for real-time data management for radar signal processing, in accordance with an embodiment of the present disclosure.
[0057] Referring to FIG. 3, at block 302 analogue to digital converter (ADC) 102 can receive the set of signals and can convert the received set of signals to the digital set of signals. At block 304, the generator 106 can generate the corresponding unique ID for each of the digital set of signals, where the unique ID associated with each of the digital set of signals used as address into the memory 108.
[0058] The digital set of signals can include plurality of input channels, each input channel comprises plurality of pulse repetition intervals, each pulse repetition intervals comprises a plurality of range bins. The unique ID is formed by concatenating the pulse number, range bin number and an input channel number in any of the order. The processor 110 uniquely identifies the digitals set of signals with corresponding channel number, pulse number and range bin number.
[0059] At block 306, processor 110 can uniquely identifies the digital set of signals with corresponding channel number, pulse number and range bin number, the processed data is received by the output unit 112 to distribute output set of data for other subsystem.
[0060] It will be apparent to those skilled in the art that the system 100 of the disclosure may be provided using some or all of the mentioned features and components without departing from the scope of the present disclosure. While various embodiments of the present disclosure have been illustrated and described herein, it will be clear that the disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the scope of the disclosure, as described in the claims.

ADVANTAGES OF THE PRESENT DISCLOSURE
[0061] The present disclosure provides a system that provides unique ID based hardware description language (HDL) architecture memory mapping scheme for data storage and retrieval suitable for parallel and pipelined architectures in pulsed doppler radar signal processing.
[0062] The present disclosure provides signal processing algorithms that can be realized in parallel and pipelined architecture with easy data referencing.
[0063] The present disclosure facilitates conditional and selective processing.
[0064] The present disclosure provides a system that enables easier way to implement the signal processing algorithms and debug the application.
[0065] The present disclosure provides a system that provides a unique ID that is associated with every incoming sample in addition to the flags.
[0066] The present disclosure provides a system that convenient for data retrieval and data management.
[0067] The present disclosure provides a system that enables the associated unique ID is used as address for storing the data samples into the memory.