CROSS-REFERENCE TO RELATED APPLICATIONS AND PRIORITY
[001] The present application does not claim priority from any patent application.

TECHNICAL FIELD
[002] The present disclosure in general relates to the field of memory diagnostics. More particularly, the present invention relates to a system and method for memory diagnostics at runtime.
BACKGROUND
[003] With the development in the field of Information Technology (IT) and electronics, the use of microprocessors in real-time system has increased marginally. With the use of microprocessors it is now possible to continuously monitor real-time applications such as mission critical systems or safety systems. These systems are deployed at remote location and cannot be readily accessed for maintenance and repair. These mission critical systems may be installed in satellites, drones and flight navigation applications which have a limited accessibility and need to be operational 24x7. Such systems require failsafe and comprehensive RAM diagnostics, which is capable of detecting memory issues during normal system operation.
[004] In some cases, bad memory (RAM) can be catastrophic for such applications. In the existing art typical RAM diagnostics solutions are available as part of POST request process. However, the available methods for run-time RAM diagnostics have various limitations such as impact on application performance, limited RAM coverage, lack of diagnostics for DMA regions, lack of failsafe solution.

SUMMARY
[005] This summary is provided to introduce aspects related to systems and methods for memory diagnostics and allocation and the aspects are further described below in the detailed description. This summary is not intended to identify essential features of the claimed subject matter nor is it intended for use in determining or limiting the scope of the claimed subject matter.
[006] In one embodiment, a method for runtime diagnostics and allocation of memory is disclosed. The memory may be a dynamic memory such as a Synchronous Dynamic Random Access Memory (SDRAM). Initially, a processor is configured to execute programmed instructions stored in a memory unit for identifying a set of memory blocks from a memory that are not occupied by a Direct Memory Access (DMA) operation performed in the memory. In one embodiment, the memory unit may be a Static Random Access Memory (SRAM), wherein the SRAM is configured to store a memory diagnostics program in the form of programmed instructions, and wherein the memory diagnostics program is configured to perform memory diagnostics of the memory. Further, the processor is configured for identifying a set of corrupted memory blocks from the set of memory blocks based upon a predefined pattern. Once the set of corrupted memory blocks is identified, address details of the set of corrupted memory blocks are stored in the memory unit. Further, the processor is configured to generate alerts to change a set of memory modules in the memory, wherein the set of memory modules is associated with the set of corrupted memory blocks, and wherein the alerts are generated based on the number of corrupted memory blocks.
[007] In one embodiment, a system for runtime diagnostics and allocation of memory is disclosed. The system comprises a memory, a processor coupled to the memory, wherein the processor is configured to execute programmed instructions stored in the memory unit, and wherein the memory may be a dynamic memory such as a Synchronous Dynamic Random Access Memory (SDRAM). Initially, the processor is configured to execute the programmed instructions stored in a memory unit for identifying a set of memory blocks from the memory that are not occupied by a Direct Memory Access (DMA) operation performed in the memory. In one embodiment, the memory unit may be a Static Random Access Memory (SRAM), wherein the SRAM is configured to store a memory diagnostics program in the form of the programmed instructions, and wherein the memory diagnostics program is configured to perform memory diagnostics of the memory. Further, the processor is configured for identifying a set of corrupted memory blocks from the set of memory blocks based upon a predefined pattern. Once the set of corrupted memory blocks is identified, address details of the set of corrupted memory blocks are stored in the memory unit. Further, the processor facilitates generating alerts to change a set of memory modules in the memory, wherein the set of memory modules is associated with the set of corrupted memory blocks, and wherein the alerts are generated based on the number of corrupted memory blocks.
[008] In one embodiment, a computer program product having embodied computer program for runtime diagnostics and allocation of a memory is disclosed. The computer program product comprises a program code stored in a memory unit for identifying a set of memory blocks from the memory that are not occupied by a Direct Memory Access (DMA) operation performed in the memory. In one embodiment, the memory unit may be a Static Random Access Memory (SRAM), wherein the SRAM is configured to store a memory diagnostics program in the form of the programmed instructions. Further, computer program product comprises a program code stored in a memory unit for identifying a set of corrupted memory blocks from the set of memory blocks based upon a predefined pattern. Further, computer program product comprises a program code stored in a memory unit for storing the address details of the set of corrupted memory blocks in the memory. Further, the computer program product comprises a program code stored in a memory unit for generating alerts to change a set of memory modules in the memory, wherein the set of memory modules is associated with the set of corrupted memory blocks, and wherein the alerts are generated based on the number of corrupted memory blocks.

BRIEF DESCRIPTION OF DRAWINGS
[009] The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to refer like features and components.
[0010] Figure 1 illustrates a network implementation of a system for runtime diagnostics and allocation of memory is illustrated, in accordance with an embodiment of the present subject matter.
[0011] Figure 2 illustrates the system for runtime diagnostics and allocation of memory, in accordance with an embodiment of the present subject matter.
[0012] Figure 3 illustrates a block diagram of the system for runtime diagnostics and allocation of memory, in accordance with an embodiment of the present subject matter.

DETAILED DESCRIPTION
[0013] In one embodiment, a system for runtime diagnostics and allocation of memory is disclosed. The system comprises a memory unit, a processor coupled to the memory unit and the memory, wherein the memory may a dynamic memory such as a Synchronous Dynamic Random Access Memory (SDRAM). Initially, the processor is configured to execute programmed instructions stored in a memory unit for identifying a set of memory blocks from the memory that are not occupied by a Direct Memory Access (DMA) operation performed in the memory.
[0014] In one embodiment, the memory unit may be a Static Random Access Memory (SRAM) and wherein the SRAM is configured to store a memory diagnostics program in the form of the programmed instructions, wherein the memory diagnostics program is configured to perform memory diagnostics of the memory. Further, the processor is configured for identifying a set of corrupted memory blocks from the set of memory blocks based upon a predefined pattern. Once the set of corrupted memory blocks is identified, address details of the set of corrupted memory blocks are stored in the memory unit. Further, the processor is configured to generate alerts to change a set of memory modules in the memory, wherein the set of memory modules is associated with the set of corrupted memory blocks, and wherein the alerts are generated based on the number of corrupted memory blocks.
[0015] While aspects of described system and method for runtime diagnostics and allocation of memory may be implemented in any number of different computing systems, environments, and/or configurations, the embodiments are described in the context of the following exemplary system.
[0016] Referring now to Figure 1, a network implementation 100 of a system 102 for runtime diagnostics and allocation of memory. Although the present subject matter is explained considering that the system 102 is implemented on a server of a mission critical operation, it may be understood that the system 102 may also be implemented in a variety of computing systems, such as a laptop computer, a desktop computer, a notebook, a workstation, a mainframe computer, a server, a network server, and the like. In one implementation, the system 102 may be implemented in a cloud-based environment. It will be understood that the system 102 may be accessed by multiple users through one or more user devices 104-1, 104-2…104-N, collectively referred to as user devices 104 hereinafter, or applications residing on the user devices 104. Examples of the user devices 104 may include, but are not limited to, a portable computer, a personal digital assistant, a handheld device, and a workstation. The user devices 104 are communicatively coupled to the system 102 through a network 106.
[0017] In one embodiment, the present invention is specifically targeted for safety / mission critical system 102, hereafter referred to as system 102 and provides failsafe operation with comprehensive coverage of memory, more specifically SDRAM without impacting application running on the SDRAM. Initially, the system 102 enables identification of memory blocks which are occupied by DMA operations which are running on the SDRAM during normal operation of the system 102 using integrity check. This increases coverage and reduces impact on application performance. Further, the system 102 may identify coverage of DMA regions using mutually exclusive operation and device drivers in the system 102 that involve DMA transfer over the SDRAM.
[0018] Further, the system 102 maintains memory diagnostic application/ algorithm at the memory unit (SRAM) in the form of programmed instructions for integrity checking of memory (SDRAM). The memory diagnostic application is configured to manage runtime diagnostics of the SDRAM on a continuous basis and is configured to work with existing system management application running on the SDRAM. Further, the memory diagnostics application also identifies a set of corrupted memory blocks from the memory (SDRAM). The memory diagnostic application provides well defined message based interface and can be adapted as per system requirement.
[0019] In one implementation, the network 106 may be a wireless network, a wired network or a combination thereof. The network 106 can be implemented as one of the different types of networks, such as intranet, local area network (LAN), wide area network (WAN), the internet, and the like. The network 106 may either be a dedicated network or a shared network. The shared network represents an association of the different types of networks that use a variety of protocols, for example, Constrained Application Protocol (CoAP), Hypertext Transfer Protocol (HTTP), Transmission Control Protocol/Internet Protocol (TCP/IP), Wireless Application Protocol (WAP), and the like, to communicate with one another. Further the network 106 may include a variety of network devices, including routers, bridges, servers, computing devices, storage devices, and the like. The process of memory diagnostics is further explained with respect to the Figure 2.
[0020] Referring now to Figure 2, the system 102 is illustrated in accordance with an embodiment of the present subject matter. In one embodiment, the system 102 may include at least one processor 202, an input/output (I/O) interface 204, and a memory unit 206 and a memory 208. The memory unit 206 may be in the form of an SRAM storing modules 212 for performing diagnostics of memory 208. In one embodiment, the memory 208 may be a collection of memory modules, wherein each memory module is configured to maintain a set of memory blocks for storing data. Further, the at least one processor 202 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuitries, and/or any devices that manipulate signals based on operational instructions. Among other capabilities, the at least one processor 202 is configured to fetch and execute computer-readable instructions stored in the memory unit 206. Further, the memory unit 206 is configured to store modules 212 and data 210.
[0021] The I/O interface 204 may include a variety of software and hardware interfaces, for example, a web interface, a graphical user interface, and the like. The I/O interface 204 may allow the system 102 to interact with a user directly or through the client devices 104. Further, the I/O interface 204 may enable the system 102 to communicate with other computing devices, such as web servers and external data servers (not shown). The I/O interface 204 can facilitate multiple communications within a wide variety of networks and protocol types, including wired networks, for example, LAN, cable, etc., and wireless networks, such as WLAN, cellular, or satellite. The I/O interface 204 may include one or more ports for connecting a number of devices to one another or to another server.
[0022] Further, the modules 212 include routines, programs, objects, components, data structures, etc., which perform particular tasks, functions or implement particular abstract data types. In one implementation, the modules 212 may include a memory block analysis module 214, a corrupted memory detection module 216, an address detection module 218, and a communication module 220. The memory block analysis module 214, the corrupted memory detection module 216, the address detection module 218, and the communication module 220 constitute the memory diagnostics program stored in the memory unit 206. Further, the memory 208 is configured to store a system management application 228, operating system applications 230, and DMA applications 232. Further a database 222 stored in the data 210 is configured to maintain results of memory diagnostics performed by the memory block analysis module 214. The data 210, amongst other things, serves as a repository for storing data processed, received, and generated by one or more of the modules 212. In one embodiment, the integrity of the memory diagnostics algorithm is checked by the system management application 228. The system management application 228 may enable a memory diagnostics management application for checking the integrity of the memory diagnostics algorithm at the time of booting the system 102.
[0023] Once the integrity of the memory diagnostics algorithm is checked, the system 102 enables a RAM diagnostics driver for initiating the memory diagnostics process. The RAM diagnostics driver is a character driver which provides kernel level memory Diagnostic APIs to user-level and user space applications, primarily RAM Diagnostic Managerial layer. The RAM diagnostics driver also Manages RAM Diagnostic sessions. Initially, the RAM diagnostics driver maps SRAMs separately into non-cacheable kernel’s paged virtual memory map so that SRAMs can be used for the modules 212. The SRAM is mapped to non-cacheable addresses to access SDRAM in RAM Diagnostic driver so that every access by passes the cache.
[0024] In one embodiment, the RAM diagnostics driver is configured to make sure that read and write operations to SDRAM locations are atomic. For this purpose, the RAM diagnostics driver may disable the interrupts just before jumping to SRAM to execute the memory diagnostics program. The interrupts are enabled after returning from one scan session.
[0025] The RAM Diagnostic driver also maintains an array of structure for storing starting and ending logical addresses of consistent DMA allocations done by other drivers. This array is used in making the decision of skipping certain chunks of memory region falling in consistent DMA regions. The RAM diagnostics driver also exports the APIs to update this structure to other drivers so that all the drivers in the system use a consistent interface for updating this structure and also ensure mutually exclusive access of this structure among various drivers running in the memory 108.
[0026] In one embodiment, the RAM Diagnostic driver is configured to identify any streaming DMA buffer allocation in the kernel address space before calling the memory diagnostics program from the SRAM. If RAM Diagnostic driver identifies that any system driver has allocated streaming DMA buffer, RAM diagnostics driver does not call the memory diagnostics program. This is done to ensure smooth and error free DMA operations inside the system 102. If the memory diagnostics program is called in the presence of streaming DMA allocations in the kernel space, and this algorithm happens to scan the same kernel region, DMA buffer data may be corrupted, and hence can affect the smooth operation of the device using that data. Since these streaming DMA allocations are used very frequently by drivers like Ethernet, etc. it is not possible to keep tract of these random allocations inside the kernel space. Hence the RAM diagnostics driver stops memory Diagnostic program for the time these buffers exist in the kernel space. This strategy requires very careful implementation using kernel level semaphores/mutex to ensure that the global flag used by these device drivers to signal RAM Diagnostic driver about streaming DMA allocation is not in inconsistent state when RAM Diagnostic driver reads it.
[0027] In one embodiment, once the RAM Diagnostic driver analyses the memory, the memory block analysis module 214 is configured for identifying a set of memory blocks from the memory 208 that are not occupied by the Direct Memory Access (DMA) operation performed in the memory 208. The memory 208 may be configured for running system management application 228, operating system applications 230 and DMA applications 232. The set of memory block are memory locations from the memory 208 that are not occupied by any Direct Memory Access (DMA) operation performed in the memory 208.
[0028] In one embodiment, the corrupted memory detection module 216 is configured to scan only 32-bits (4 bytes) of the set of memory block in one session and identify the set of corrupted memory blocks. This is done to ensure the responsiveness of the memory 208. In every scan session, the data of the four memory blocks is stored in a backup register, then these memory blocks are written with a specific pattern and then this pattern is read. If the read cycle is successful, then and anti-pattern is written to these locations. If the read cycle of this anti-pattern is also successful, the original data is restored in these locations from the backup register and the session is reported to be successful.
[0029] In one embodiment, the corrupted memory detection module 216 is configured to write a predefined pattern and anti-pattern to memory location in order to make sure that each and every memory location bit is capable of storing both 1 and 0 values. If a memory block is not capable of storing 1 and/ or 0 value, the memory block is identified as a corrupted memory block. In one embodiment, all the corrupted memory blocks from the set of memory blocks are identified and a set of corrupted memory blocks is generated. Further, the address details of the set of corrupted memory blocks are identified by the address detection module 218 and stored in the memory unit 206.
[0030] In one embodiment, these address details are communicated to the processor 202 by the communication module 220 for facilitating efficient memory allocation and replacement, for the processes running on the memory 208. More specifically the processor is configured to generate alerts to change a set of memory modules, in the memory 208, which is associated with the set of corrupted memory blocks. These alerts may be communicated to the user, over the electronic device 104, by the communication module 220. In one embodiment, the alerts are generated based on the number of corrupted memory blocks. Further, based on the frequency of alerts that are generated, the user may decide to change the set of memory modules or the memory 208 itself. The process of memory diagnostics is further explained with respect to the flowchart of figure 3.
[0031] Figure 3 represent a block diagram for memory diagnostics and allocation. Once the user starts the system 102, the process of memory diagnostics is run on continuous bases. At block 302, the memory block analysis module 214 is configured to identify a set of memory blocks from a memory that are not occupied by Direct Memory Access (DMA) operation performed in the memory 208.
[0032] At block 304, the corrupted memory detection module 216 is configured to identify a set of corrupted memory blocks from the set of memory blocks using a set of pattern and anti-patterns.
[0033] At block 306, the address detection module 218 is configured to store address details of the set of corrupted memory blocks in the memory unit 206.
[0034] At block 308, the communication module 220 is configured to communicate the address details of the set of corrupted memory blocks to the processor 202 for facilitating generation of alerts to change a set of memory modules in the memory, wherein the set of memory modules is associated with the set of corrupted memory blocks, wherein the alerts are generated based on the number of corrupted memory blocks.
[0035] Although implementation of methods and systems for memory diagnostics is disclosed, it is to be understood that the appended claims are not necessarily limited to the specific features or methods described herein. Rather, the specific features and methods are disclosed as examples of memory diagnostics at runtime.

Claims:1. A system for dynamic allocation of a memory, the system comprising:
a memory unit; and
a processor coupled to the memory unit, wherein the processor is configured to execute a set of instructions stored in the memory unit for:
identifying a set of memory blocks from a memory that are not occupied by:
a Direct Memory Access (DMA) operation performed in the memory;
identifying a set of corrupted memory blocks from the set of memory blocks based upon a predefined pattern;
storing address details of the set of corrupted memory blocks in the memory unit; and
facilitating generation of alerts to change a set of memory modules in the memory, wherein the set of memory modules are associated with the set of corrupted memory blocks, wherein the alerts are generated based on the number of corrupted memory blocks.

2. The system of claim 1, wherein the memory is an Synchronous Dynamic Random Access Memory (SDRAM) and the memory unit is a Static Random Access Memory (SRAM).

3. The system of claim 1, wherein the memory is configured to execute one or more software applications, wherein the software applications include an operating system application or a mission critical software application.

4. The system of claim 1, wherein the set of corrupted memory blocks is identified by writing and reading the pattern on the set of memory blocks to the capacity, wherein the writing and reading the pattern in each memory block enables determining the capacity of each bit from a memory block to store binary values.

5. A method for dynamic allocation of a memory, the method comprising:
identifying, by a processor, a set of memory blocks from a memory that are not occupied by:
a Direct Memory Access (DMA) operation performed in the memory;
identifying, by the processor, a set of corrupted memory blocks from the set of memory blocks based upon a predefined pattern;
storing, by the processor, address details of the set of corrupted memory blocks in the memory unit; and
facilitating, by the processor, generation of alerts to change a set of memory modules in the memory, wherein the set of memory modules are associated with the set of corrupted memory blocks, wherein the alerts are generated based on the number of corrupted memory blocks.

6. The method of claim 5, wherein the memory is an Synchronous Dynamic Random Access Memory (SDRAM) and the memory unit is a Static Random Access Memory (SRAM).

7. The method of claim 5, wherein the memory is configured to execute one or more software applications, wherein the software applications include an operating system application or a mission critical software application.

8. The method of claim 5, wherein the set of corrupted memory blocks is identified by writing and reading the pattern on the set of memory blocks to the capacity, wherein the writing and reading the pattern in each memory block enables determining the capacity of each bit from a memory block to store binary values.

9. A computer program product having embodied thereon a computer program for dynamic allocation of a memory, the computer program product comprising:
a program code for identifying a set of memory blocks from a memory that are not occupied by:
a Direct Memory Access (DMA) operation performed in the memory;
a program code for identifying a set of corrupted memory blocks from the set of memory blocks based upon a predefined pattern;
a program code for storing address details of the set of corrupted memory blocks in the memory unit; and
a program code for facilitating generation of alerts to change a set of memory modules in the memory, wherein the set of memory modules are associated with the set of corrupted memory blocks, wherein the alerts are generated based on the number of corrupted memory blocks.