Abstract: Embodiments of present disclosure disclose a method and a system for selecting victim memory block for garbage collection. A memory block having minimum valid unit count is identified. Wear count bit of memory block to be null wear count or non-null wear count is determined. Memory block is selected as victim memory block for garbage collection upon determining memory block having null wear count. A plurality of memory blocks are divided into first set of memory blocks and second set of memory blocks upon determining memory block having non-null wear count. Minimum valid unit count and wear count bit are identified for each memory block in each set. Division is iterated until a first target memory block having minimum valid unit count and null wear count from one of first set of memory blocks and second set of memory blocks is identified. Final target memory block is selected as victim memory block for garbage collection. FIGURE 2
CLIAMS:We claim:
1. A method for selecting a victim memory block in a storage device for garbage collection comprising:
identifying, by a block selection system, a memory block having a minimum valid unit count among a plurality of memory blocks in the storage device;
determining, by the block selection system, a wear count bit of the identified memory block to be one of a null wear count and a non-null wear count;
selecting, by the block selection system, the identified memory block as the victim memory block for garbage collection upon determining the identified memory block having the null wear count; and
performing, by the block selection system, upon determining the identified memory block having the non-null wear count:
dividing the plurality of memory blocks into a first set of memory blocks and a second set of memory blocks, wherein a minimum valid unit count and a wear count bit is identified for each memory block in the first set of memory blocks and the second set of memory blocks;
iterating the division until a first target memory block having the minimum valid unit count and the null wear count from one of the first set of memory blocks and the second set of memory blocks is identified; and
selecting the target memory block as the victim memory block for garbage collection.
2. The method as claimed in claim 1 further comprising:
identifying, by the block selection system, a second target memory block having the minimum valid unit count and the null wear count from remaining set of memory blocks of the first set of memory blocks and the second set of memory blocks during the iteration; and
merging, by the block selection system, the first target memory block and the second target memory block for garbage collection.
3. The method as claimed in claim 1, wherein the plurality of memory blocks is divided into the first set of memory blocks and the second set of memory blocks by masking the identified memory block having non-null wear count.
4. The method as claimed in claim 1, wherein the wear count bit relates to a wear count of the identified memory block that corresponds to number of times the memory block is used for garbage collection.
5. The method as claimed in claim 1, wherein the wear count bit of the identified memory block is null when the identified memory block is never used for garbage collection.
6. The method as claimed in claim 1, wherein the wear count bit of the identified memory block is non-null when the identified memory block is used at least once for garbage collection.
7. A block selection system for selecting a victim memory block in a storage device for garbage collection comprising:
a processor;
a memory communicatively coupled to the processor, wherein the memory stores processor-executable instructions, which, on execution, cause the processor to:
identify a memory block having a minimum valid unit count among a plurality of memory blocks in the storage device;
determine a wear count bit of the identified memory block to be one of a null wear count and a non-null wear count;
select the identified memory block as the victim memory block for garbage collection upon determining the identified memory block having the null wear count; and
perform upon determining the identified memory block having the non-null wear count:
divide the plurality of memory blocks into a first set of memory blocks and a second set of memory blocks, wherein a minimum valid unit count and a wear count bit is identified for each memory block in the first set of memory blocks and the second set of memory blocks;
iterate the division until a first target memory block having the minimum valid unit count and the null wear count from one of the first set of memory blocks and the second set of memory blocks is identified; and
select the final target memory block as the victim memory block for garbage collection.
8. The block selection system as claimed in claim 8, wherein the processor is further configured to:
identify a second target memory block having the minimum valid unit count and the null wear count from remaining set of memory blocks of the first set of memory blocks and the second set of memory blocks during the iteration; and
merge the first target memory block and the second target memory block for garbage collection.
9. The block selection system as claimed in claim 7, wherein the processor masks the identified memory block having non-null wear count to divide the plurality of memory blocks into the first set of memory blocks and the second set of memory blocks.
10. The block selection system as claimed in claim 7, wherein the wear count bit relates to a wear count of the identified memory block that corresponds to number of times the memory block is used for garbage collection.
11. The block selection system as claimed in claim 7, wherein the wear count bit of the identified memory block is null when the identified memory block is never used for garbage collection.
12. The block selection system as claimed in claim 7, wherein the wear count bit of the identified memory block is non-null when the identified memory block is used at least once for garbage collection.
13. A non-transitory computer readable medium including instructions stored thereon that when processed by a processor cause a block selection system to perform acts of:
identifying a memory block having a minimum valid unit count among a plurality of memory blocks in a storage device;
determining a wear count bit of the identified memory block to be one of a null wear count and a non-null wear count;
selecting the identified memory block as the victim memory block for garbage collection upon determining the identified memory block having the null wear count; and
performing upon determining the identified memory block having the non-null wear count:
dividing the plurality of memory blocks into a first set of memory blocks and a second set of memory blocks, wherein a minimum valid unit count and a wear count bit is identified for each memory block in the first set of memory blocks and the second set of memory blocks;
iterating the division until a first target memory block having the minimum valid unit count and the null wear count from one of the first set of memory blocks and the second set of memory blocks is identified; and
selecting the final target memory block as the victim memory block for garbage collection.
Dated this 28th day of March 2015
SHWETHA A CHIMALGI
OF K & S PARTNERS
AGENT FOR THE APPLICANT
,TagSPECI:TECHNICAL FIELD
The present subject matter is related, in general to a storage device and more particularly, but not exclusively to a method and a system for selecting a victim memory block in a storage device for garbage collection.
| Section | Controller | Decision Date |
|---|---|---|
| # | Name | Date |
|---|---|---|
| 1 | 1601-CHE-2014 FORM-9 28-03-2015.pdf | 2015-03-28 |
| 1 | 1601-CHE-2015-RELEVANT DOCUMENTS [20-09-2023(online)].pdf | 2023-09-20 |
| 2 | 1601-CHE-2014 FORM-18 28-03-2015.pdf | 2015-03-28 |
| 2 | 1601-CHE-2015-PROOF OF ALTERATION [11-03-2022(online)].pdf | 2022-03-11 |
| 3 | 1601CHE2015_CertifiedCopyRequest.pdf | 2015-04-08 |
| 3 | 1601-CHE-2015-US(14)-HearingNotice-(HearingDate-02-11-2020).pdf | 2021-10-17 |
| 4 | IP30270-spec.pdf | 2015-04-13 |
| 4 | 1601-CHE-2015-IntimationOfGrant03-05-2021.pdf | 2021-05-03 |
| 5 | IP30270-fig.pdf | 2015-04-13 |
| 5 | 1601-CHE-2015-PatentCertificate03-05-2021.pdf | 2021-05-03 |
| 6 | FORM 5-IP30270.pdf | 2015-04-13 |
| 6 | 1601-CHE-2015-Annexure [17-11-2020(online)].pdf | 2020-11-17 |
| 7 | FORM 3-IP30270.pdf | 2015-04-13 |
| 7 | 1601-CHE-2015-PETITION UNDER RULE 137 [17-11-2020(online)].pdf | 2020-11-17 |
| 8 | abstract 1601-CHE-2015.jpg | 2015-04-22 |
| 8 | 1601-CHE-2015-RELEVANT DOCUMENTS [17-11-2020(online)].pdf | 2020-11-17 |
| 9 | 1601-CHE-2015 POWER OF ATTORNEY 26-06-2015.pdf | 2015-06-26 |
| 9 | 1601-CHE-2015-Written submissions and relevant documents [17-11-2020(online)].pdf | 2020-11-17 |
| 10 | 1601-CHE-2015 FORM-1 26-06-2015.pdf | 2015-06-26 |
| 10 | 1601-CHE-2015-Correspondence to notify the Controller [01-10-2020(online)].pdf | 2020-10-01 |
| 11 | 1601-CHE-2015 CORRESPONDENCE OTHERS 26-06-2015.pdf | 2015-06-26 |
| 11 | 1601-CHE-2015-FORM-26 [01-10-2020(online)].pdf | 2020-10-01 |
| 12 | 1601-CHE-2015-FER_SER_REPLY [13-05-2020(online)].pdf | 2020-05-13 |
| 12 | REQUEST FOR CERTIFIED COPY [23-03-2016(online)].pdf | 2016-03-23 |
| 13 | 1601-CHE-2015-FORM 3 [13-05-2020(online)].pdf | 2020-05-13 |
| 13 | CERTIFIED COPIES US 72 OR FOR CERTIFICATE US-147 AND RULE 133(2) [20-02-2017(online)].pdf | 2017-02-20 |
| 14 | 1601-CHE-2015-FER.pdf | 2019-11-14 |
| 14 | CERTIFIED COPIES US 72 OR FOR CERTIFICATE US-147AND RULE 133(2) Copy-Online.pdf | 2017-02-21 |
| 15 | 1601-CHE-2015-FER.pdf | 2019-11-14 |
| 15 | CERTIFIED COPIES US 72 OR FOR CERTIFICATE US-147AND RULE 133(2) Copy-Online.pdf | 2017-02-21 |
| 16 | 1601-CHE-2015-FORM 3 [13-05-2020(online)].pdf | 2020-05-13 |
| 16 | CERTIFIED COPIES US 72 OR FOR CERTIFICATE US-147 AND RULE 133(2) [20-02-2017(online)].pdf | 2017-02-20 |
| 17 | REQUEST FOR CERTIFIED COPY [23-03-2016(online)].pdf | 2016-03-23 |
| 17 | 1601-CHE-2015-FER_SER_REPLY [13-05-2020(online)].pdf | 2020-05-13 |
| 18 | 1601-CHE-2015 CORRESPONDENCE OTHERS 26-06-2015.pdf | 2015-06-26 |
| 18 | 1601-CHE-2015-FORM-26 [01-10-2020(online)].pdf | 2020-10-01 |
| 19 | 1601-CHE-2015 FORM-1 26-06-2015.pdf | 2015-06-26 |
| 19 | 1601-CHE-2015-Correspondence to notify the Controller [01-10-2020(online)].pdf | 2020-10-01 |
| 20 | 1601-CHE-2015 POWER OF ATTORNEY 26-06-2015.pdf | 2015-06-26 |
| 20 | 1601-CHE-2015-Written submissions and relevant documents [17-11-2020(online)].pdf | 2020-11-17 |
| 21 | 1601-CHE-2015-RELEVANT DOCUMENTS [17-11-2020(online)].pdf | 2020-11-17 |
| 21 | abstract 1601-CHE-2015.jpg | 2015-04-22 |
| 22 | 1601-CHE-2015-PETITION UNDER RULE 137 [17-11-2020(online)].pdf | 2020-11-17 |
| 22 | FORM 3-IP30270.pdf | 2015-04-13 |
| 23 | 1601-CHE-2015-Annexure [17-11-2020(online)].pdf | 2020-11-17 |
| 23 | FORM 5-IP30270.pdf | 2015-04-13 |
| 24 | 1601-CHE-2015-PatentCertificate03-05-2021.pdf | 2021-05-03 |
| 24 | IP30270-fig.pdf | 2015-04-13 |
| 25 | IP30270-spec.pdf | 2015-04-13 |
| 25 | 1601-CHE-2015-IntimationOfGrant03-05-2021.pdf | 2021-05-03 |
| 26 | 1601CHE2015_CertifiedCopyRequest.pdf | 2015-04-08 |
| 26 | 1601-CHE-2015-US(14)-HearingNotice-(HearingDate-02-11-2020).pdf | 2021-10-17 |
| 27 | 1601-CHE-2015-PROOF OF ALTERATION [11-03-2022(online)].pdf | 2022-03-11 |
| 27 | 1601-CHE-2014 FORM-18 28-03-2015.pdf | 2015-03-28 |
| 28 | 1601-CHE-2015-RELEVANT DOCUMENTS [20-09-2023(online)].pdf | 2023-09-20 |
| 28 | 1601-CHE-2014 FORM-9 28-03-2015.pdf | 2015-03-28 |
| 1 | 26thfile_14-11-2019.pdf |