System and method for time synchronization between channels of a multi-channel reception system for radio signals The present invention relates to a device for synchronization between channels adapted to be inserted into a reception channel of a multi-channel reception system for radio signals, as well as a system and a method for synchronization between channels of a multi-channel reception system. radio signals. The invention lies in the general field of multichannel reception systems for radio signals, used in many fields such as amplitude direction finding, interferometry, multistatic synthetic aperture radar systems, frequency measurements and medical imaging. In a known manner, in a multi-channel reception system, each reception channel comprises a reception chain delivering an electrical signal at the input of an analog-to-digital converter having an associated sampling frequency, and an interfacing module connected at the output of said analog-to-digital converter and suitable for supplying the digitized signal samples at the input of a digital signal processing module in packets of samples, that is to say with a minimum of parallelization. This is due to the fact that a digital signal processing module comprises one or more programmable digital components of the FPGA (Field Programmable Gâte Arraÿ) type, the working frequency of which is much lower than the sampling frequency of the analog-to-digital conversion. In particular for applications which exploit the phase shift between reception channels, for example for interferometry, it is necessary that the samples from each channel relate to the same time slot of the radio signals picked up at the input of the reception channels, or, in other words, that the sample packets are synchronized between reception channels. In addition, it is necessary for the synchronization between reception channels to be stable and reproducible. There are various possible causes of desynchronization between receive channels. For example, when all the reception channels include an analog-to-digital converter operating at a sampling frequency of Fe. This is the case for reception chains respecting the Shannon condition, performing filtering with a bandwidth less than Fe / 2 before digital-to-analog conversion. The frequency Fe is very high and much higher than the maximum operating frequency of programmable digital components. Interfacing modules are used, for example demultiplexers which may include one or more demultiplexing stages, which provide sets of P samples in parallel, P being a non-zero integer, at the frequency Fe / P. Any possible time lag of the demultiplexers, for example during start-up, In this case, synchronization methods are known in the state of the art based on the use of particular architectures allowing a distribution of synchronization signals, the objective of which is to synchronize the demultiplexers. Series or star synchronization signal distribution architectures have been proposed. Such solutions are complex, and the synchronization obtained depends on the clock synchronization. The Fe sampling frequency being very high, the corresponding period is very low, and the propagation times and their drift are not negligible compared to this period. The synchronization systems thus obtained can therefore become unstable. In another case, the reception chains do not respect the Shannon condition, performing an instantaneous very wide band filtering, and the analog-to-digital converters use different Fe sampling frequencies to solve the problem of aliasing. due to not respecting Shannon's condition. Synchronization between reception channels based on synchronization signals is not possible in this case. After estimating the time offset values ​​between channels, for example a time offset value between each channel and a reference channel, in one or other of the cases mentioned above, it is necessary to 'carry out effective synchronization of the samples from the different channels and corresponding to the same time slot. The object of the invention is to propose a system for synchronization between reception channels, operating in particular for sampling frequencies different from the analog-to-digital converters of the multi-channel reception system. To this end, the invention proposes a synchronization device suitable for being inserted into a reception channel of a multi-channel reception system for radio signals between an interface module and a digital signal processing module, the module of interfacing being adapted to receive digitized signal samples coming from an analog-to-digital converter having its own sampling frequency and to supply packets of P digitized signal samples at a first frequency. This device includes: a memory accessible in writing and in reading by independent accesses, in which input packets of P samples of the digitized signal supplied by the interface module are stored, a first set of registers fed as input by first packets of P samples read from said memory, at a second frequency, each packet of P samples being read at a read address, and a second set of registers fed as input by the outputs of the first set of registers and adapted to deliver second packets of P samples at the rate of the second frequency, a second packet of P samples corresponding to the samples of the first packet of P samples with a delay of one period of the second frequency. Advantageously, the device of the invention makes it possible to synchronize samples originating from channels operating at different sampling frequencies, while compensating for time shifts between these channels. The synchronization device according to the invention can also have one or more of the characteristics below, taken independently or in combination. The synchronization device is such that the outputs of the first and second sets of registers are connected to the input of a multiplexer so as to provide double packets of 2 P samples, the multiplexer being adapted to form a third packet of P consecutive samples among the 2 P input samples of the multiplexer from a multiplexing address, the synchronization device further comprising a PLC adapted to calculate said read in memory and multiplexing addresses as a function of a counter and an offset temporal with respect to a reference reception channel,the synchronization device providing as output pluralities of third packets of P samples forming successive series each comprising a number of samples in series corresponding to the same duration, and each first sample of a said series of said temporally corresponding reception channel to the first sample of a corresponding series of the reference reception channel. The automaton has an associated period, calculated as a function of said duration, said counter being incremented in a synchronous manner between reception channels at each automaton period. The automaton is suitable for calculating said multiplexing address for a current counter value as a function of said time offset, said number of samples in series and the number P of samples per packet. The controller further calculates a read address hold indicator for a current counter value, as a function of a comparison between a multiplexing address calculated for said current counter value, and a multiplexing address calculated for a value. previous counter. The automaton is adapted to calculate said read address for the current counter value as a function of said number of samples in series, said hold indicator for the current counter value and a read address calculated for the counter value former. According to another aspect, the invention relates to a system for synchronization between reception channels of a multi-channel reception system, the reception system comprising a set of radio signal reception channels, each reception channel comprising a reception channel delivering an analog electrical signal at the input of an analog-to-digital converter) having an associated sampling frequency, an interfacing module connected to the output of said analog-to-digital converter and a digital signal processing module comprising one or more programmable digital components, the interface module being suitable for supplying digitized signal samples at the input of said digital signal processing module in packet parallel.This system is such that each reception channel includes a synchronization device as briefly described above. According to one characteristic, the system further comprises a counting module adapted to supply in a synchronized manner a counter value to each synchronization device of each reception channel. According to another aspect, the invention relates to a method of synchronization between reception channels of a multichannel reception system for radio signals implemented in a synchronization device suitable for being inserted into a reception channel of a multichannel reception system. of radioelectric signals between an interfacing module and a digital signal processing module, the interfacing module being adapted to receive digitized signal samples from an analog-to-digital converter having a specific sampling frequency and to provide packets of P signal samples digitized at a first frequency. This process includes: - storage in a memory accessible in writing and in reading by independent accesses, in which input packets of P samples of the digitized signal supplied by an interfacing module at a first frequency are stored, obtaining first packets of P samples in a first set of registers fed at input by first packets of P samples read in said memory, at a second frequency, each first packet of P samples being read at a read address, and obtaining second packets of P samples in a second set of registers fed as input by the outputs of the first set of registers and adapted to deliver second packets of P samples at the rate of the second frequency, a second packet of P samples corresponding to the samples of the first packet of P samples with a delay of one period of the second frequency. According to one characteristic, the synchronization method further comprises steps of: - reception and storage of a time offset to be applied, - obtaining a current counter value, and calculating a current read address and a current multiplexing address as a function of the current counter value and the time offset to be applied, obtaining a said first packet of samples from a first set of registers and a said second packet of samples from a second set of registers by applying the current read address, extracting a third packet of P consecutive samples from a double packet of 2 P samples formed by the first and second packets, using said multiplexing address. Other characteristics and advantages of the invention will emerge from the description which is given below, by way of indication and in no way limiting, with reference to the appended figures, among which: FIG. 1 schematically illustrates a system for synchronization between reception channels of a multi-channel reception system according to one embodiment; FIG. 2 illustrates in detail an embodiment of a synchronization device for a reception channel; FIG. 3 schematically represents packets of samples originating from an interfacing device of a reception channel; FIGS. 4 and 5 diagrammatically represent an example of sample packets originating from two reception channels, before and after application of the synchronization; FIG. 6 schematically illustrates first and second packets of samples used to obtain a series of samples according to one embodiment; FIGS. 7 and 8 illustrate, in one example, sample packets originating from the first and second sets of registers of the synchronization device, and from the synchronized series obtained; FIG. 9 is a block diagram of the main steps of a synchronization method according to one embodiment. FIG. 1 illustrates a multi-channel reception system 1 implementing a synchronization system 2 between the channels. The multi-channel radio signal reception system 1 comprises N reception channels \ to V N , any one of the reception channels being referred to below as V, with i ranging between 1 and N. Each reception channel comprises an analog reception chain not shown in FIG. 1, an analog-to-digital converter or ADC 8 ,, an interface module 10 ,, a synchronization device 26, and a digital signal processing module 12, associated with the reception channel, forming part of a digital processing module 12. The module 12 is also suitable for performing digital calculations on the elements originating from the various digital signal processing modules 12 ,, for example calculations of correlation. The ADC 8 supplies digital samples of the signal S j (t) delivered by the analog reception chain to the interface module 10, at the rate of the sampling frequency Fe ; of said CAN. The digital samples of the signal are hereinafter referred to simply as samples. In the embodiment described here, all the sampling frequencies Fe; are different. The sampling frequency Fe j is much greater than the maximum operating frequency of the programmable digital components (FPGA) located downstream of the ADCs, in particular in the digital signal processing module 12. The interfacing module 10 therefore has the function of transforming the flow of series samples at the rate Fe into a series flow of packets of P samples in parallel at the first frequency - -, P being a non-zero integer, this first frequency being slower and compatible with the second frequency or frequency working programmable digital components F T . SJt) denotes the digital signal delivered by the interface module 10 ,, resulting from a corresponding analog signal S j (t). The interfacing module 10 is, in one embodiment, a demultiplexer with one or more demultiplexing stages, providing packets of P samples in parallel. The demultiplexers 10, of the different reception channels are not synchronized, and cannot be synchronized because the Fe frequencies are different, and therefore the - - values ​​are also different. Each reception channel of the system comprises a synchronization device 26, connected between the interface module 10, and the digital processing module 12 ,. This synchronization device 26 has the function, from a serial input stream of packets of P successive samples passed in parallel, the samples being obtained at a sampling frequency Fe and having undergone a possible time shift related to to channel i, to form series of N t successive samples, always formatted in packets of P successive samples in parallel, of which the first sample of said series corresponds, whatever may be i, to the same absolute time, that is to say tell the current time in the input stream corrected for said possible time offset. Each synchronization device 26, receives as input a time offset value At tC between the channel V, and the reference channel V r , calculated moreover by a suitable method, so as to provide series of samples temporally adjusted between channels to modules 12 ,. The module 100 is in the preferred embodiment a counting module common to all the synchronization devices 26, which distributes the same counter value at a given instant to each synchronization device. As a variant, the counting module 100 is suitable for synchronizing the counters of the synchronization devices 26 ,, for example by an initial reset, so that each of the counters delivers the same counter value to each control device. synchronization 26 ,. Each digital processing module 12 can, for example, perform a discrete Fourier transform (DFT) on the Ni successive samples of a series, corresponding to a signal duration AT which is the same for all the reception channels. So, whatever i: In particular for interferometric applications, it is necessary that the series of Ni successive samples for different values ​​of i, all correspond to the same absolute time interval so that the phase shift between end of channels, between two given channels, is representative of that at the output of the antennas of said two channels on the same incident signal. FIG. 2 illustrates in detail a synchronization device 26, forming part of the reception channel V i. The synchronization device 26, receives as input packet P samples the first frequency - -, and provides outputs of the sets of N ty samples, packet P samples. FIG. 3 illustrates a first problem to be solved owing to the fact that the number N t is not, generally, a multiple of P. FIG. 3 illustrates the parallelization of the flow of samples in P parallel lines, carried out by the demultiplexer 10 ,. Each sample is symbolized by a box 140. These samples are illustrated in a diagram with two time axes and T 2 . The packets 150 of P samples are referenced by an index Ç j . The duration corresponding to a packet is PTe t = ^ · The curved arrows 160 indicate the continuity of the samples over time. The series 18 to be outputted are series of Ni samples, referenced by an index /, shown in thick lines. However, the number N t not being a multiple of P, each series 18 does not systematically start with a packet of P samples belonging to it entirely, as illustrated in FIG. 3 by the sample of index 0 of each packet. The position of the first sample of a series 18 in a packet of P samples 150 changes over time, and depends on the remainder P j of the Euclidean division of N t by P. The number Ni is written in the form: N t = M x P + Ri (EQ 2) with 0