Claims:1. A system (100) for training and verification of an integrated circuit layout comprising:
a layout retrieval subsystem (110) configured to retrieve one or more design layouts of an integrated circuit from one or more sources using one or more types of query;
a verification subsystem (120) operatively coupled to the layout retrieval subsystem (110) and configured to verify one or more retrieved design layouts with a plurality of techniques and one or more rule database; and
a report generation subsystem (130) operatively coupled to the verification subsystem (120) and configured to generate an error report for resolving at least one error encountered in the one or more design layouts; and
a learning subsystem (140) operatively coupled to the report generation subsystem (130) and layout database (112) and configured to visualise one or more learning contents in one or more formats corresponding to a generated error report.
2. The system (100) as claimed in claim 1, wherein the one or more sources comprises a user or a layout database.
3. The system (100) as claimed in claim 1, wherein the plurality of techniques comprises a design rule check (DRC) technique, a layout versus schematic (LVS) technique, an electrical rule check (ERC) technique, a design for manufacturability (DFM) technique and a reliability check technique such as antenna rule violations.
4. The system (100) as claimed in claim 1, wherein the learning subsystem (140) comprises a brief mode of learning, a detail mode of learning and a practice mode of learning.
5. The system (100) as claimed in claim 1, wherein the one or more formats of the visualisation comprises at least one of a textual format, a graphical format or an audio-visual format.
6. The system (100) as claimed in claim 1, wherein the learning subsystem is also configured to update an undefined learning content and the layout database when the one or more learning contents corresponding to the generated error report is undetermined.
7. The system (100) as claimed in claim 1, further comprising an error database operatively coupled to the verification subsystem (130), the layout database (112) and the report generation subsystem (130) configured to store the at least one error encountered in the one or more design layouts in the layout database.
8. The system (100) as claimed in claim 7, wherein the error database is also configured to update the at least one error encountered with a plurality of design layouts to provide a historical data for resolving one or more future errors by using a learning technique.
9. A method (200) for training and verification of an integrated circuit layout comprising:
retrieving, by a layout retrieval subsystem, one or more design layouts of an integrated circuit from one or more sources using one or more types of query (210);
verifying, by a verification subsystem, one or more retrieved design layouts by using a plurality of techniques (220);
generating, by a report generation subsystem, an error report for resolving at least one error encountered in the one or more design layouts (230); and
visualising, by a learning subsystem, one or more learning contents in one or more formats corresponding to a generated error report (240).
10. The method (200) as claimed in claim 9, further comprising of storing at least one error encountered in the one or more design layouts in a database.
11. The method (200) as claimed in claim 10, further comprising updating the at least one error encountered with a plurality of design layouts to provide a historical data for resolving one or more future errors by using a learning technique.
, Description:BACKGROUND
[1] Embodiments of a present disclosure relates to a system for verification and more particularly to a system and method for training and verification of an integrated circuit layout.
[2] Integrated circuit (IC) designing is a combination of both an art and technology. The IC layout which is designed is becoming complex as sizes of transistors and circuit traces continue to decrease, thereby allowing fabrication of greater numbers of the transistors and one or more logic elements in a smaller chip. A layout engineer in order to create an optimised IC layout needs to understand and build expertise in a plurality of design concepts such as very large-scale integration (VLSI) design and fabrication process, design rules, best practices and hands-on skills in computer aided design (CAD) tools. The optimised IC layout and the optimised one or more cell libraries which are handcrafted are integrated by using a plurality of automated approaches. Various systems are available in order to check or verify the layout design of the integrated circuits.
[3] Conventionally, the system available for verification of the layout involves physical verification of the IC layout by one or more engineers or via an electronic design automation tool. However, such systems become incapable when a plurality of cells are being designed. In such a case, process of designing is time consuming and also development time depends heavily on experience level of individual involved. Moreover, additional training by several hours of hands on practice sessions or learning is involved with complex cells, development of cells in a new process technology and also when new design rules or constraints are introduced.
[4] Hence, there is need for an improved system and a method for training and verification of an integrated circuit layout which may be used for training new team members, to run skilling sessions and to build expertise of existing team members and to systematically improve the knowledge and reduce trial and error approaches in order to address the aforementioned issues.
BRIEF DESCRIPTION
[5] In accordance with an embodiment of the present disclosure, system for training and verification of an integrated circuit layout is disclosed. The system includes a layout retrieval subsystem configured to retrieve one or more design layouts of an integrated circuit from one or more sources using one or more types of query. The system also includes a verification subsystem operatively coupled to the layout retrieval subsystem. The verification subsystem is configured to verify one or more retrieved design layouts with a plurality of techniques and one or more rule database. The system also includes a report generation subsystem operatively coupled to the verification subsystem. The report generation subsystem is configured to generate an error report for resolving at least one error encountered in the one or more design layouts. The system also includes a learning subsystem operatively coupled to the report generation subsystem. The learning subsystem is configured to visualise one or more learning contents in one or more formats corresponding to a generated error report.
[6] In accordance with another embodiment of the present disclosure, a method for training and verification of an integrated circuit layout is disclosed. The method includes retrieving, by a layout retrieval subsystem, one or more design layouts of an integrated circuit from one or more sources, using one or more query. The method also includes verifying, by a verification subsystem, one or more retrieved design layouts by using a plurality of techniques.
The method also includes generating, by a report generation subsystem, an error report for resolving at least one error encountered in the one or more design layouts. The method also includes visualising, by a learning subsystem, one or more learning contents in one or more formats corresponding to a generated error report.
[7] To further clarify the advantages and features of the present disclosure, a more particular description of the disclosure will follow by reference to specific embodiments thereof, which are illustrated in the appended figures. It is to be appreciated that these figures depict only typical embodiments of the disclosure and are therefore not to be considered limiting in scope. The disclosure will be described and explained with additional specificity and detail with the appended figures.
BRIEF DESCRIPTION OF THE DRAWINGS
The disclosure will be described and explained with additional specificity and detail with the accompanying figures in which:
[8] FIG. 1 is a block diagram of a system for training and verification of an integrated circuit layout in accordance with an embodiment of the present disclosure;
[9] FIG. 2 illustrates a schematic representation of an exemplary embodiment of a system for training and verification of an integrated circuit layout of FIG. 1 in accordance with an embodiment of the present disclosure;
[10] FIG. 3 is a flow chart representing the steps involved in a method for training and verification of an integrated circuit layout in accordance with the embodiment of the present disclosure.
[11] Further, those skilled in the art will appreciate that elements in the figures are illustrated for simplicity and may not have necessarily been drawn to scale. Furthermore, in terms of the construction of the device, one or more components of the device may have been represented in the figures by conventional symbols, and the figures may show only those specific details that are pertinent to understanding the embodiments of the present disclosure so as not to obscure the figures with details that will be readily apparent to those skilled in the art having the benefit of the description herein.
DETAILED DESCRIPTION
[12] For the purpose of promoting an understanding of the principles of the disclosure, reference will now be made to the embodiment illustrated in the figures and specific language will be used to describe them. It will nevertheless be understood that no limitation of the scope of the disclosure is thereby intended. Such alterations and further modifications in the illustrated system, and such further applications of the principles of the disclosure as would normally occur to those skilled in the art are to be construed as being within the scope of the present disclosure.
[13] The terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process or method that comprises a list of steps does not include only those steps but may include other steps not expressly listed or inherent to such a process or method. Similarly, one or more devices or sub-systems or elements or structures or components preceded by "comprises... a" does not, without more constraints, preclude the existence of other devices, sub-systems, elements, structures, components, additional devices, additional sub-systems, additional elements, additional structures or additional components. Appearances of the phrase "in an embodiment", "in another embodiment" and similar language throughout this specification may, but not necessarily do, all refer to the same embodiment.
[14] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. The system, methods, and examples provided herein are only illustrative and not intended to be limiting.
[15] In the following specification and the claims, reference will be made to a number of terms, which shall be defined to have the following meanings. The singular forms “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise.
[16] Embodiments of the present disclosure relate to a system for training and verification of an integrated circuit layout is disclosed. The system includes a layout retrieval subsystem configured to retrieve one or more design layouts of an integrated circuit from one or more sources. The system also includes a verification subsystem operatively coupled to the layout retrieval subsystem. The verification subsystem is configured to verify one or more retrieved design layouts with a plurality of techniques and one or more rule database. The system also includes a report generation subsystem operatively coupled to the verification subsystem. The report generation subsystem is configured to generate an error report for resolving at least one error encountered in the one or more design layouts. The system also includes a learning subsystem operatively coupled to the report generation subsystem. The learning subsystem is configured to visualise one or more learning contents in one or more formats corresponding to a generated error report.
[17] FIG. 1 is a block diagram of a system (100) for training and verification of an integrated circuit layout in accordance with an embodiment of the present disclosure. The system (100) includes a layout retrieval subsystem (110) configured to retrieve one or more design layouts of an integrated circuit from one or more sources using one or more types of query. In one embodiment, the one or more sources may include a user or a layout database. In some embodiment, the user may provide a new dataset for implementation. In another embodiment, the layout database may include a plurality of practice layouts with varying complexity. In such embodiment, the plurality of practice layouts may include partially completed layouts, layouts with one or more errors or layouts with rule violations.
[18] The system (100) also includes a verification subsystem (120) operatively coupled to the layout retrieval subsystem (110). The verification subsystem (120) is configured to verify one or more retrieved design layouts with a plurality of techniques and one or more rule database. In one embodiment, the plurality of techniques may include a design rule check (DRC) technique, a layout versus schematic (LVS) technique, an electrical rule check (ERC) technique, a design for manufacturability (DFM) technique and a reliability check technique such as antenna rule violations.
[19] The system (100) also includes a report generation subsystem (130) operatively coupled to the verification subsystem (120). The report generation subsystem (130) is configured to generate an error report for resolving at least one error encountered in the one or more design layouts. In one embodiment, the error report may include information about the at least one error encountered, type of the at least one error encountered and complexity of the at least one error encountered.
[20] The system (100) also includes a learning subsystem (140) operatively coupled to the report generation subsystem (130). The learning subsystem (140) is configured to visualise one or more learning contents in one or more formats corresponding to a generated error report. In one embodiment, the learning subsystem (140) may include a brief mode of learning for visualising the one or more learning contents. In such embodiment, the brief mode of the learning may include a brief text-based explanation of at least one error encountered and tip or recommendations for resolving the same. In another embodiment, the learning subsystem (140) may also include a detail mode of learning for visualising the one or more learning contents. In such embodiment, the detail mode may include information and concepts in details for the at least one error encountered. In yet another embodiment, the learning subsystem may also include a practice mode of learning for visualising the one or more learning contents. In some embodiment, the practice mode may provide an opportunity to a learner about a single rule or a concept by practicing and running a test case specific to the at least one error encountered.
[21] In one embodiment, the one or more formats of the visualisation of the one or more learning contents may include at least one of a textual format, a graphical format or an audio-visual format. In some embodiment, the learning subsystem (140) is also configured to update an undefined learning content and the layout database when the one or more learning contents corresponding to the generated error report is undetermined. In such embodiment, the undefined learning content may be a new learning content which needs to be updated for resolving the at least one error encountered corresponding to the generated error report.
[22] In a specific embodiment, the system (100) further includes an error database operatively coupled to the verification subsystem (120) and the layout database (112). The error database is configured to store the at least one error encountered in the one or more design layouts. In such embodiment, the error database is also configured to update the at least one error encountered with a plurality of design layouts to provide a historical data for receiving one or more future errors by using a learning technique. In some embodiment, the learning technique may include an artificial intelligence technique. In such embodiment, the artificial intelligence technique may include a prediction technique.
[23] FIG. 2 illustrates a schematic representation of an exemplary embodiment of a system (100) for training and verification of an integrated circuit layout of FIG. 1 in accordance with an embodiment of the present disclosure. Manually verifying the integrated circuit layout is time consuming as well as prone to one or more errors. In order to efficiently verify the integrated circuit layout by reducing trial and error approaches, the system (100) to automatically train and verify the integrated circuit layout is developed. The system (100) is developed to design and verify the integrated circuit layout of a universal serial bus (USB) circuit. The system (100) includes a layout retrieval subsystem (110) configured to retrieve one or more design layouts of an integrated circuit from one or more sources using one or more types of query. For example, the one or more sources may be a layout database (112) or a user (115). Here, a design layout is retrieved from the layout database (112), wherein retrieved design layout is a practice layout with one or more errors and partially completed.
[24] The system (100) also includes a verification subsystem (120) operatively coupled to the layout retrieval subsystem (110). The verification subsystem (120) is configured to verify one or more retrieved design layouts with a plurality of techniques and one or more rules from a rule database (117). Here, the verification subsystem (120) for verifying the retrieved design layouts utilises a plurality of techniques such as a design rule check technique (DRC) to determine whether retrieved design layout satisfies a series of recommended parameters called design rules. Also, a layout versus schematic (LVS) technique is used to determine whether the retrieved design layout corresponds to an original schematic or a circuit diagram of the design. Similarly, an electrical rule check (ERC) technique is used to involve checking of a design for proper contacts and spacing thereby ensuring correct power and ground connections. Also, a design for manufacturability (DFM) technique is used to design products of the integrated circuit layout in such a way which is easy to manufacture. Moreover, a reliability check technique such as antenna rule violations.
[25] The system (100) also includes a report generation subsystem (130) operatively coupled to the verification subsystem (120). The report generation subsystem (130) is configured to generate an error report for resolving at least one error encountered in the one or more design layouts. Here, the error report is generated in order to provide information to the user (115) about the at least one error encountered, type of the at least one error encountered and complexity of the at least one error encountered. For example, the type of the at least one error encountered may include but not limited to a metal-to-metal spacing violation, or a poly-overhang-of moat violation.
[26] The system (100) also includes a learning subsystem (140) operatively coupled to the report generation subsystem (130). The learning subsystem (140) is configured to visualise one or more learning contents in one or more formats corresponding to a generated error report.
For example, the one or more formats corresponding to the generated error report may include a detail mode (145) for visualising the one or more learning contents. Here, the detail mode (145) includes related information and related concepts in details for the at least one error encountered. For example, the detailed information stored in a content database may be detailed documentation or a video lecture explaining about the at least one error encountered in detail. The video-lecture by a domain expert helps the user (115) to understand to analyse the at least one error encountered, reason for the at least the one error to occur and what measures may be taken in order to resolve the error. Also, the user (115) may get some idea or knowledge related to the error which may be helpful for future perspective, if same type of the error occurs in other designs.
[27] In a specific embodiment, the system (100) further includes an error database (150) operatively coupled to the layout database (112), the verification subsystem (120) and the report generation subsystem (130). Here, the error database (150) is configured to store the at least one error encountered in the one or more design layouts in the error database (150). The error report which shows the at least one error is further stored in the error database (150) for future reference. For example, while designing the IC layout for universal serial bus (USB) circuits, if the at least one error occurred, and similarly, such same type of the error is also encountered while designing the IC layout for another circuit, then the error database (150) helps in providing reference.
[28] Moreover, the error database (150) is also configured to update the at least one error encountered automatically with a plurality of design layouts to provide a historical data for resolving one or more future errors by using a learning technique. The errors may be stored with user information or design information for easy retrival in future. Here, the learning technique may be an artificial intelligence technique. For example, artificial intelligence technique may include a machine learning technique to automatically learn from past experiences of errors which are encountered.
[29] FIG. 3 is a flow chart representing the steps involved in a method (200) for training and verification of an integrated circuit layout in accordance with the embodiment of the present disclosure. The method (200) includes retrieving, by a layout retrieval subsystem, one or more design layouts of an integrated circuit from one or more sources using one or more types of query in step 210. In one embodiment, retrieving the one or more design layouts of the integrated circuit includes retrieving the one or more design layouts from the one or more sources such as a user or a layout database. In some embodiment, retrieving the one or more design layouts of the integrated circuit from the user may include retrieving a new dataset from scratch for implementation. In another embodiment, retrieving the one or more design layouts of the integrated circuit from the layout database may include retrieving a plurality of practice layouts with varying complexity, partial level of completion or one or more errors.
[30] The method (200) also includes verifying, by a verification subsystem, one or more retrieved design layouts by using a plurality of techniques in step 220. In one embodiment, verifying the one or more retrieved design layouts may include verifying the one or more retrieved design layouts by using the plurality of techniques, wherein the plurality of techniques includes a design rule check (DRC) technique, a layout versus schematic (LVS) technique, an electrical rule check (ERC) technique, a design for manufacturability (DFM) technique and a reliability check technique such as antenna rule violations.
[31] The method (200) also includes generating, by a report generation subsystem, an error report for resolving at least one error encountered in the one or more design layouts in step 230. In one embodiment, generating the error report for resolving the at least error encountered may include generating the error report for identifying the information about the at least one error encountered, type of the at least one error encountered and complexity of the at least error encountered.
[32] The method (200) also includes visualising, by a learning subsystem, one or more learning contents in one or more formats corresponding to a generated error report in step 240. In one embodiment, visualising the one or more learning contents in one or more formats may include visualising the one or more learning contents in the one or more formats such as a brief mode of learning, a detail mode of learning and a practice mode of learning. In some embodiment, visualising the one or more learning contents in the brief mode of learning may include visualising a brief text-based explanation of at least one error encountered and tip or recommendations for resolving the same. In another embodiment, visualising the one or more learning contents in the detail mode of learning may include visualising related information and related concepts in details for the at least one error encountered. In yet another embodiment, visualising the one or more learning contents in the practice mode of learning may include visualising a single rule or a concept and running a test case specific to the at least one error encountered, which is practiced by a learner.
[33] In a specific embodiment, the method (200) further includes storing the at least one error encountered in the one or more design layouts in a database. In such embodiment, storing the at least one error encountered may include storing the at least one error encountered after verification or after fixing.
[34] In some embodiment, the method (200) further includes updating the at least one error encountered with a plurality of design layouts to provide a historical data for resolving one or more future errors by using a learning technique. In such embodiment, updating the at least one error encountered with the plurality of design layouts may include updating the at least one error for providing a historical data for resolving one or more future errors by using an artificial intelligence technique.
[35] Various embodiments of the present disclosure provide an automatic training and verification of the integrated circuit layout which is simple and user-friendly.
[36] Moreover, the present disclosed system reduces manual effort by reducing additional training of several hours or hands on practice sessions of the user and makes the system faster.
[37] Furthermore, the present disclosed system improves the knowledge and reduces trial and error approaches and as a result improves accuracy.
[38] It will be understood by those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the disclosure and are not intended to be restrictive thereof.
[39] While specific language has been used to describe the disclosure, any limitations arising on account of the same are not intended. As would be apparent to a person skilled in the art, various working modifications may be made to the method in order to implement the inventive concept as taught herein.
[40] The figures and the foregoing description give examples of embodiments. Those skilled in the art will appreciate that one or more of the described elements may well be combined into a single functional element. Alternatively, certain elements may be split into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, the order of processes described herein may be changed and are not limited to the manner described herein. Moreover, the actions of any flow diagram need not be implemented in the order shown; nor do all of the acts need to be necessarily performed. Also, those acts that are not dependent on other acts may be performed in parallel with the other acts. The scope of embodiments is by no means limited by these specific examples.