Claims:1. An input sensing circuit for digital input sensing, said circuit comprising:
a first opto-isolator (ISO1) configured to sense input signal;
a constant current circuit configured to generate a constant current; and
a digital sampling circuit comprising a second opto-isolator (ISO2), wherein the constant current circuit enables constant current through LED of the first opto-isolator (ISO1) by providing driving current for the first opto-isolator (ISO1) in a wider input sensing range, and wherein power dissipation in the constant current circuit is compensated by the digital sampling circuit.

2. The input sensing circuit of claim 1, wherein the constant current circuit comprises a MOSFET M1, a BJT Q1, and a resistor R2.

3. The input sensing circuit of claim 1, wherein the digital sampling circuit further comprises a resistor R2, a resistor R5, and a BJT Q2.

4. The input sensing circuit of claim 1, wherein the second opto-isolator (ISO2) receives a pulse from a FPGA/microcontroller through a control signal in order to obtain the state of the input signal.

5. The input sensing circuit of claim 2, wherein the control signal is given for a defined time in order to maintain low duty cycle.

6. A method for configuring an input sensing circuit for digital input sensing, said method comprising the steps of:
configuring a first opto-isolator (ISO1) to sense input signal;
configuring a constant current circuit generate a constant current; and
configuring a digital sampling circuit comprising a second opto-isolator (ISO2),
wherein the constant current circuit enables constant current through LED of the first opto-isolator (ISO1) by providing driving current for the first opto-isolator (ISO1) in a wider input sensing range, and wherein power dissipation in the constant current circuit is compensated by the digital sampling circuit.

7. The method of claim 6, wherein the constant current circuit comprises a MOSFET M1, a BJT Q1, and a resistor R2.

8. The method of claim 6, wherein the digital sampling circuit further comprises a resistor R2, a resistor R5, and a BJT Q2.

9. The method of claim 6, wherein the second opto-isolator (ISO2) receives a pulse from a FPGA/microcontroller through a control signal in order to obtain the state of the input signal.

10. The method of claim 9, wherein the control signal is given for a defined time in order to maintain low duty cycle.
, Description:TECHNICAL FIELD
[0001] The present disclosure relates generally to the field of voltage sensing. In particular, the present disclosure pertains to a system and method for universal isolated digital input sensing.
BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Input signal sensing is one of the primary requirements for any electronics equipment in automation application for controlling and monitoring industrial processes. In a typical application, input signal range or type is always mentioned. Any input signal that is not within the input range can cause the electronic circuit to misbehave or cause damage to it. Most of the existing industrial applications have a bounded input range, for example, 24V DC, 230V AC. Existing linear voltage drop circuits have high power dissipation and use a complex design such as switch mode kind of configuration.
[0004] There is therefore a need for a novel and improved input sensing method that overcomes the above-mentioned and other disadvantages of existing techniques.
[0005] All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
[0006] In some embodiments, the numbers expressing quantities of ingredients, properties such as concentration, reaction conditions, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term “about”. Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
[0007] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0008] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0009] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all Markush groups used in the appended claims.

OBJECTS OF THE INVENTION
[0010] An object of the present disclosure is to provide a system and method for improved digital input sensing.
[0011] An object of the present disclosure is to provide a single digital input circuit that processes all mentioned input signal ranges to minimize inventory to reduce cost.
[0012] An object of the present disclosure is to provide a single digital input circuit that works in linear mode to avoid issues pertaining to Electromagnetic compatibility (EMC) or electromagnetic interference (EMI).
[0013] An object of the present disclosure is to provide a single digital input circuit that enables lower power dissipation when compared to linear voltage drop circuit.
[0014] An object of the present disclosure is to provide a single digital input circuit that uses a less complex design when compared with switch mode kind of configuration.
[0015] An object of the present disclosure is to provide a single digital input circuit that has a wide voltage input range by using constant current source.
[0016] An object of the present disclosure is to provide a single digital input circuit that has a current limit function that protects MOSFET overload.
[0017] An object of the present disclosure is to provide a single digital input circuit that configures Galvanic isolation between input and FPGA/microcontroller.
[0018] An object of the present disclosure is to provide a single digital input circuit that provides isolation of common mode and differential mode noise.

SUMMARY
[0019] The present disclosure relates generally to the field of voltage sensing. In particular, the present disclosure pertains to a system and method for universal isolated digital input sensing.
[0020] In an aspect, the present disclosure relates to an input sensing circuit for digital input sensing, said circuit comprising a first opto-isolator (ISO1) configured to sense input signal; a constant current circuit configured to generate a constant current; anda digital sampling circuit comprising a second opto-isolator (ISO2), wherein the constant current circuit enables constant current through LED of the first opto-isolator (ISO1) by providing driving current for the first opto-isolator (ISO1) in a wider input sensing range, and wherein power dissipation in the constant current circuit is compensated by the digital sampling circuit.
[0021] In an aspect, the constant current circuit can include a MOSFET M1, a BJT Q1, and a resistor R2. In another aspect, the digital sampling circuit can include a resistor R2, a resistor R5, and a BJT Q2.
[0022] In another aspect, the second opto-isolator (ISO2) can be configured to receive a pulse from a FPGA/microcontroller through a control signal in order to obtain the state of the input signal. In an aspect, the control signal can be given for a defined time in order to maintain low duty cycle.
[0023] The present disclosure further relates to a method for configuring an input sensing circuit for digital input sensing, said method comprising the steps of configuring a first opto-isolator (ISO1) to sense input signal; configuring a constant current circuit generate a constant current; and configuring a digital sampling circuit comprising a second opto-isolator (ISO2), wherein the constant current circuit enables constant current through LED of the first opto-isolator (ISO1) by providing driving current for the first opto-isolator (ISO1) in a wider input sensing range, and wherein power dissipation in the constant current circuit is compensated by the digital sampling circuit.
[0024] In an aspect, the proposed system and architecture uses a combination of linear and switch mode techniques to achieve a wide range of input voltage, wherein the system includes a constant current circuit that can generate a constant current and help achieve a wide input sensing range to drive an opto-isolator, and wherein the opto-isolator can provide galvanic isolation between the field-programmable gate array (FPGA)/microcontroller and the input signal. Furthermore, the opto-isolator can sense the input signal by transferring electrical signals between the two isolated circuits using light from a light emitting diode (LED), which can be proportional to the input constant current.
[0025] In an aspect, the metal oxide semiconductor field effect transistor (MOSFET) that can be responsible for generating a constant current can also be responsible for producing high power dissipation. This high power dissipation can be compensated by the digital sampling circuit implemented within the FPGM/ microprocessor, which can give signal to the opto-isolator through a control signal. The digital sampling circuit can be configured to give signal for a fraction of time to maintain a low duty cycle that can limit the power dissipation by the MOSFET of the constant current circuit.
[0026] In an aspect, since a linear circuit is used, there is no electromagnetic interference (EMI) or electromagnetic compatibility (EMC) issue encountered. The circuit design is less complex compared to switch mode configurations. The constant current source helps achieve wide voltage input range. The current limit function protects MOSFET overload and reduces the power dissipation, which is less compared to linear voltage drop circuits. Galvanic isolation is achieved between the FPGA/ microcontroller and the input signal. Further, isolation of common mode and differential mode noise is achieved.
[0027] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0029] FIG. 1 illustrates an exemplary representation of the proposed input sensing circuit in accordance with an embodiment of the present disclosure.
[0030] FIG. 2 illustrates an exemplary flow diagram of operation of the proposed input sensing circuit in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0031] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0032] Each of the appended claims defines a separate invention, which for infringement purposes is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, all references below to the "invention" may in some cases refer to certain specific embodiments only. In other cases it will be recognized that references to the "invention" will refer to subject matter recited in one or more, but not necessarily all, of the claims.
[0033] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0034] All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0035] Various terms as used herein. To the extent a term used in a claim is not defined, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
[0036] The present disclosure relates generally to the field of voltage sensing. In particular, the present disclosure pertains to a system and method for universal isolated digital input sensing.
[0037] In an aspect, the present disclosure relates to an input sensing circuit for digital input sensing, said circuit comprising a first opto-isolator (ISO1) configured to sense input signal; a constant current circuit configured to generate a constant current; and a digital sampling circuit comprising a second opto-isolator (ISO2), wherein the constant current circuit enables constant current through LED of the first opto-isolator (ISO1) by providing driving current for the first opto-isolator (ISO1) in a wider input sensing range, and wherein power dissipation in the constant current circuit is compensated by the digital sampling circuit.
[0038] In an aspect, the constant current circuit can include a MOSFET M1, a BJT Q1, and a resistor R2. In another aspect, the digital sampling circuit can include a resistor R2, a resistor R5, and a BJT Q2.
[0039] In another aspect, the second opto-isolator (ISO2) can be configured to receive a pulse from a FPGA/microcontroller through a control signal in order to obtain the state of the input signal. In an aspect, the control signal can be given for a defined time in order to maintain low duty cycle.
[0040] The present disclosure further relates to a method for configuring an input sensing circuit for digital input sensing, said method comprising the steps of configuring a first opto-isolator (ISO1) to sense input signal; configuring a constant current circuit generate a constant current; and configuring a digital sampling circuit comprising a second opto-isolator (ISO2), wherein the constant current circuit enables constant current through LED of the first opto-isolator (ISO1) by providing driving current for the first opto-isolator (ISO1) in a wider input sensing range, and wherein power dissipation in the constant current circuit is compensated by the digital sampling circuit.
[0041] In an aspect, the proposed system and architecture uses a combination of linear and switch mode techniques to achieve a wide range of input voltage, wherein the system includes a constant current circuit that can generate a constant current and help achieve a wide input sensing range to drive an opto-isolator, and wherein the opto-isolator can provide galvanic isolation between the field-programmable gate array (FPGA)/microcontroller and the input signal. Furthermore, the opto-isolator can sense the input signal by transferring electrical signals between the two isolated circuits using light from a light emitting diode (LED), which can be proportional to the input constant current.
[0042] In an aspect, the metal oxide semiconductor field effect transistor (MOSFET) that can be responsible for generating a constant current can also be responsible for producing high power dissipation. This high power dissipation can be compensated by the digital sampling circuit implemented within the FPGM/microprocessor, which can give signal to the opto-isolator through a control signal. The digital sampling circuit can be configured to give signal for a fraction of time to maintain a low duty cycle that can limit the power dissipation by the MOSFET of the constant current circuit.
[0043] In an aspect, since a linear circuit is used, there is no electromagnetic interference (EMI) or electromagnetic compatibility (EMC) issue encountered. The circuit design is less complex compared to switch mode configurations. The constant current source helps achieve wide voltage input range. The current limit function protects MOSFET overload and reduces the power dissipation, which is less compared to linear voltage drop circuits. Galvanic isolation is achieved between the FPGA/microcontroller and the input signal. Further, isolation of common mode and differential mode noise is achieved.
[0044] In an aspect, the proposed system can include a constant current module that can be configured to generate a constant current, an opto-isolator module that can be configured to provide galvanic isolation, and a digital sampling module that can be configured to compensate for the high power dissipation. In an embodiment, the constant current module can have a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), and a resistor to form a constant current circuit. The constant current circuit can be configured to enable a constant current flow through the light emitting diode (LED) of the opto-isolator module. The constant current module can further help achieve a wider input sensing range to drive the opto-isolator.
[0045] In an embodiment, the opto-isolator module can have an opto-isolator that can be driven by the constant current generated by the constant current module, wherein the opto-isolator can be configured to provide galvanic isolation between the field-programmable gate array (FPGA)/ microcontroller and the input signal, i.e., the opto-isolator prevents any direct conduction between the two. In an embodiment, the digital sampling module can have an opto-isolator along with resistors and a BJT to form a digital sampling circuit. The digital sampling circuit can be configured to compensate for the excess high power dissipated by the MOSFET in the constant current circuit.
[0046] FIG. 1illustrates an exemplary circuit diagram 100 in accordance with embodiments of the present disclosure. In an embodiment, a constant current circuit can be configured to enable a constant current flow through the LED of the opto-isolator. In an embodiment, the opto-isolator can be configured to provide galvanic isolation between the FPGA/ microcontroller and the input signal. In an embodiment, the digital sampling circuit can be configured to compensate for the excess high power produced by the MOSFET in the constant current circuit.
[0047] As shown in the FIG. 1, the circuit diagram can be divided for better understanding into sub-circuits including a constant current circuit, an opto-isolator circuit, and a digital sampling circuit. In an embodiment, the constant current circuit can include a MOSFET M1, a BJT Q1, and a resistor R2. The opto-isolator circuit includes an opto-isolator ISO1. The digital sampling circuit includes an opto-isolator ISO2, a BJT Q2, and resistors R2 and R5.
[0048] In an embodiment, the MOSFET M1 in the constant current circuit can be configured to generate a constant current. This constant current output can help to achieve wider input sensing range to drive the opto-isolator. The constant current can be fed to the LED of the opto-isolator IOS1. The opto-isolator ISO1 can be configured to provide a galvanic isolation between the FPGM/ microprocessor and the input signal, wherein theopto-isolator ISO1 can sense the input signal by transferring electrical signals between the two isolated circuits using light from the LED which can be proportional to the input constant current. In an embodiment, power dissipation, if any, in the MOSFET M1 can be compensated for by the digital sampling circuit.
[0049] In an aspect, the digital logic implemented within the FPGM/ microprocessor can be configured to give pulse to the opto-isolator ISO2 through a control signal, wherein the control signal can be given for a fraction of time to maintain a low duty cycle. This low duty cycle can limit the power dissipation by the MOSFET M1 of the constant current circuit.
[0050] FIG. 2 illustrates an exemplary flow diagram 200 of operation of the proposed input sensing circuit in accordance with an embodiment of the present disclosure.
[0051] In an aspect, the method can include the steps of, at step 202, configuring a first opto-isolator (ISO1) to sense input signal; configuring, at step 204, a constant current circuit generate a constant current; and, at step 206, configuring a digital sampling circuit comprising a second opto-isolator (ISO2), wherein the constant current circuit enables constant current through LED of the first opto-isolator (ISO1) by providing driving current for the first opto-isolator (ISO1) in a wider input sensing range, and wherein power dissipation in the constant current circuit is compensated by the digital sampling circuit.
[0052] In another aspect, the constant current circuit can include a MOSFET M1, a BJT Q1, and a resistor R2. Furthermore, the digital sampling circuit can further include a resistor R2, a resistor R5, and a BJT Q2.
[0053] In yet another aspect, the second opto-isolator (ISO2) can be configured to receive a pulse from a FPGA/microcontroller through a control signal in order to obtain the state of the input signal, wherein the control signal is given for a defined time in order to maintain low duty cycle.
[0054] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE INVENTION
[0055] The present disclosure provides a system and method for improved digital input sensing.
[0056] The present disclosure provides a single digital input circuit that processes all mentioned input signal ranges to minimize inventory to reduce cost.
[0057] The present disclosure provides a single digital input circuit that works in linear mode to avoid issues pertaining to Electromagnetic compatibility (EMC) or electromagnetic interference (EMI).
[0058] The present disclosure provides a single digital input circuit that enables lower power dissipation when compared to linear voltage drop circuit.
[0059] The present disclosure provides a single digital input circuit that uses a less complex design when compared with switch mode kind of configuration.
[0060] The present disclosure provides a single digital input circuit that has a wide voltage input range by using constant current source.
[0061] The present disclosure provides ide a single digital input circuit that has a current limit function that protects MOSFET overload.
[0062] The present disclosure provides a single digital input circuit that configures Galvanic isolation between input and FPGA/microcontroller.
[0063] The present disclosure provides a single digital input circuit that provides isolation of common mode and differential mode noise.