FIELD OF INVENTION
The invention pertains to power saving in SoC that implement Device Wire Adapter (DWA) functionality of the Certified Wireless USB Protocol (CWUSB). It also pertains to using cross layer parameters of Device Wire Adaptor in order to optimized-dynamic power consumption in DWA SoC
DESCRIPTION OF THE RELATED ART
A CWUSB DWA bridges between upstream wireless interface and downstream wired interface. The PHY rate of this upstream can be varying while the PHY rate of this downstream is always constant. The consequent rate mismatch results in downstream interface to be in idle state for long time.
SUMMARY OF THE INVENTION
The invention relates to the field of Certified Wireless Universal Serial Bus (CWUSB) protocol integrated into a System on Chip (SoC). In particular, the invention relates to power saving in SoC that implements Device Wire Adapter (DWA) functionality of the CWUSB. The CWUSB integrated SoC includes an upstream wireless interface and a downstream wired interface. The upstream wireless interface comprises varying and low physical layer transmission rates (PHY rates) and the downstream wired interface comprises constant and high

PHY rates. Therefore, the overall throughput at the upstream wireless interface is lesser than the downstream wired interface and an idle state is established at the downstream wired interface. This results in consumption of additional power during the idle state. The invention proposes a method for saving the additional power consumed during the idle state by determining power saving operating points (PSOPs). A PSOP is a decision that aids in determining time frames for which the power of hardware components of the CWUSB protocol is required to be saved. The PSOPs are determined by finding an idle factor based on the PHY rates of the upstream wireless interface and the downstream wired interface by a power manager The method also incorporates the effect of system buffer availability and protocol overhead to determine the PSOPs. The power manager saves the power based on PSOPs by using various methods such as Dynamic Frequency Scaling, Dynamic Voltage Scaling etc.
Accordingly the invention explains a method of dynamic power saving in CWUSB DWA SOC by determining power saving operating points (PSOPs) where the PSOPs are determined by finding an idle factor based on the PHY rates of an upstream wireless interface and a downstream wired interface by a SoC power manager.
The method further comprising the steps of incorporating the effect of system buffer availability and protocol overhead to determine the PSOPs. The SoC Power Manager is provided with an input of the instantaneous PHY Rate of the Upstream Wireless interface. The SoC Power Manager is provided with an input

of the Buffer Watermark which indicates the buffer availability to store upstream or downstream packets for a determined period of time. The SoC Power Manager is provided with an input of MMC Scheduling and CWUSB protocol overhead. The SoC Power Manager further calculates the ratio of upstream PHY rate to the constant downstream PHY Rate which is the Downstream Idle Factor. The method further comprising the steps of the SoC Power Manager determining the total period and schedule time of upstream data transfer using the information in the MMC of CWUSB and from the DWA Protocol information fields. The method further comprising the steps of determining the approximate ■ period that the downstream interface needs to be active in order to transmit/receive all the upstream transfers by multiplying the total period taken by the upstream interface to transmit/receive packets with the Downstream Idle Factor. If the power saved is greater than a pre-determined threshold value, the SoC Power Manager uses a power saving technique to minimize the power consumption.
Accordingly the invention explains a system of dynamic power saving in CWUSB DWA SOC by determining power saving operating points (PSOPs) where the PSOPs are determined by finding an idle factor based on the PHY rates of an upstream wireless interface and a downstream wired interface by a SoC power manager.
These and other objects, features and advantages of the present invention will become more apparent from the ensuing detailed description of the invention taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
Figure 1 depicts Typical DWA SoC and its flow of Data
Figure 2 depicts DWA SoC Power Manager Block
DETAILED DESCRIPTION OF THE INVENTION
The preferred embodiments of the present invention will now be explained with reference to the accompanying drawings. It should be understood however that the disclosed embodiments are merely exemplary of the invention, which may be embodied in various forms. The following description and drawings are not to be construed as limiting the invention and numerous specific details are described to provide a thorough understanding of the present invention, as the basis for the claims and as a basis for teaching one skilled in the art how to make and/or use the invention. However in certain instances, well-known or conventional details are not described in order not to unnecessarily obscure the present invention in detail.
System on a Chip has become very prevalent in the embedded and wireless industry. More and more IPs are getting integrated into an SoC. Power consumed by an SoC is of utmost importance as it directly influences the battery

life time of mobile and CE devices.
A number of power saving enablers are being incorporated into hardware IPs such as
(1) Multiple Voltage Domains
(2) Module Clock Gating
(3) Dynamic Frequency Scaling (DFS)
(4) Dynamic Voltage Scaling (DVS)
It is the responsibility of SAA/ via Processor Cores to use the power save enablers in order to save dynamic power. A SoC Power Manager SAA/ is required in every SoC SAA/ in order to identify power save operating points (PS OP) and exercise control over hardware IPs accordingly. A PSOP is a decision that determines when and how long to save hardware module's power consumption.
In this invention, we identify the power save operating points (PSOPs) based on the cross layer parameters and system parameters of the upstream and downstream interface. Specifically, we use the ratio of wireless PHY rate to the constant wired PHY rate in order to derive "Downstream Idle Factor (DIF)". The DIF is combined with buffer availability and protocol overhead in determining the PSOPs.
A DWA SoC typically consists of the following hardware IPs and processor core

1. CWUSB Device IP
2. USB2.0 Host Controller IP
3. ARM Core
4. SDRAM
5. Other Peripherals
As seen in the figure 1, the CWUSB Device IP being the upstream interface is the initiator of any data flow through the DWA SoC. The upstream wireless PHY communicates with CWUSB HOST System using any of the following PHY Rates
53.3, 80, 1067, 160, 200, 320, 400, 480 Mbps.
Whereas the downstream wired USB2.0 host controller interface communicates with downstream USB2.0 Device using constant rate of 480Mbps only.
As can be seen from the Data Flow part of figure 1, the time taken to transmit/receive a fixed bytes block of data through the upstream interface (operating at 53Mbps) is much higher that the time taken to receive/transmit the same fixed bytes block through the downstream interface.
This rate mismatch results in the downstream USB2.0 Host Controller IP to be in idle state for a long time.

The USB2.0 Host Controller cannot be placed in the USB Suspend State since it typically takes 20ms to resume from the suspend state. This 20ms is a long time and will result in huge latency.
The current invention describes a novel method based on cross layer parameters to determine the PSOP at which to minimize power consumption of USB2.0 Host Controller IP.
The method described will typically be implemented in SAA/ called SoC Power Manager
The SoC Power Manager system is shown in figure 2.
The SoC Power Manager as shown in figure 2 has the following inputs
1. The instanaeous PHY Rate of the Upstream Wireless interface
a. The PHY rate can be obtained using methods such as ranging, information from channel time allocation lEs, using LQI etc
2. The Buffer Watermark
a. It indicates the buffer availability to store upstream or downstream packets for a determined period of time
3. MMC Scheduling and CWUSB protocol overhead
a. This factor will be a constant for most of the time.

The SoC Power Manager calculates the ratio of upstream PHY rate to the constant downstream PHY Rate
Downstream Idle Factor = Upstream PHY Rate/ Downstream PHY Rate (480Mbps)
The SoC Power Manager determines the total period and schedule time of upstream data transfer using in the information in the MMC of CWUSB and from the DWA Protocol information fields.
The total period is multiplied with the Downstream Idle Factor to determine the approximate period that the downstream interface needs to be active in order to transmit/receive all the upstream transfers.
If X is the total period taken by the upstream interface to transmit/receive packets, then the amount of time required by the downstream interface is approximately
Y = X * Downstream Idle Factor
Given the 2 value of X and Y, the SoC Power manager checks the buffer availability to store packets.

The SoC Power manager determines the appropriate PS OP based on the 3 values of (X, Y and Buffer Availability).
The SoC Pov^er Manager computes the power saved using the PS OP. If the power saved is-greater than a pre-determined threshold value, the SoC Power Manager uses any one of the power save techniques such as DPS, DVS, Clock Gating to minimize the power consumption of USB2.0 Host Controller IP.
Some more decision factors such as the reliability of the wireless link are being studied to influence the PS OP decision.
The method of using the upstream wireless rate and downstream constant PHY rate to determine the Downstream Idle Factor is the best method/system of this invention.
And also combining the cross layer PHY parameters with system resources such as buffer availability to determine the most optimum PS OP is the best method/system of this invention.
Advantages
Srnce wireless PHY rates are always varying and as wireless PHY is not as reliable as wired PHY, the overall throughput of wireless interface is always less than the wired interface. Hence by using this above mentioned method, power

consumed by the downstream wired Host Controller IP can be reduced to a large extent.
It will also be obvious to those skilled in the art that other control methods and apparatuses can be derived from the combinations of the various methods and ' apparatuses of the present invention as taught-by the description and the accompanying drawings and these shall also be considered within the scope of the present invention. Further, description of such combinations and variations is therefore omitted above. It should also be noted that the host for storing the applications include but not limited to a microchip, microprocessor, handheld communication device, computer, rendering device or a multi function device.
Although the present invention has been fully described in connection with the preferred embodiments thereof with reference to the accompanying drawings, it is to be noted that various changes and modifications are possible and are apparent to those skilled in the art. Such changes and modifications are to be understood as included within the scope of the present invention as defined by the appended claims unless they depart there from.

GLOSSARY OF TERMS AND THEIR DEFINITIONS:
CWUSB : Certified Wireless USB
DWA: Device Wire Adapter: A Wireless Hub with CWUSB Device as upstream interface and USB2.0 Host as downstream interface. It is an enabler for classic USB2.0 Devices to become wireless.
MMC: Micro Management Commands: A CWUSB Upstream Command that contains the data transfer information/PHY layer information/timing information of all data transfers.
SoC: System on a Chip.
DPS: Dynamic Frequency Scaling: A method of reducing the clock frequency to a particular hardware IP.
DVS: Dynamic Voltage Scaling: A method of reducing the supply voltage to a particular hardware IP.
Clock Gating: A method of switching of the clock to a particular hardware IP.
PS OP: Power Save Operating Point: The Decision point which

determines when and how long should a particular hardware IP should be enabled for reduced power consumption.

We Claim:
1. A method of dynamic power saving in CWUSB DWA SOC by determining power saving operating points (PSOPs) where the PSOPs are determined by finding an idle factor based on the PHY rates of an upstream wireless interface and a downstream wired interface by a SoC power manager.
2. The method according to claim 1 further comprising the steps of incorporating the effect of system buffer availability and protocol overhead to determine the PSOPs.
3. The method as claimed in claim 1 wherein the SoC Power Manager is provided with an input of the instantaneous PHY Rate of the Upstream Wireless interface.
4. The method as claimed in claim 1 wherein the SoC Power Manager is provided with an input of the Buffer Watermark, which indicates the buffer availability to store upstream or downstream packets for a determined period of time.
5. The method as claimed in claim 1 wherein the SoC Power Manager is provided with an input of MMC Scheduling and CWUSB protocol overhead.
6. The method as claimed in claim 1 wherein the SoC Power Manager further

calculates the ratio of upstream PHY rate to the constant downstream PHY Rate which is the Downstream Idle Factor.
7. The method as claimed in claim 1 further comprising the steps of the SoC Power Manager determining the total period and schedule time of upstream data transfer using the information in the MMC of CWUSB and from the DWA Protocol information fields.
8. The method according to claim-1 further comprising the steps of determining the approximate period that the downstream interface needs to be active in order to transmit/receive all the upstream transfers by multiplying the total period taken by the upstream interface to transmit/receive packets with the Downstream Idle Factor.
9. The method according to claim 1 wherein if the power saved is greater than a pre-determined threshold value, the SoC Power Manager uses a power saving technique to minimize the power consumption.
10. A system of dynamic power saving in CWUSB DWA SOC by determining
power saving operating points (PSOPs) where the PSOPs are determined by
finding an idle factor based on the PHY rates of an upstream wireless interface
and a downstream wired interface by a SoC power manager.
11 A method of dynamic power saving in CWUSB DWA SOC substantially

described particularly with reference to the accompanying drawings.
12. A system of dynamic power saving in CWUSB DWA SOC substantially described particularly with reference to the accompanying drawings.