Claims:What is claimed is:
1. A system for improving the performance of amplifiers using bias current, comprising:
a computing device 102 comprises a simulation module 104 configured to design an architecture of an amplifier using an active comb filter to remove the selected frequencies of various signals, whereby the active comb filter is based on only operational transconductance amplifiers (OTAs) and capacitors that makes it suitable for implementation of monolithic integrated circuits (ICs), the computing device 102 configured to perform simulation using cadence virtuoso analog design environment in CMOS technology to examine the effect of bias current for different ECG performance parameters;

2. The system of claim 1, wherein the computing device 102 comprises simulation module 104 configured to test the workability of the analog circuit for different test signals of 60, 180, 300, and 420 Hz as in ECG signal.

3. The system of claim 1, wherein the simulation module 104 configured to control the bias current of this analog circuit by controlling the voltage of the OTA.

4. The system of claim 1, wherein the active comb filter comprises a resistance (??) and an inductance (??) are primarily dependent on the bias current of respective OTAs.

5. The system of claim 1, wherein the operational transconductance amplifiers comprises of NMOS transistors of 0.45 W (µm) and 0.18 L (µm).

6. The system of claim 1, wherein the operational transconductance amplifiers further comprises of PMOS transistors of 0.90 W (µm) and 0.18 L (µm).

7. A method for improving the performance of amplifiers using bias current, comprising:
designing an amplifier using an active comb filter on a computing device to remove the selected frequencies of various signals;

testing the workability of the analog circuit for different test signals of 60, 180, 300, and 420 Hz as in ECG signal using the simulation module;

examine the effect of bias current for different ECG performance parameters using the simulation module; and

increasing the bias current using the simulation module to improve the ECG performance in terms of gain and bandwidth at 0.18 µm CMOS technology. , Description:TECHNICAL FIELD
[001] The present disclosure generally relates to the field of electrocardiogram signal processing system. More particularly, the present disclosure relates to a system to improve the performance of an operational trans-conductance amplifier at standard complementary metal-oxide-semiconductor (CMOS) technology.

BACKGROUND
[002] Electrocardiography (ECG) is the process of recording the electrical activity of the heart over a period of time using electrodes placed on the human body. In recent years, the smaller size and lower power consumption makes most of the ECG measurement systems portable. The ECG amplifiers are normally powered by battery due to its wearable condition. Normally, the ECG measurement setup consists of electrodes to measure the signal from the human body, an analog front end (AFE) amplifier to amplify the received signal, an analog to digital converter (ADC) for digitizing the analog signal, and a display device to monitor the heart of the patient regularly. When the signal transmission line of an ECG amplifier is coupled with certain frequency components, the harmonic interference may affect the transmitted data. The most common type of interference for biomedical signals is the power line interference. Electric field and magnetic field interferences are two primary components in power line interferences. A spike at 50/60 Hz frequency is generated in electric field interference, whereas the magnetic field is produced due to the transformer in the power supply causes interference to create harmonic frequencies of the fundamental. For example, in a medical clinic where a number of biomedical instruments run on AC power line, the electric and magnetic field interferences are designed. Hence, the power line frequency and its harmonics normally corrupt the physiological signals. These interferences may be removed using both digital and analog filtering techniques. In analog circuit designing, the operational amplifiers are the primary functional units. However, the limitations in bandwidth and slew rate of operational amplifiers lead the analog designer to search for other possibilities. In general, OTA is a voltage controlled current source (VCCS) and uses an additional input for a current to control the amplifier's transconductance. Recently, operational transconductance amplifier (OTA) has been considered as the most suitable building blocks in analog signal processing (ECG amplifiers) due to its higher bandwidth, slew rate, and transconductance gain. Hence, the circuits developed using OTAs are most likely to possess intrinsic electronic control of parameters such as the cut-off frequency, quality factor, gain of a filter or frequency of oscillation, and the condition of oscillation of an oscillator.

[003] In the light of the aforementioned discussion, there exists a need for a certain system with novel methodologies that would overcome the above-mentioned disadvantages.

SUMMARY
[004] The following presents a simplified summary of the disclosure in order to provide a basic understanding to the reader. This summary is not an extensive overview of the disclosure and it does not identify key/critical elements of the invention or delineate the scope of the invention. Its sole purpose is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later.

[005] An objective of the invention directed towards designing an amplifier using an active comb filter to remove the selected frequencies of various signals.

[006] Another objective of the invention directed towards using operational transconductance amplifiers (OTAs) and capacitors that makes it suitable for implementation of monolithic integrated circuits (ICs).

[007] Another objective of the invention directed towards using Cadence Virtuoso analog design environment, the effect of bias current is examined for different ECG performance parameters.

[008] Another objective of the invention directed towards increasing the performance in terms of gain and bandwidth considerably for an increase in bias current.

[009] Another objective of the invention directed towards developing the integrated circuits using OTAs are most likely to possess intrinsic electronic control of parameters such as the cut-off frequency, quality factor, gain of a filter or frequency of oscillation, and the condition of oscillation of an oscillator.

[0010] According to an exemplary aspect, a system for improving the performance of amplifiers using bias current, comprising a computing device comprises a simulation module configured to design an architecture of an amplifier using an active comb filter to remove the selected frequencies of various signals.

[0011] According to another exemplary aspect, the active comb filter is based on only operational transconductance amplifiers (OTAs) and capacitors that makes it suitable for implementation of monolithic integrated circuits (ICs), the computing device 102 configured to perform simulation using cadence virtuoso analog design environment in CMOS technology to examine the effect of bias current for different ECG performance parameters.

BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 is a circuit diagram depicting a schematic representation of a computing system, in accordance with one or more embodiments.

[0013] FIG. 2 is an example diagram depicting a schematic representation of an operational transconductance amplifier, in accordance with one or more embodiments.

[0014] Referring to FIG. 3 is an example diagram depicting a schematic representation of an operational trans-conductance amplifier symbol, in accordance with one or more embodiments.

[0015] FIG. 4 is an example diagram depicting a schematic representation of an internal structure of the operational transconductance amplifier, in accordance with one or more embodiments.

[0016] FIG. 5 is an example diagram depicting a schematic representation of an OTA-C notch filter, in accordance with one or more embodiments.

[0017] FIG. 6 is an example diagram depicting a schematic representation of a simulation setup in cadence, in accordance with one or more embodiments.

[0018] FIG. 7 is an example diagram depicting exemplary graphs of a gain vs frequency response, in accordance with one or more exemplary embodiments.

[0019] FIG. 8 is an example diagram depicting exemplary graphs of a gain vs frequency response, in accordance with one or more exemplary embodiments.

[0020] FIG. 9 is an example diagram depicting exemplary graphs of a gain vs frequency response, in accordance with one or more exemplary embodiments.

[0021] FIG. 10 is a flowchart depicting an exemplary method for improving the performance of amplifier using bias current, in accordance with one or more exemplary embodiments.

[0022] FIG. 11 is a block diagram illustrating the details of a digital processing system in which various aspects of the present disclosure are operative by execution of appropriate software instructions.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0023] It is to be understood that the present disclosure is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The present disclosure is capable of other embodiments and of being practiced or of being carried out in various ways. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting.

[0024] The use of “including”, “comprising” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. The terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item. Further, the use of terms “first”, “second”, and “third”, and the like, herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

[0025] Referring to FIG. 1, is a block diagram 100 depicting a computing system, in accordance with one or more exemplary embodiments. The computing system 102 may include a simulation module 104. The simulation module 104 may be configured to perform simuation using cadence virtuoso analog design environment in CMOS technology to examine the effect of bias current for different ECG performance parameters. The performance of gain and bandwidth considerably increases for an increase in bias current. The simulation module 104 may be configured to design an amplifier using an active comb filter to remove the selected frequencies of various signals. The filter is based on only operational transconductance amplifiers (OTAs) and capacitors that makes it suitable for implementation of monolithic integrated circuits (ICs). The simulation module 104 may be configured to test the workability of the analog circuit for different test signals of 60, 180, 300, and 420 Hz as in ECG signal. The simulation module 104 may also be configured to control the bias current of this analog circuit by controlling the voltage of the OTA.

[0026] The ECG performance for different bias current and corresponding values of gain and bandwidth are represented in the following table:
Bias Current,
IB (µA) Gain (dB) Bandwidth (Hz)
103.6 45.25 57
263.4 47.23 72
523.2 51.42 93

[0027] Referring to FIG. 2 is an example diagram 200 depicting a schematic representation of an operational transconductance amplifier, in accordance with one or more embodiments. The instrumentation amplifier used in the ECG amplifier is said to be the operational transconductance amplifier. The OTA design 200 may be implemented as long tailed pairs with current mirror circuit. The OTA design 200 comprises input voltages (Vp and Vn) 202a-202b, supply voltages (??dd and ??ss) 206a-206b, biasing voltage (??con) 208. The input voltages (Vp and Vn) 202a-202b may be chosen as 1V sine wave signal for simulation purpose.

[0028] Referring to FIG. 3 is an example diagram 300 depicting a schematic representation of an operational trans-conductance amplifier symbol, in accordance with one or more embodiments. The operational transconductance amplifier symbol 300a comprises of an input differential pair and an output current mirror. The operational transconductance amplifier symbol 300 comprises input voltages (Vp and Vn) 302a-302b, an output current (Iout) 304, and a bias current (IB) 303, biasing voltage (??con) 308. The OTA can be referred as active current mode building block and is the most popular building block for designing of integrated circuits and suitable for various biomedical applications. In comparison to an operational amplifier, the operational transconductance amplifier (OTA) possesses higher bandwidth and slew rate. The biasing current (IB) 303 electronically controls the transconductance gain (??) of OTA over a wide range. The PMOS devices are preferred over NMOS due to the less flicker noise in PMOS devices. In order to reduce the flicker noise, it is necessary to increase the W/L ratio of input transistor in the first stage of the amplifier. The device matching in the second stage of the amplifier does not provide any change in the noise performance. The input voltages (Vp and Vn) 302a-302b may be chosen as 1V sine wave signal for simulation purpose. The values of bias current (IB) 303 may be adjusted to 103.6 µA, 263.4 µA and 523. The increase in bias current (IB) 303 may improve the ECG performance parameters in terms of gain and bandwidth can be obtained. The transconductance gain for CMOS based OTA is expressed as

[0029] Where ?? is constant, ?? and ??ox represents the mobility of electron and the oxide capacitance, respectively; the bias current (????) 303 is controlled by the biasing voltage (??con) 308; the channel width and length of the transistors are represented by ?? and ??, respectively.

[0030] As it is a low-frequency operation, a low noise and low distortion OTA (presented in Fig. 3B and Fig. 4) is suitable for low-frequency application.

[0031] Referring to FIG. 4 is an example diagram 400 depicting a schematic representation of an internal structure of the operational transconductance amplifier, in accordance with one or more embodiments. The internal structure of the operational transconductance amplifier 400 comprises input voltages (Vp and Vn) 402a-402b, output current (Iout) 404, a bias current (????) 403, supply voltages (??dd and ??ss) 406a-406b, biasing voltage (??con) 408, PMOS transistors (M3, M4, M5, M6, M7, M8, M9, and M10) 410a-410h, NMOS transistors (M1, M2, M11, M12, M13, M14, M15, M16, M17, M18, and M19) 412a-412k, The width and length of NMOS transistors (M1, M2, M11, M12, M13, M14, M15, M16, M17, M18, and M19) 412a-412k may be of 0.45 W (µm) and 0.18 L (µm). The width and length of PMOS transistors (M3, M4, M5, M6, M7, M8, M9, and M10) 410a-410h may be of 0.90 W (µm) and 0.18 L (µm). The OTA is simulated using cadence virtuoso analog design environment in 0.18 ??m CMOS technology. The value of supply voltages (??dd and ??ss) 406a-406b ??dd = 1.8 V and ??ss = -1.8 are may be used for simulation. The biasing current (????) 403 of OTA is primarily controlled by the biasing voltage (Vcon) 408. An increase of the biasing voltage (??con) 408 enhances the biascurrent (IB) 403 that results in the increase of output current value (Iout) 404.

[0032] The dimensions of MOS transistors are represented in the following table:

MOS Transistors W (µm) L (µm)
M1, M2, M11, M12, M13, M14, M15, M16, M17, M18, and M19 0.45 0.18
M3, M4, M5, M6, M7, M8, M9, and M10 0.90 0.18

[0033] Referring to FIG. 5 is an example diagram 500 depicting a schematic representation of an OTA-C notch filter, in accordance with one or more embodiments. The OTA-C notch filter 500 comprises a resistance (R) 502, and inductance 504. The resistance (R) 502 includes operational transconductance amplifiers 506a-506d, and internal capacitor (C) 508a, load capacitor (CL) 508b. The quantitative values of resistance (??) and inductance (??) are primarily dependent on the bias current of respective OTAs 502a-502d. Hence, the bias current has a major impact on angular frequency (??0), quality factor (??0), and bandwidth (???) of OTAs. It is also apparent that ??0 can be tuned independently of ??0 by R.

[0034] The value of internal capacitor (C) 508a may be adjusted to 999.85 nF and the value of load capacitor (CL) 508b may be adjusted to 21 nF. The value of resistance (R) 502 adjusted to 100 kO by biasing the current of corresponding OTA circuit. Therefore, the characteristics expressions of all the parameters of proposed notch filter can be expressed as:

[0035] It is obvious that once the values of internal capacitor (C) 508a and load capacitor (CL) 508b are fixed as required, the notch frequencies can still be tuned by varying ???? using bias currents of OTAs. The similar comment is also work for the characteristics parameters of quality factor (??0) and bandwidth (???).

[0036] Referring to FIG. 6 is an example diagram 600 depicting a schematic representation of a simulation setup in cadence, in accordance with one or more embodiments. The simulation setup in cadence 600 comprises input voltages (Vp and Vn) 602a-602b, a black box of OTA 604, and supply voltages (??dd and ??ss) 606a-606b. The black box of OTA 604 may primarily consists of the internal structure of OTA. The supply voltages (??dd and ??ss) 606a-606b used for simulation are ??dd = 1.8 V and ??ss = -1.8 V. The Input voltages (Vp and Vn) 602a-602b are chosen as 1V sine wave signal for the simulation purpose. Physiological signal such as ECG signal primarily contains the power line frequency and its harmonics along with the input signal.

[0037] Referring to FIG. 7 is an example diagram 700 depicting exemplary graphs of a gain vs frequency response, in accordance with one or more exemplary embodiments. The exemplary graph 700 may include frequency (Hz) 702 on X-axis and gain (dB) 704 on Y-axis. The exemplary graph 700 depicting frequency response of OTA for bias current (IB) of 103.6 µA.

[0038] Referring to FIG. 8 is an example diagram 800 depicting exemplary graphs of a gain vs frequency response, in accordance with one or more exemplary embodiments. The exemplary graph 800 may include frequency (Hz) 802 on X-axis and gain (dB) 804 on Y-axis. The exemplary graph 800 depicting the frequency response of OTA for bias current (IB) of 263.4 µA.

[0039] Referring to FIG. 9 is an example diagram 900 depicting exemplary graphs of a gain vs frequency response, in accordance with one or more exemplary embodiments. The exemplary graph 900 may include frequency (Hz) 902 on X-axis and gain (dB) 904 on Y-axis. The exemplary graph 900 depicting the frequency response of OTA for bias current (IB) of 523.2 µA.

[0040] Referring to FIG. 10 is a flowchart 1000 depicting an exemplary method for improving the performance of amplifier using bias current, in accordance with one or more exemplary embodiments. As an option, the method 1000 is carried out in the context of the details of FIG. 1, FIG. 2 FIG. 3, FIG. 4 FIG.5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, and FIG. 10. However, the method 1000 is carried out in any desired environment. Further, the aforementioned definitions are equally applied to the description below.

[0041] The exemplary method 1000 commences at step 1002, designing an amplifier using an active comb filter on a computing device to remove the selected frequencies of various signals. Thereafter at step 1004, testing the workability of the analog circuit for different test signals of 60, 180, 300, and 420 Hz as in ECG signal using the simulation module. Thereafter at step 1006, examine the effect of bias current for different ECG performance parameters using the simulation module. Thereafter at step 1008, increasing the bias current using the simulation module to improve the ECG performance in terms of gain and bandwidth at 0.18 µm CMOS technology.

[0042] Referring to FIG. 11, FIG. 11 is a block diagram 1100 illustrating the details of a digital processing system 1100 in which various aspects of the present disclosure are operative by execution of appropriate software instructions. The digital processing system 1100 may correspond to the computing device 102 (or any other system in which the various features disclosed above can be implemented).

[001] Digital processing system 1100 may contain one or more processors such as a central processing unit (CPU) 1110, random access memory (RAM) 1120, secondary memory 1127, graphics controller 1160, display unit 1170, network interface 1180, and input interface 1190. All the components except display unit 1170 may communicate with each other over communication path 1150, which may contain several buses as is well known in the relevant arts. The components of Figure 11 are described below in further detail.

[002] CPU 1110 may execute instructions stored in RAM 1120 to provide several features of the present disclosure. CPU 1110 may contain multiple processing units, with each processing unit potentially being designed for a specific task. Alternatively, CPU 1110 may contain only a single general-purpose processing unit.

[003] RAM 1120 may receive instructions from secondary memory 1130 using communication path 1150. RAM 1120 is shown currently containing software instructions, such as those used in threads and stacks, constituting shared environment 1125 and/or user programs 1126. Shared environment 1125 includes operating systems, device drivers, virtual machines, etc., which provide a (common) run time environment for execution of user programs 1126.

[004] Graphics controller 1160 generates display signals (e.g., in RGB format) to display unit 1170 based on data/instructions received from CPU 1110. Display unit 1170 contains a display screen to display the images defined by the display signals. Input interface 1190 may correspond to a keyboard and a pointing device (e.g., touch-pad, mouse) and may be used to provide inputs. Network interface 1180 provides connectivity to a network (e.g., using Internet Protocol), and may be used to communicate with other systems (such as those shown in Figure 1) connected to the network.

[005] Secondary memory 1130 may contain hard drive 1135, flash memory 1136, and removable storage drive 1137. Secondary memory 1130 may store the data software instructions (e.g., for performing the actions noted above with respect to the Figures), which enable digital processing system 1100 to provide several features in accordance with the present disclosure.

[006] Some or all of the data and instructions may be provided on removable storage unit 1140, and the data and instructions may be read and provided by removable storage drive 1137 to CPU 1110. Floppy drive, magnetic tape drive, CD-ROM drive, DVD Drive, Flash memory, removable memory chip (PCMCIA Card, EEPROM) are examples of such removable storage drive 1137.

[007] Removable storage unit 1140 may be implemented using medium and storage format compatible with removable storage drive 1137 such that removable storage drive 1137 can read the data and instructions. Thus, removable storage unit 1140 includes a computer readable (storage) medium having stored therein computer software and/or data. However, the computer (or machine, in general) readable medium can be in other forms (e.g., non-removable, random access, etc.).

[008] In this document, the term "computer program product" is used to generally refer to removable storage unit 1140 or hard disk installed in hard drive 1135. These computer program products are means for providing software to digital processing system 1100. CPU 1110 may retrieve the software instructions, and execute the instructions to provide various features of the present disclosure described above.

[009] The term “storage media/medium” as used herein refers to any non-transitory media that store data and/or instructions that cause a machine to operate in a specific fashion. Such storage media may comprise non-volatile media and/or volatile media. Non-volatile media includes, for example, optical disks, magnetic disks, or solid-state drives, such as storage memory 1130. Volatile media includes dynamic memory, such as RAM 1120. Common forms of storage media include, for example, a floppy disk, a flexible disk, hard disk, solid-state drive, magnetic tape, or any other magnetic data storage medium, a CD-ROM, any other optical data storage medium, any physical medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASH-EPROM, NVRAM, any other memory chip or cartridge.

[0010] Storage media is distinct from but may be used in conjunction with transmission media. Transmission media participates in transferring information between storage media. For example, transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise bus (communication path) 1150. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave and infra-red data communications.

[0011] Reference throughout this specification to “one embodiment”, “an embodiment”, or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases “in one embodiment”, “in an embodiment” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0012] Furthermore, the described features, structures, or characteristics of the disclosure may be combined in any suitable manner in one or more embodiments. In the above description, numerous specific details are provided such as examples of programming, software modules, user selections, network transactions, database queries, database structures, hardware modules, hardware circuits, hardware chips, etc., to provide a thorough understanding of embodiments of the disclosure.

[0013] Although the present disclosure has been described in terms of certain preferred embodiments and illustrations thereof, other embodiments and modifications to preferred embodiments may be possible that are within the principles and spirit of the invention. The above descriptions and figures are therefore to be regarded as illustrative and not restrictive.

[0014] Thus the scope of the present disclosure is defined by the appended claims and includes both combinations and sub-combinations of the various features described hereinabove as well as variations and modifications thereof, which would occur to persons skilled in the art upon reading the foregoing description.