Description:TECHNICAL FIELD
[0001] The present disclosure relates, in general, to the embedded system, and more specifically, relates to the system and method for implementing precise timers for time-critical applications in user mode of a generic OS-based computing module/platform.

BACKGROUND
[0002] Real-time applications demand timing accuracy which can be achieved using bare metal programs that can directly target the processing element without the intervention of operating systems. However, the complexity of the task which needs to be programmed increases. Hence, hardware requirement proportionally varies based on computational power and the number of processing elements. To support this complex hardware an operating system is employed.
[0003] The operating systems are generalized for various requirements and thus use the internal schedulers which time shares the processing element based on the requirement of the task. Therefore, the timing accuracy for the timer is reduced when operating systems are employed. Hence, various challenges need to be addressed to deliver accurate timing signals to users when operating systems are employed.
[0004] Real-time operating systems use a priority-based scheduling parameter which helps to increase timing accuracy. However, the cost incurred to use them are high and driver support for hardware is not robust. As a result, non-real-time operating systems are preferred in most cases. Non-real-time operating systems have more than one mode of operation. As a result, the timer signal has to progress through multiple layers before the time-critical application executes. Moreover, the scheduling criteria are more generalized which is first in first out based or round-robin based. Hence, the scheduling of the user code based on the timer signal can introduce timing delays which can also propagate to the next timing signal, and finally, loss of interrupt can occur. To overcome these losses and error tolerances when non-real-time operating systems are used, it is mandatory for an effective method to deliver the timer expiry signal to time-critical user applications without loss of timing accuracy.
[0005] The non-real-time operating systems with intel architecture using traditional high precision event timers provide considerable timing delays. Furthermore, the drift in timers accumulates over a period of time and significantly impacts the performance of time-critical applications. The timer signals can be delivered to the processing unit from the programmable logic using various interfaces.
[0006] An example of such embedded system is recited in a patent US 2011/0173354 A1. The invention provides a hardware-implemented connection monitoring system. The system provides a mechanism to monitor input and output connections which are hardware implemented. Timer arrays with multiple timers are used to monitor the connections where for each input and output connection, the timer value is adjusted by the state machine and timer expiry is tested to report the event to the processor. The event reporting to the processor is buffered as input and output events where further necessary action is taken by the processor. However, buffering events in the queue can generate a delay in interrupting the processor. Hence, timing milestones can be missed in time-critical applications.
[0007] Another example is recited in a patent US 8,185,770 B2. The invention relates to modern computers that come with different timers having different attributes like time resolution, supported time range and time reference. The invention explains the mechanism to synchronise different types of timers available in the operating system with the single high-resolution timer (64-bit value) which may be useful in packet scheduling for data transport applications. It deals with defining and implementing an efficient algebra for computations with the timer values from multiple sources of timers having different attributes like timer range, resolution and reference time. This also defines a local timer with less consistency. This also defines a method for processing timer values in the computer using the global and local data structure.
[0008] Yet another example is recited in a patent US 2006/0218429 A1, the present invention facilitates access to timers in a computing device. The system explains the abstractions and how timer registers are set from the user space to the hardware. The timers are accessed from different layers of abstraction which are user mode, kernel mode, hardware abstraction layer and hardware layer. The kernel layer validates the user commands and sets the hardware timers in either periodic or one-shot mode. Moreover, the invention inserts the application service routine into the timer service routine to execute on the expiration of the timer. However, the invention does not specify how delay between the layers is managed. Hardware to kernel interrupt delivery generates interface delays. Whereas, Kernel to user interrupt delivery generates context switching delays.
[0009] Therefore, it is desired to overcome the drawbacks, shortcomings, and limitations associated with existing solutions, and develop a system and method for implementing precise timers for time-critical applications in user mode of a generic OS-based computing module/platform.

OBJECTS OF THE PRESENT DISCLOSURE
[0010] An object of the present disclosure relates, in general, to an embedded system, and more specifically, relates to the system and method for implementing precise timer for time-critical applications in user mode of a generic OS-based computing module/platform.
[0011] Another object of the present disclosure is to provide a system for accurate time signal delivery in a non-real-time operating system environment using time stamp counter (TSC) internal timers of x86 processing elements for delay calculation in coherence with the hardware timers on the programmable logic element.
[0012] Another object of the present disclosure is to provide a system that uses hardware timers programmed in the programmable logic element for the effective delivery of interrupts.
[0013] Another object of the present disclosure is to provide a system that predicts the next interrupt delivery time based on past interrupt time with variable scan numbers. Finally, feeds back the predicted timing interval to the programmable logic element.
[0014] Another object of the present disclosure is to provide a system that generates fixed time intervals determined by the user application, programmed in low-resolution hardware timers implemented in programmable logic elements.
[0015] Another object of the present disclosure is to provide a system for fixed time interval timeout interrupts which are generated to the processing element over the PCIe interface using message-signalled interrupts.
[0016] Yet another object of the present disclosure is to provide a system that achieves high resolution with negligible tolerances.

SUMMARY
[0017] The present disclosure relates in general, to an embedded system, and more specifically, relates to the system and method for implementing precise timers for time-critical applications in user mode of a generic OS-based computing module/platform. The main objective of the present disclosure is to overcome the drawback, limitations, and shortcomings of the existing system and solution, by providing a system that consists of a processor running a non-RTOS and programmable logic responsible for generating timer ticks. It also gives the method for achieving precise timer functionalities at the user level. Also, the timing accuracy is increased using a feedback mechanism which predicts the next timing interrupt time based on past scheduling delays.
[0018] The present disclosure provides a system for implementing a high-resolution timer for time-critical application requirements, the system includes an application programming interface (API) residing in a processing element in a user mode operative to provide access to interface parameters. The interface parameters pertain to set timer rate, get timer rate, start timer and stop timer. A programmable logic driver establishes communication with the API through a communication path and is configured to receive the interface parameters from the API, the programmable logic driver in a kernel mode uses I/O write operations to access a programmable logic element, where the processing element and the programmable logic element connected through a Peripheral Component Interconnect (PCI) interface for efficient interrupt delivery. The system provides accurate time signal delivery in a non-real-time operating system environment using time stamp counter (TSC) internal timers of x86 processing elements for delay calculation in coherence with the hardware timers on the programmable logic element.
[0019] The processing element runs Linux and the programmable logic element is configured for implementing high-resolution hardware timers. The hardware timers are programmed in programmable logic element to interrupt the processing element for every timer expiry, thereby the system uses hardware timers programmed in the programmable logic element for effective delivery of interrupts. The programmable logic element interrupts the processing element using a multi-vectored message signalled interrupts (MSI), thereby the system for fixed time interval timeout interrupts which are generated to the processing element over the PCIe interface using MSI.
[0020] The processing element is operable to set rate of timer, start and stop the timers respectively. The number of timers in the programmable logic element is scaled up based on the number of the processing element cores and timer accuracy. The past interrupt interval is used as an input to the feedback mechanism to adjust the programmable logic element timer rate with respect to the processing element ticks for every timer interrupt. Further, the processing element is the central processing unit (CPU) and the programmable logic element is the field programmable gate array (FPGA).
[0021] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The following drawings form part of the present specification and are included to further illustrate aspects of the present disclosure. The disclosure may be better understood by reference to the drawings in combination with the detailed description of the specific embodiments presented herein.
[0023] FIG. 1 illustrates an exemplary setup architecture of user application communicating with the programmable logic, in accordance with an embodiment of the present disclosure.
[0024] FIG. 2 illustrates an exemplary sequence diagram of a predictive approach which corrects the error in every consecutive timer cycle, in accordance with an embodiment of the present disclosure.
[0025] FIG. 3 illustrates an exemplary flow chart of the error prediction approach, in accordance with an embodiment of the present disclosure.
[0026] FIG. 4 illustrates an exemplary flow chart for implementing high-resolution timer for time-critical application requirements, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0027] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0028] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0029] The present disclosure relates, in general, to an embedded system, and more specifically, relates to the system and method for implementing precise timers for time-critical applications in the user mode of a generic OS-based computing module/platform. The proposed system disclosed in the present disclosure overcomes the drawbacks, shortcomings, and limitations associated with the conventional system by providing a system that enables timer response optimization/minimization in the user processing environment owing to operating system overheads.
[0030] In the proposed disclosure time critical applications require periodic synchronization of application-specific data between the subsystems. Hence, timers are used to control the frequency with which the application can synchronize with the subsystems. The time-critical applications demand higher timer accuracy with non-real time operating systems. Therefore, in the present disclosure, a predictive feedback mechanism with a PCI interface is disclosed to deliver interrupt to the operating system with minimal delay. The predictive feedback mechanism updates the timer rate registers with past interrupt delays which helps to reduce the delay in interrupt delivery. Furthermore, when the CPU is stressed the interrupt delivery delay increases, this issue is also addressed by the predictive feedback mechanism. The present disclosure can be described in enabling detail in the following examples, which may represent more than one embodiment of the present disclosure.
[0031] The advantages achieved by the system of the present disclosure can be clear from the embodiments provided herein. The system for accurate time signal delivery in a non-real time operating system environment uses time stamp counter (TSC) internal timers of x86 processing elements for delay calculation in coherence with the hardware timers on the programmable logic element. The system uses hardware timers programmed in the programmable logic element for the effective delivery of interrupts. The system predicts the next interrupt delivery time based on past interrupt times with variable scan numbers. Finally, feeds back the predicted timing interval to the programmable logic element. Further, the system generates fixed time intervals determined by the user application, programmed in low-resolution hardware timers implemented in programmable logic elements. The system for fixed time interval timeout interrupts, which are generated to the processing element over PCIe interface using message signalled interrupts and the system that achieves high resolution with negligible tolerances. The description of terms and features related to the present disclosure shall be clear from the embodiments that are illustrated and described; however, the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents of the embodiments are possible within the scope of the present disclosure. Additionally, the invention can include other embodiments that are within the scope of the claims but are not described in detail with respect to the following description.
[0032] FIG. 1 illustrates an exemplary setup architecture of user application communicating with the programmable logic, in accordance with an embodiment of the present disclosure.
[0033] Referring to FIG. 1, system 100 is configured for implementing a precise timer for time-critical applications in the user mode of a generic operating system (OS) based computing module/platform. The system 100 can be employed by an operating system component, kernel mode application, user-mode application, and the like to detect and recover from errors. The system 100 can include a user application programming interface (API) residing in a processing element 102 (also referred to as processing unit 102), programmable logic driver 104 and programmable logic 106. The user API residing in the processing element 102 in the user mode needs access to the programmable logic 106 having a timer that can be guaranteed to expire at a specified time and/or at a specified interval.
[0034] The architectural setup shown in FIG. 1 depicts programmable logic 106 and processing unit 102 and the communication of sub-units. The user application can communicate with the programmable logic driver 104 through the communication path and the programmable logic driver 104 can communicate with the programmable logic 106 through communication paths.
[0035] The user API residing in the processing element 102 is operative to provide access to interface parameters. The interface parameters pertain to set timer rate, get timer rate, start timer and stop timer. The user applications establish a connection with the programmable logic 106 through the programmable logic driver 104. The programmable logic driver 104 is configured to receive a number of interface parameters from the user application. The programmable logic driver 104 in a kernel mode uses I/O write operations to access the programmable logic element 106. The kernel mode driver may be used to implement certain hardware-independent aspects of a method for facilitating access to a timer in accordance with an embodiment of the invention. The processing element 102 and the programmable logic element 106 are connected through a PCI interface for efficient interrupt delivery.
[0036] The user API provides access to set timer rate, get timer rate, start timer and stop timer. The kernel uses I/O write operations to access the hardware. The programmable logic 106 and processing element 102 use PCI-based interfaces to communicate with each other. The interrupts which are delivered to the processing element 102 are message signalled, which are part of PCI standard. Hence, the efficiency of interrupt delivery with the increase of the number of timers is effective.
[0037] The communication between hardware, kernel level, and user level may generate delays. Hence, an effective technique is required to reduce the same. To overcome the above limitations, IOCtl() calls are used to communicate between user APIs and kernel programmable logic driver 104 (also referred to as programmable logic field programmable gate array (FPGA) driver 106 herein). The programmable logic driver 104 uses a newly designed protocol to set timer rate register, timer start and stop register as requested by the user API’s 102.
[0038] The processing element 102 running Linux and programmable logic element 106 is configured for implementing high-resolution hardware timers. The hardware timers are programmed in the programmable logic element 106 to interrupt the processing element for every timer expiry. The programmable logic element 106 interrupts the processing element 102 using multi-vectored (MSI) interrupts. The processing element 102 is operable to set rate of timer, start and stop the timers respectively.
[0039] In an embodiment, the number of timers in the programmable logic element 106 is scaled up based on the number of processing element cores and timer accuracy. The past interrupt interval is used as an input to the feedback mechanism to adjust the programmable logic element timer rate with respect to the processing element ticks for every timer interrupt. The processing element 102 is central processing unit (CPU) and the programmable logic element 106 is field programmable gate array (FPGA).
[0040] Thus, the present invention overcomes the drawbacks, shortcomings, and limitations associated with existing solutions, and provides the system for accurate time signal delivery in a non-real-time operating system environment using time stamp counter (TSC) internal timers of x86 processing elements for delay calculation in coherence with the hardware timers on the programmable logic element. The system uses hardware timers programmed in the programmable logic element for the effective delivery of interrupts. The system predicts the next interrupt delivery time based on past interrupt times with variable scan numbers. Finally, feeds back the predicted timing interval to the programmable logic element. Further, the system generates fixed time intervals determined by the user application, programmed in low-resolution hardware timers implemented in programmable logic element. The system for fixed time interval timeout interrupts which are generated to the processing element over PCIe interface using message signalled interrupts and the system achieves high resolution with negligible tolerances.
[0041] FIG. 2 illustrates an exemplary sequence diagram of a predictive approach that corrects the error in every consecutive timer cycle, in accordance with an embodiment of the present disclosure.
[0042] As depicted in FIG. 2, the sequence diagram of timer cycles is predicted and the communication between kernel, programmable logic106, and user API 102 takes place. The user API 102 calls programmable device kernel driver 104 to set the rate of the timer using IOCtl calls. Hence, kernel driver invokes write on programmable logic 106 with set rate header in protocol packet.
[0043] The application starts timer. The user API in turn calls kernel driver and gets locked until programmable device interrupts the CPU indicating timer expiry. Finally, kernel thread is released, and user API program control is returned.
[0044] The user program stops the timer using IOCtl call. Furthermore, kernel driver stops the timer using stop control packet. The four operations explained above constitute one timer cycle, where the time elapsed is calculated for exactly one timer cycle. The delay in timing is calculated using the equation
𝐷𝑒𝑙𝑎𝑦=𝑈𝑠𝑒𝑟𝑅𝑎𝑡𝑒− 𝑇𝑖𝑚𝑒𝐸𝑙𝑎𝑝𝑠𝑒𝑑
[0045] The delay calculated from the previous equation is used to predict the next timer cycle rate using the below equation.
𝑅𝑎𝑡𝑒=𝑈𝑠𝑒𝑟𝑅𝑎𝑡𝑒−𝐷𝑒𝑙𝑎𝑦
[0046] The user application executes time critical task corresponding to the timer interrupt. The process repeats with the above calculations running for every timer cycle and timer rate is predicted with the previous timer cycle delay.
[0047] FIG. 3 illustrates an exemplary flow chart of the error prediction approach, in accordance with an embodiment of the present disclosure.
[0048] The flowchart of one timer cycle is executed corresponding to the user API request. At block 302, the user application sets the timer rate with prediction error zero initially and starts the timer. At block 304, the kernel blocks the user process until the interrupt is received from the hardware for the set timer rate. The kernel thread wakes up upon receiving the timer expiry interrupt and releases the user process. At block 306, the user API stops the timer and executes the critical task. Furthermore, it calculates errors in delay for the next predictive timer cycle. Finally, the user API checks if the timer are requested for multiple cycles, and then the timer cycle is reinitiated.
[0049] FIG. 4 illustrates an exemplary flow chart for implementing a high-resolution timer for time-critical application requirements, in accordance with an embodiment of the present disclosure.
[0050] The method 400 includes block 402, the application programming interface (API) resided in the processing element 102 in a user mode operative to provide access to interface parameters. At block 404, the programmable logic driver 104 establishes communication with the API through a communication path and is configured to receive the interface parameters from the API, the programmable logic driver 104 in a kernel mode uses I/O write operations to access a programmable logic element 106, wherein the processing element 102 and the programmable logic element 106 connected through the PCI interface for efficient interrupt delivery.
[0051] It will be apparent to those skilled in the art that the system 100 of the disclosure may be provided using some or all of the mentioned features and components without departing from the scope of the present disclosure. While various embodiments of the present disclosure have been illustrated and described herein, it will be clear that the disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the disclosure, as described in the claims.

ADVANTAGES OF THE PRESENT INVENTION
[0052] The present invention provides a system for accurate time signal delivery in a non-real-time operating system environment using time stamp counter (TSC) internal timers of x86 processing elements for delay calculation in coherence with the hardware timers on the programmable logic element.
[0053] The present invention provides a system that uses hardware timers programmed in the programmable logic element for the effective delivery of interrupts.
[0054] The present invention provides a system that predicts the next interrupt delivery time based on past interrupt time with variable scan numbers. Finally, feeds back the predicted timing interval to the programmable logic element.
[0055] The present invention provides a system that generates fixed time intervals determined by the user application, programmed in low-resolution hardware timers implemented in programmable logic element.
[0056] The present invention provides a system for fixed time interval timeout interrupts which are generated to the processing element over the PCIe interface using message-signaled interrupts.
[0057] The present invention provides a system that achieves high resolution with negligible tolerances.
, Claims:1. A system (100) for implementing high-resolution timer for time-critical application requirements, the system comprising:
an application programming interface (API) residing in a processing element (102) in a user mode operative to provide access to interface parameters; and
a programmable logic driver (104) establishes communication with the API through a communication path and is configured to receive the interface parameters from the API, the programmable logic driver (104) in a kernel mode uses I/O write operations to access a programmable logic element (106), wherein the processing element and the programmable logic element connected through a peripheral component interconnect (PCI) interface for efficient interrupt delivery.
2. The system as claimed in claim 1, wherein the interface parameters pertain to set timer rate, get timer rate, start timer and stop timer.
3. The system as claimed in 1, wherein the processing element (102) running Linux and the programmable logic element (106) is configured for implementing high-resolution hardware timers.
4. The system as claimed in claim 3, wherein the hardware timers are programmed in programmable logic element (106) to interrupt the processing element (102) for every timer expiry.
5. The system as claimed in claim 1, wherein the programmable logic element (106) interrupts the processing element (102) using a multi-vectored message signalled interrupts (MSI).
6. The system as claimed in claim 1, wherein the processing element (102) operable to set rate of timer, start and stop the timers respectively.
7. The system as claimed in claim 1, wherein the number of timers in the programmable logic element (106) is scaled up based on the number of the processing element cores and timer accuracy.
8. The system as claimed in claim 1, wherein the past interrupt interval is used as an input to a feedback mechanism to adjust the programmable logic element timer rate with respect to the processing element ticks for every timer interrupt.
9. The system as claimed in claim 1, wherein the processing element is a central processing unit (CPU) and the programmable logic element is a field programmable gate array (FPGA).
10. A method (400) for implementing a high-resolution timer for time-critical application requirements, the method comprising:
residing (402) an application programming interface (API) in a processing element (102) in a user mode operative to provide access to interface parameters; and
establishing (404), by a programmable logic driver (104), communication with the API through a communication path and configured to receive the interface parameters from the API, the programmable logic driver (104) in a kernel mode uses I/O write operations to access a programmable logic element (106), wherein the processing element and the programmable logic element connected through a PCI interface for efficient interrupt delivery.