TECHNICAL FIELD
The present invention relates to the field of tele-communication networks. More particularly, the present invention relates to the technology of TDMoIP (Time Division Multiplexing over Internet Protocol). The same technological area is synonymously referred with other names such as TDM-IP tunnelling, TDMoPSN, Constant bit rate traffic over IP, Circuit emulation over IP etc.
BACKGROUND
Background description includes information that may be useful in understanding the present invention. Traditionally Telecommunication service providers relied upon circuit switched networks (CSN) for delivering voice based services. The inherent features of CSNs such as Quality of service (QoS), constant delay and reliable connection oriented service enabled delivery of voice services better. Later with the advent of Packet Switched Networks (PSNs), Service Providers able to manage multiple non voice services over a single network. It offered benefits such as integrated service management and administration, better tariff management, ubiquitous availability etc. Though PSNs are touted to offer myriad of services due to it's inherent nature of best effort service it couldn't offer the same amount of QoS that is offered by traditional TDM CSNs for voice services. It also requires service providers to phase out investments in existing TDM CSNs.
For smooth transition between CSNs to PSNs and reap the benefits of IP network, TDMoIP technology is used as a bridge to transport the TDM traffic over IP networks. Various schemes proposed to overcome the challenges such as TDM clock synchronization over IP networks, efficient handling methods for packet duplication or packet loss without any additional protocol overhead etc.
US patent 6,459,708 Bl entitled "Apparatus and Method for providing Tl/El telecommunications trunks over IP Networks" describes an apparatus which acts as a bridge between traditional TDM network & IP packet switched network. The system devised assumes the availability of high bandwidth, traffic engineered UDP/IP/MAC network. The method adds customized App-header overhead of 16 bytes to the raw bits received over TDM interface & encapsulates within UDP/IP/MAC header and transmits over IP network. At receiving side it strips off the UDP/IP/MAC headers and delivers the TDM payload to the

destination TDM interface. In case of network latency it uses idle fill frames to avoid the timing synchronization issues on the TDM interface.
[0005] US patent 5396492 entitled “Method and apparatus for adaptive clock
recovery”, discloses arrangement for deriving a synchronous clock from an ATM (Asynchronous Transfer mode) cell stream. The algorithm uses an open loop adjustments mode without continually adjusting the adaptive line clock frequency based on the monitored deviation of elastic buffer. It uses VCXOs for each interface to adapt the TDM service clock remotely. It aims to solve the problem of synchronous clock recovery over asynchronous ATM network.
[0006] The evolution of digital communication has led to the penetration of more
networks working on packet switched technology as backbone of modern day communication systems. The cost of deployment, performance, multiservice capability, manageability and ease of maintenance of these packet switched networks has made them ubiquitous. While these networks are very efficient for data intensive services, due to their best effort nature, packet delay variation, and loss of packets in the network, they natively cannot support services such as voice, video which are traditionally supported by legacy telecommunications TDM circuits such as PDH, SDH, SONET.
[0007] TDMoPSN (Time Division Multiplexing over PSN) is a technology which
enables circuit emulation of data of constant bit rate nature such as voice, video and any existing data services utilizing TDM networks over packet switched networks such as Ethernet, ATM etc. Circuit Emulation service is a proven approach used to convert the circuit based traffic into packets which are then transported over packet networks. Circuit emulation service leverages the strengths of the packet networks while using the existing legacy infrastructure.
[0008] Hence, there is a need in the art for providing a solution that overcomes the
above mentioned limitations.
OBJECT OF THE PRESENT INVENTION
[0009] Some of the objects of the present disclosure, which at least one embodiment
herein satisfies are as listed herein below.
[0010] It is an object of the present invention to transport constant bit rate traffic such
as TDM, Voice, and Video etc. over an un-reliable Packet Switched Network (PSNs) such as,
but not limited to IP, MPLS networks using bandwidth efficient payload encapsulation

scheme and highly stable adaptive clock recovery mechanism to recover TDM service clock
from asynchronous service clock at remote destination.
[0011] Another object of the present invention is to generate TDM service clock
without any need for PLLs or VCXOs.
[0012] Yet another object of the present invention is to eliminate stability issues that
arise in closed loop clock recovery systems.
[0013] Yet another object of the present invention is to recover the multiple TDM line
interface clocks which eliminates the vulnerability to voltage variations that results in VCXO
based controls without any requirement of multiple PLLs or VCXOs.
[0014] Yet another object of the present invention is to support direct ethernet
encapsulation of RAW TDM, voice bits into UDP/IP/MAC packets without the need for any
adaptation layers such as RTP, AALs etc to save bandwidth.
[0015] Yet another object of the present invention is to provide single byte of
sequence number overhead for UDP/IP/MAC based PSNs using IP header extension concept.
SUMMARY
[0016] The present disclosure relates to the system for transporting constant bit rate
traffic over packet switched networks (PSNs), said system comprising: an encapsulation scheme wherein the raw data bits received from TDM interface are made as packets compatible for transmission over PSNs vice versa in bandwidth efficient manner without any extra adaptation layers overhead such as RTP etc; an adaptive clock recovery method to recover the synchronous TDM service clock from asynchronous PSNs. Said CBR sources comprise, but not limited to, PDH/SDH/PCM etc. Said PSNs comprise, but not limited to, UDP/IP/MAC, MPLS/UDP/IP/MAC etc.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The invention talks about various subsystems using the preferred but not
limited embodiment illustrated in figures 1 to 4. These methods and apparatus may be utilized for IP tunnelling of TDM, voice, video traffic. These and other objects, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings where:

[0018] FIG. 1 illustrates a suggested architecture of the technology for transporting
circuit switched data over packet switched networks (PSNs) in accordance with an
embodiment of the present disclosure.
[0019] FIG. 2 illustrates Block diagram of 102 line interface module shown in FIG 1,
in accordance with an embodiment of the present disclosure.
[0020] FIG. 3 illustrates the block diagram of adaptive clock recovery module, in
accordance with an embodiment of the present disclosure.
[0021] FIG. 4 illustrates TDM data encapsulation into UDP/IP/MAC packet, in
accordance with an embodiment of the present disclosure.
DETAILED DESCRIPTION
[0022] In the following description, numerous specific details are set forth in order to
provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details.
[0023] Figure 1 illustrates a suggested architecture of the technology for transporting
circuit switched data over packet switched networks (PSNs). This technology mainly consists of 102 line interface module, 101 network packet processing module. The line interface module is a computer based logical device consisting necessary hardware in the form of either processors or logic devices & software that enables it to interface to end device nodes 103. These end device interfaces list, though may not be exhaustive, consist of PDH/SDH/PCM whose nature of traffic is that of constant bit rate.
[0024] For example PDH E1 interface works at a constant line rate of 2.048 MHz +/-
50ppm and E3 interface works at a constant line rate of 34.368MHz +/-20ppm rate. These interfaces are necessary to interface any existing TDM base station or Private Branch Exchanges (PBXs). The line interface module will feature necessary data encoders/ decoders appropriate for underlying line interface.
[0025] The line interface module receives data from underlying legacy devices,
decodes/decrypts the information from the frames, segments the received data, buffers into memory and communicates to the network processing module. Similarly it receives the raw data bits from network processing module, buffers it using circular buffer, encrypts/encodes the data and finally transmits over the line using the recovered service clock which is recovered by 207 adaptive clock recovery module.

[0026] The network packet processing module 101 is computer based logic device
that acts as bridge between legacy line interface & underlying PSNs. For example in case of IP PSNs, the raw data bits received from line interface module are encapsulated into UDP/IP/MAC frames and transmitted over IP Networks. Similarly it strips off UDP/IP/MAC header of the packets received from the network and delivers the payload to line interface module. The packet encapsulation method is shown in figure 4.
[0027] The communication between 101 network processing module and 102 line
interface module may consist, but not limited to, high speed SERDES communication, PCI-e, I2C etc. The network interface module also features required physical interfaces to enable it send and receive data from the PSNs. This physical interface may be, but not limited to, electrical Ethernet, optical Ethernet etc. The network module 101 will have methods and intelligence to detect and drop the duplicate packets arrived from the PSNs.
[0028] Ways of duplicate packet consist of checking sequence number of packet with
past received packet’s sequence numbers. The sequence number of one byte may be added as optional header field made available in most of the packet formats illustrated in figure 4. In case of IP networks as shown in figure 4 we use IHL & options fields to add one byte of sequence number. The same sequence number is utilized to drop the old packets arising due to out of order delivery by PSNs.
[0029] By using the optional header feature of IP packet frame 12 bytes overhead of
RTP header may be avoided and similarly there is no need of any AAL’s for synchronization.
[0030] Figure 3 illustrates the block diagram of adaptive clock recovery module 207.
It plays a vital role in synchronous transmission of data received from PSN with variable delay over the end node interface. It aids in synchronizing locally generated TDM service clock with that of remote system. It works by taking receive circular buffer read and write addresses as input and by deriving the instantaneous buffer fill depth. Each packet written into circular buffer will increment the buffer write signal & each packet read out from the buffer increments the buffer read signal. When these read or write addresses reach to maximum they return back to start address and continue to fill.
[0031] The 207 adaptive clock recovery module illustrated in Figure 3 process these
read/write addresses to derive the fill depth of buffer by maintaining internal read/write counters. The difference between write and read counters gives the fill depth indicating number of packets stored in the buffer. Initially the buffer is allowed to fill till a predetermined underflow fill depth.

[0032] Once buffer fill depth reaches to the underflow fill depth constant, data will be
read out with f1 as source clock frequency which is running at lower extreme of allowable
frequency range. As our buffer reading frequency is less, the buffer fill depth tends to
increase. When buffer fill depth reaches to predetermined overflow fill depth the service
clock will be switched to f2 by controlling clock mux selection input.
[0033] Likewise 207 adaptive clock recovery module compares against buffer fill
depth with predetermined underflow/ overflow fill depth constants and accordingly overflow/
underflow signal is generated as input select signal to frequency multiplexer to adjust the
service clock by selecting between f1 and f2.
[0034] If the current fill depth is greater than overflow fill depth constant then
overflow/underflow indictor o/p is asserted. If the current fill depth is less than underflow fill
depth constant then overflow/underflow indicator is de-asserted. If the fill depth is between
the overflow and underflow fill depth then mux select input is unchanged from its previous
state.
[0035] The input to the multiplexer are two temperature compensated clocks running
at two extremes of allowed interface clock frequency. For example in case of E1 interface f1
will be 2.048 MHz -50ppm and f2 will be 2.048 MHz +50ppm. As can be seen here f2>f1. In
this manner the adaptive clock recovery module generates a service clock whose average bit
equal to the underlying interface line rate.
ADVANTAGES OF THE INVENTION
[0036] The present disclosure provides a system and method to improve protocol and
bandwidth efficiency.
[0037] The present disclosure provides a system and method for improving latency by
start reading the buffered data as soon as it reaches underflow fill level instead of waiting till
the buffer gets filled to half.
[0038] The present disclosure provides a system and method where no initial
algorithm convergence latency or loss of initial data for training the algorithm for clock
recovery.

[0039] The method of the present invention may be adapted to varying amounts of
packet delay variation incurred over packet switched network by controlling the underflow/overflow fill level.

We Claim:
1. A system for transporting constant bit rate traffic over packet switched networks
(PSNs), said system comprising:
an encapsulation scheme wherein the raw data bits received from TDM interface are made as packets compatible for transmission over PSNs vice versa in bandwidth efficient manner without any extra adaptation layers overhead such as RTP etc.
an adaptive clock recovery method to recover the synchronous TDM service clock from asynchronous PSNs,
wherein said CBR sources comprise, but not limited to, PDH/SDH/PCM etc. wherein said PSNs comprise, but not limited to, UDP/IP/MAC, MPLS/UDP/IP/MAC etc.
2. The system as claimed in claim 1, wherein said encapsulation scheme adds no extra information apart from 1 byte sequence number added using optional header feature of underlying PSN’s packet format and avoids intermediate RTP/AALs to improve bandwidth efficiency.
3. The system as claimed in claim 1, wherein said encapsulation scheme encapsulates data received from TDM interface into configurable size UDP/IP/MAC frames using necessary end application port number, customized MAC frame type for source identification, source/destination IP and MAC addresses.
4. The system as claimed in claim 1, wherein said encapsulation scheme aids destination system to be able to perform checks for duplicate packet and out of order delivery using sequence number present as part extended IP header, extract the payload and delivers the data to TDM interface in sequence.
5. The system to tunnel the CBR traffic over PSNs as claimed in claim 1, wherein said system comprises an adaptive clock recovery module as part of line interface module.
6. The system as claimed in claim 5, wherein service clock recovered by an adaptive clock recovery module is used to send the data which is received from PSN, on to the TDM interface.
7. The system as claimed in claim 1 wherein said adaptive clock recovery module uses circular buffer read write pointers, uses two crystals running at f1 & f2, which are at two extremes of under CBR interface line rate.

8. The system as claimed in claim 1 wherein said adaptive clock recovery module accepts pre-determined buffer overflow/underflow fill depth constants as additional inputs and compares with derived instantaneous buffer fill depth for generating mux select signal to select any one of the f1,f2 frequencies.