DESC:TECHNICAL FIELD
[0001] The present disclosure relates generally to bus architecture. The disclosure, more particularly, relates to a system for conversion of (advanced micro-controller bus architecture) AMBA signals to display interface signal and method thereof.
BACKGROUND
[0002] Advanced Microprocessor Bus Architecture is an open standard for SoC designs. It is an open-standard that layout the connection and management of the different components or blocks within the Soc.
[0003] US 7475182B2 titled “System-on-a-chip mixed bus architecture” discloses a mixed architecture system on chip is provided by combining a Core Connect system on chip architecture with an AMBA system on chip architecture. To eliminate data transfer and bus error that could occur in the mixed architecture, an additional peripheral bus and bridge are provided to manage communication with AHB (Advanced High Performance Bus) resources. It relates to a system architecture design combining IBM Core connect architecture with the AMBA architecture.
[0004] The existing approach for interacting between a display master and the interconnect implements a Bridge that is tightly coupled to display master. This implementation has 3 FIFOs for Command, Transmit data & Receive data. The APB is part of AMBA protocol family which can interface with other AMBA protocols like AXI (Advanced Extensible Interface) and AHB. Currently, masters which have the capability of creating display interface signals can directly interface with the display master. The host processor which interacts with a display master is based on AMBA APB.
[0005] Thus, there is a need for a system for the conversion of AMBA Advanced Microcontroller Bus Architecture) APB (Advanced Peripheral Bus) bus protocol for interfacing with a display.
SUMMARY OF THE INVENTION
[0006] This summary is provided to disclose a system on chip architecture for the conversion of AMBA (Advanced Microcontroller Bus Architecture) protocol for interfacing with an external display. This summary is neither intended to identify essential features of the present invention nor is it intended for use in determining or limiting the scope of the present invention.
[0007] In an embodiment, the present invention describes a system on chip architecture for the conversion of AMBA (Advanced Microcontroller Bus Architecture) protocol for interfacing with an external display. The system includes a display master configured to receive an input from a display parallel interface and an APB (Advanced Peripheral Bus) interface protocol. The system further includes an APB to display interface bridge configured to convert the APB interface protocol transfer to a display parallel interface transfer, in order to interact with an external display module interface.
[0008] The system of the present invention further includes a display controller configured to transmit an RGB (Red Green Blue) parallel signals towards the display master, wherein the RGB parallel signals are received from a host processor. The display master transmits the RGB parallel signals data and display parallel interface transfer data, serially to the external display module. The system of the present invention further includes a system firmware configured to send commands and receive status and response from the external display module through the display master.
[0009] In another embodiment, the present invention describes a method for conversion of AMBA (Advanced Microcontroller Bus Architecture) protocol for interfacing with an external display. The method comprising the steps of receiving by a display master, input from a display parallel interface, a display controller, and an APB interface protocol. The method further includes converting, by an APB (Advanced Peripheral Bus) to display interface bridge, the APB interface protocol transfer to a display parallel interface transfer, in order to interact with an external display module interface. The method further includes the step of transmitting, by the display controller, an RGB parallel signals received from a host processor towards the display master. The method further includes the step of receiving, by the display master, input from the display controller and the display parallel interface, and further transmitting, by the display master, the received RGB parallel signals data and display parallel interface transfer data, serially to the external display module. The method further includes performing sending and receiving, by system firmware, in the form of commands and status from/to the external display module through the display master.
BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0010] The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and modules.
[0011] Fig. 1 illustrates a block diagram depicting a current existing System on Chip (Soc) architecture, according to an embodiment of the present disclosure (prior art).
[0012] Fig. 2 illustrates a block diagram depicting a System on Chip (SOC) architecture for the conversion of AMBA (Advanced Microcontroller Bus Architecture) protocol, according to an embodiment of the present disclosure.
[0013] Fig. 3 illustrates a functional block diagram of a bridge, according to an embodiment of the present disclosure.
[0014] Fig. 4a illustrates a Transmit flow chart, according to an exemplary implementation of the present disclosure.
[0015] Fig. 4b illustrates a Receive flow chart, according to an exemplary implementation of the present disclosure.
[0016] Fig. 5 illustrates a method for the conversion of AMBA (Advanced Microcontroller Bus Architecture) protocol, according to an exemplary implementation of the present invention.
[0017] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative methods embodying the principles of the present disclosure. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes which may be substantially represented in a computer-readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
Detailed Description
[0018] The various embodiments of the present invention describe a system for conversion of AMBA bus protocol for interfacing with display and method thereof. The novel aspect of the present invention is the development of a bridge that converts AMBA APB signals to display interface signals. A novel implementation is adopted for removing this dependence of tightly coupled APB to display Interface Bridge by moving it external to the display master. This implementation is more generic and can be used with any other system (SOC). Further, in the present invention, the reduction in the number of FIFOs from 3 to 2 (Transmit data & Receive data) is achieved. This also reduces the silicon area of a SOC.
[0019] In the following description, for purpose of explanation, specific details are outlined in order to provide an understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without these details. One skilled in the art will recognize that embodiments of the present disclosure, some of which are described below, may be incorporated into a number of systems.
[0020] However, the systems and methods are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the presently disclosure and are meant to avoid obscuring the presently disclosure.
[0021] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
[0022] In one of the embodiments, the present invention discloses a system on chip architecture for the conversion of AMBA protocol for interfacing with an external display. The system includes a display master configured to receive an input from a display parallel interface, an RGB parallel display controller (not shown in Fig.) or from a display controller, and an APB (Advanced Peripheral Bus) interface protocol. The system further includes an APB to display interface bridge configured to convert the APB interface protocol transfer to a display parallel interface transfer, in order to interact with an external display module interface. The system further includes the display controller configured to transmit the RGB parallel signals towards the display master, wherein the RGB parallel signals are received from a host processor. The display master transmits the RGB parallel signals data and a display parallel interface input data, serially to the external display module. The system of the present invention also includes a system firmware configured to send commands and receive status and response from the external display module through the display master.
[0023] In another embodiment, the present disclosure discloses an interface bridge. The interface bridge includes an address decoder configured to decode received APB interface transfer received from the host processor. The interface bridge further includes configuration registers to configure registers internal to the interface bridge.
[0024] The interface bridge further includes a transmit FIFO (First In First Out) configured to receive and store the decoder data. The interface bridge further includes a master transactor configured to timing protocol conversion between the received APB transfer data (signals) to necessary display timings signals, and to write the necessary information stored in the transmit FIFO and transmit towards the display parallel interface. The interface bridge further includes a receiver FIFO (First In First Out) configured to receive the data from the master transactor and store the updated data, wherein the master transactor receives data from the display master.
[0025] In another embodiment, the present invention discloses the development of a bridge that converts AMBA APB signals to display interface signals.
[0026] In another embodiment, the present invention discloses an implementation that is adopted for removing the dependence of tightly coupled APB to display Interface Bridge by moving it external to the Display master. This implementation is more generic and can be used with any other system (SOC).
[0027] In another embodiment, the present invention discloses a reduction in the number of FIFOs from 3 to 2 (Transmit data and Receive data). This also reduces the silicon area of a SOC.
[0028] In another embodiment, the present invention discloses a system-on-chip (SOC). The SOC includes an APB to display interface bridge for converting the AMBA APB in any SOC to a display based protocol to interact with a display module, wherein this bridge transmits display commands and data and receiving data from the display panel. A display master capable of receiving RGB parallel signals and display parallel signals, and a display controller capable of transmitting RGB parallel signals is disclosed.
[0029] In another embodiment, the present invention discloses a display slave interface that is connected to an APB master interface.
[0030] In another embodiment, the present invention discloses a conversion interface bridge. For example, provided herein is a SOC comprising of a host processor with multiple high speed and peripheral controllers. The interface communication between the processor, various other masters with the peripheral devices is based on AMBA protocol. All of the peripherals are connected to the host processor through the Network Interconnect. One such peripheral controller is a display master that has a mobile display serial interface. The display master receives parallel pixel data from the display controller. The host processor configures the commands through the APB interface, but the display master understands these commands through a specific interface. These necessities the implementation of a bridge that converts the commands through the APB interface to display interface signals.
[0031] In another embodiment of the present invention, SOC includes system firmware to send commands and receive status and response through the display master is disclosed. The system firmware load images on the display module through the display master.
[0032] In another embodiment, the present invention discloses that the SOC command is sent to refresh the screen with a reduced size or fill up with a partial frame buffer so that the serial interface to host processor can be shut down to reduce the power consumption.
[0033] In another embodiment, the present invention discloses an implementation of an address decoder for command/parameter/data transfer from the host processor.
[0034] In another embodiment, the present invention discloses a design that includes implementation of a Transmit and Receive FIFO, wherein the number of FIFO's is reduced from the existing system 3 to 2. The design includes implementation of a transmit FIFO (First In First Out) for command/parameter/data with necessary identifiers to differentiate command and data with support for various bit width. Storing the values comprises setting one or more data bits to a pre-determined value.
[0035] In another embodiment, the present invention discloses an implementation of a register interface control and information for the bridge along with the status.
[0036] In another embodiment, the present invention discloses an implementation of a Receive FIFO to receive the data sent from the display module.
[0037] In another embodiment, the present invention discloses an implementation of a master transactor which is used for timing protocol conversion between the APB signals to necessary display timing signals. The master transactor is configured to stall new transactions during an ongoing transfer.
[0038] In another embodiment, the present invention discloses a design consists of the implementation of a write FSM (Finite State machine) for sending commands and data to the display module. The design defined consists of the implementation of a read FSM (Finite State Machine) for receiving the status and data from the display module. The design is generic in nature and can be used in any system based on AMBA based protocol.
[0039] Fig. 1 illustrates a block diagram depicting a current existing System on Chip (Soc) architecture (prior art), according to an embodiment of the present disclosure. In Fig. 1, the SOC includes a host processor (100), and various other masters connected to various subsystems though a network interconnect. In the system, the APB data to interact with the display interface is taken care by the APB 2 display bridge (105) which is tightly coupled to the display master (101).
[0040] Fig. 2 illustrates a block diagram depicting a System on Chip (SOC) architecture, according to an embodiment of the present invention.
[0041] The system includes a host processor (202), a network interconnect (204), a display controller (206), an APB interface protocol (208), an APB to display interface bridge (210), a display master (216), an RGB parallel display controller (not shown in Fig.) , RGB parallel signals (218), display parallel interface (212), and an external display module (220).
[0042] The host processor (202), and various other masters connected to various subsystems though a network interconnect (204). The host processor (202) can separately perform controlling the subsystems and transferring data using the Advanced Microcontroller Bus Architecture (AMBA) protocol bus architecture. The APB to display interface bridge (210) allows the processor (202) to separately access the display master (216) by converting the APB transfer to a display parallel interface (212) transfer.
[0043] The APB to display interface bridge (210) convert the received APB interface protocol (208) transfer to a display parallel interface transfer (212) to interact with a, external display module interface (220). The APB signals are obtained from the host processor (202) through the network interface (204). A display controller (206) configured to transmit the RGB parallel signals (218) towards the display master (216). The said RGB parallel signals (218) are received from the host processor (202) through AXI. The said display master (216) further sends the received RGB parallel signals (218) data and the display parallel interface (212) data serially to the external display module (220).
[0044] The transfer of commands to the mobile display serial interface is only possible through a mobile display interface. The software running on the host processor (202) shall configure the mode, Read/write transfer, and Low speed/High-speed transfer through the APB interface. The said interface bridge (210) handles the write and read path between the APB master and the display master (216).
[0045] The APB to display interface bridge (210) is connected to the APB master interface protocol.
[0046] Fig. 3 illustrates a functional block diagram of an interface bridge, according to an embodiment of the present disclosure.
[0047] In Fig. 3, the interface bridge (210) of the present invention includes an address decoder (300), a transmit FIFO (First In First Out) (302), a configuration registers (304), master transactor (308), a status register (not shown in Fig.), a receive FIFO (First In First Out) (310), and a multiplexer.
[0048] The address decoder (300) decodes the received APB interface transfer received from the host processor (202) through the APB bus, and pass to successive logic. The APB transfer contains command/data/parameter as control signals. This decoded data is further sent towards a transmit FIFO (302) through the APB bus. The transmit FIFO (302) is configured to receive and store the decoder data. These commands and data are stored with identifiers to differentiate between command and the data, wherein the identifiers are written on the transmit FIFO (302). Once the complete command and related information are available in the transmit FIFO (302), the display master (216) can read and transfer the information adhering to the display interface timing protocol.
[0049] In the case of a read request, the valid data from the display module is available on data input. The valid data from the host controller (202) is indicated by the assertion of the data available signal. The data from the external display module (220) is made available in the receive FIFO (310) based on the data received, the host processor (202) can read the values.
[0050] The configuration registers (304) to configure registers internal to the interface bridge (210).
[0051] The Master Transactor (308) is the heart of the bridge (210) which implements FSM logic to drive the write/read transactions. The master transactor (308) configured for timing protocol conversion between the received APB transfer data (signals) to necessary display timings signals, and to read/write the necessary information stored in the transmit FIFO (302) and transmit towards the display parallel interface (212);
[0052] The type of transfer (write/read) and the mode is configured by the host processor (202). Once the host processor (202) transfers the last information byte, the transactor (308) starts reading the information from the transmit FIFO (302). The controls are toggled according to the timing specification mentioned for display interface protocol. The host processor (202) places the next commands once the current transfer finishes. If there is read request from the host processor (202), FSM jumps to read sequence, where the necessary signals are toggled as per display interface protocol and the received data is stored in the receive FIFO (310) from which the values are read by the host processor (202). The commands/parameters/data from the host processor are transferred to the external display module (220) through the display parallel interface (212).
[0053] The write FSM transaction is used to send commands and data to the external display module (220), and the read FSM transaction is used to receive the status and data from the external display module (220).
[0054] The receive FIFO (310) of the present invention receives the data from the master transactor (308) and store the updated data. The master transactor (308) receives data from the display parallel interface (212).
[0055] Fig. 4a illustrates a Transmit FIFO flow chart, according to an exemplary implementation of the present invention.
[0056] The commands/parameters/data from the host processor (202) are transferred to peripheral adhering to display timing protocol. The toggling of the display read/write control signals for reading/writing transfer is at least 2 display clock cycles. The detailed transfer sequence is explained with state transitions as below.
[0057] Transmit Idle (402): Initially, all Display Master Control signals are driven HIGH. Once the host processor transfers complete information, it sets the host write last bit in the control register. If the host write last bit is '1' and write FIFO is empty state changes to check display bus interface stall (404) status. For generic read transfer with zero parameters, there is no command phase. It expects the response from peripheral, so state changes to Receive Idle (406).
[0058] Check display bus interface stall (404): Before initiating the transfer on display bus interface, the display bus interface stall signal is monitored from the host controller. If the display bus interface stall is set, which indicates the host controller is not ready to receive the data. Chip select should be de-asserted and other controls are driven HIGH on the display bus interface. Once the display bus interface stall goes low, initiate the transfer sequence by reading Transmit FIFO (302).
[0059] Read Transmit FIFO (302): Assert read control to get the command/data information from FIFO. This read control is a pulse of one display bus interface clock to read one information at a time.
[0060] Check command/data (410): The read control to FIFO is cleared. The read data from FIFO is checked for the 16th bit, if the bit is '0', then its data information else it is command information. Accordingly, the state transition happens to initiate the transfer.
[0061] Command/Data Transmit 412/414: For command transfer to initiate, chip select is asserted. Controls of display bus interface chip select, and display bus interface write are driven ‘low’. The command to be transmitted is placed on the display bus interface data outline. Always the information to be transmitted is launched on the falling edge of the display bus interface write. Bus busy status is set.
[0062] Delay 1 (416): display bus interface write should be held low for at least two display bus interface clock cycles. Inserting a clock delay.
[0063] Toggle display bus interface write (418): After 2 display bus interface clock delay, display bus interface write is set to ‘1’, so that display bus interface slave can sample the data which is transmitted. After asserting the display bus interface write to ‘1’, finite state machine should wait for 2 display bus interface clock cycles before it gets toggled.
[0064] Delay 2 (420): Inserting a clock delay
[0065] Transmit Done (422): FSM jumps to display bus interface stall 402 state if some more information is available in transmit FIFO. If all the information is transmitted and transmit FIFO is empty transmit done signal is asserted. If the command is of reading request, FSM jumps to Receive Idle 424 state.
[0066] Fig. 4 b illustrates a receiver FIFO flow chart, according to an exemplary implementation of the present disclosure.
[0067] Receive Idle (402): To initiate the read sequence, whether receive FIFO (310) is full and display bus interface data available status from the slave is monitored. If FIFO is full and some more data is expected from the slave, display bus interface read is not toggled, instead, it’s held HIGH. By doing this, slave transfer is stopped. If FIFO is empty and still valid data expected from a slave, the display bus interface read is toggled. On bus interface data available de-assertion, which means no valid data available from the slave, FSM switches to Transmit Idle (402) state to transmit the fresh commands when available. Bus busy status is asserted to indicate transfer is ongoing.
[0068] Drive Receive Control (502): To initiate the read transfer, chip select is asserted, display bus interface chip select is set to ‘1’, and display bus interface read is set to ‘0’. The slave will launch the read data on falling edge of the display bus interface read. The toggling of the display bus interface read holds the same as of display bus interface write.
[0069] Delay 3 (504): Insert a clock delay
[0070] Toggle display bus interface read (506): Drive display bus interface read to ‘1’. Master should sample the read response on the rising edge of the display bus interface read. Finite State Machine should wait for at least 2 display bus interface clock.
[0071] Delay 4 (508): Insert a clock delay and jump to Receive Idle 406 state.
[0072] The host write last bit is hardware cleared. Once transmit done is set, host write last gets cleared and it’s asserted when host configures it.
[0073] Fig. 5 illustrates a method for the conversion of AMBA (Advanced Microcontroller Bus Architecture) protocol, according to an exemplary implementation of the present invention.
[0074] Referring now to Fig. 5 which illustrates a flowchart (600) for the conversion of AMBA (Advanced Microcontroller Bus Architecture) protocol, according to an exemplary implementation of the present invention. The flow chart (600) of Fig. 5 is explained below with reference to Fig. 2 as described above.
[0075] At step 602, receiving, by a display master (218), input from a display parallel interface (212), a display controller (206), and an APB (Advanced Peripheral Bus) interface protocol (208).
[0076] At step 604, converting, by an APB to display interface bridge (210), the APB interface protocol transfer to a display parallel interface transfer, in order to interact with an external display module interface (220).
[0077] At step 606, transmitting, by the display controller (206), RGB parallel signals (218) received from a host processor (202) towards the display master (216).
[0078] At step 608, receiving, by the display master (218), input data from the display controller (206) and the display parallel interface (212).
[0079] At step 610, transmitting, by the display master (218), the RGB parallel signals (218) data and display parallel interface input data, serially to the external display module (220).
[0080] At step 612, performing sending and receiving, by system firmware, in the form of commands and status from the external display module (220) through the display master (216).
[0081] The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the substance of the invention may occur to a person skilled in the art, the invention should be construed to include everything within the scope of the invention.

,CLAIMS:
1. A system on chip architecture for the conversion of AMBA (Advanced Microcontroller Bus Architecture) protocol for interfacing with an external display comprising:
a display master (216) configured to receive an input from a display parallel interface (212) and an APB (Advanced Peripheral Bus) interface protocol (208);
an APB to display interface bridge (210) configured to convert the APB interface protocol transfer to a display parallel interface transfer (212), in order to interact with an external display module interface (220);
a display controller (206) configured to transmit an RGB (Red Green Blue) parallel signals (218) towards the display master (216), wherein the RGB parallel signals (218) are received from a host processor (202); and
a system firmware configured to send commands and receive status and response from the external display module (220) through the display master (216);
wherein the RGB parallel signals (218) data and the display parallel interface transfer data are sent serially to the external display module (220).

2. The system on chip architecture as claimed in claim 1, wherein the interface bridge (210) comprises:
an address decoder (300) configured to decode the APB interface transfer data received from the host processor (202);
a configuration registers (304) to configure registers internal to the interface bridge (210);
a transmit FIFO (First In First Out) (302) configured to receive and store the decoder data;
a master transactor (308) configured
for timing protocol conversion between the received APB transfer data (signals) to necessary display timings signals, and
to read/write the necessary information stored in the transmit FIFO (302) and transmit towards the display parallel interface (212); and
a receive FIFO (First In First Out) (310) configured to receive the data from the master transactor (308) and store the updated data, wherein the master transactor (308) receives data from the display parallel interface (212).
3. The system on chip architecture as claimed in claim 2, wherein the APB transfer contains command/data/parameter.
4. The system on chip architecture as claimed in claim 2, wherein the commands and data are stored with identifiers to differentiate between command and the data, wherein the identifiers are written on the transmit FIFO (302).
5. The system on chip architecture as claimed in claim 1, wherein the APB to display interface bridge (210) is connected to the APB master interface protocol (208).
6. The system on chip architecture as claimed in claim 1, wherein the RGB parallel signals (218) data and display parallel interface transfer data are sent serially to the external display module (220) by the display master (216).
7. The system on chip architecture as claimed in claim1, wherein the system firmware load the images on the external display module (220) through the display master (216).
8. The system on chip architecture as claimed in claim 2, wherein the total number of the FIFO’s present on the interface bridge (210) is 2.
9. The system on chip architecture as claimed in claim 2, wherein the master transactor (308) implements FSM (Finite State Machine) logic to drive read/write transactions, wherein the FSM logic jumps from reading to writing or vice-versa as per the display interface protocol requirement.
10. The system on chip architecture as claimed in claim 8, wherein the write FSM transaction is to send commands and data to the external display module (220).
11. The system on chip architecture as claimed in claim 8, wherein the read FSM transaction is to receive the status and data from the external display module (220).
12. The system on chip architecture as claimed in claim 1, wherein the stored decoder values of the transmit FIFO (302) comprises of setting one or more data bits to a pre-determined value.
13. A method for conversion of AMBA (Advanced Microcontroller Bus Architecture) protocol for interfacing with an external display comprising:
receiving, by a display master (216), input from a display parallel interface (212), a display controller (206), and an APB (Advanced Peripheral Bus) interface protocol (208);
converting, by an APB to display interface bridge (210), the APB interface protocol transfer to a display parallel interface transfer, in order to interact with an external display module interface (220);
transmitting, by the display controller (206), an RGB parallel signals (218) received from a host processor (202) towards the display master (216);
receiving, by the display master (218), input data from the display controller (206) and the display parallel interface (212), and
transmitting, by the display master (216), the received RGB parallel signals (218) data and the received display parallel interface transfer data, serially to the external display module (220); and
performing sending and receiving, by system firmware, in form of commands and status from the external display module (220) through the display master (216).
14. The method as claimed in claim 10 further comprising:
decoding, by an address decoder (300), the received APB (Advanced Peripheral Bus) interface transfer received from the host processor (202);
configuring, by a configuration registers (304), a registers internal to the interface bridge (210);
receiving, by a transmit FIFO (First In First Out) (302), the decoder data for storing;
performing, by a master transactor (308), a timing protocol conversion between the received APB transfer data (signals) to necessary display timings signals;
reading/writing, by the master transactor (308), the necessary information stored in the transmit FIFO (302), and
transmit the necessary information towards the display parallel interface (212); and
receiving, by a receive FIFO (First In First Out) (310), the data from the master transactor (308) and store the updated data.