F O R M 2

THE PATENTS ACT, 1970
(39 of 1970)
&
The Patents Rules, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)

1. Title of the invention: SYSTEM FOR DETECTING SERIES ARCING IN POWER LINES AND METHOD THEREOF

2. Applicant(s):

(a) NAME : LARSEN & TOUBRO LIMITED
(b) NATIONALITY : An Indian Company
(c) ADDRESS : L & T House, Ballard Estate, Mumbai 400 001, State of
Maharashtra, India

3. PREAMBLE TO THE DESCRIPTION

The following specification particularly describes the invention and the manner in which it is to be performed:

TECHNICAL FIELD OF THE INVENTION

This invention relates generally to a system and method for arc detection and more particularly to a system and method for series arc detection in power line by separately analyzing the plurality of positive and negative half cycles of current using a mixed signal processing system.

BACKGROUND AND THE PRIOR ART

An electric arc is a condition of luminous and hot discharge of electricity in air or gas existing between two conductors. It can be broadly categorized as the one where the fault occurs in series with the load and where the fault occurs parallel to the load. The latter also known as parallel arcing is a condition in which the fault occurs between line and neutral or line to line, offering low impedance path and as a result the load is cut off from the system. The impedance now available is only by the conductor and the arc itself resulting in abnormal rise in current. Series arcing on the other hand is a condition in which the fault occurs in series with the load. This fault can be due to loose connections, physical damage to the cable etc.

Series arcing is insidious because unlike parallel arcing where fault current rises abnormally, the current is limited by the load impedance and impedance offered by the arc and the condition goes undetected as the conventional circuit breakers cannot detect it as overload or as short circuit. Series arcs if not interrupted can lead to overheating of the cable and can subsequently lead to an electrical fire.

Thus to mitigate this threat there is a need for a method to reliably detect a series arc and interrupt the circuit in which this condition has developed.

The method of detection of series arc relies on the randomness of the arc waveform. When the electric circuit is free from any fault, the load will maintain a pattern such that the measures like RMS, time averages or even current peaks do not have a cycle to cycle variation. This regularity in the current waveform maintained by the load is disrupted when a series arc occurs in the system. The challenge is to discriminate between normal arcing (during switching operations, arcing at motor brush etc) from an arc fault condition. The situation is further complicated because of the increased presence of modern power electronic loads which produce current waveforms with harmonics and can be mistaken for arc fault current waveforms.

US7633729 claims to detect series arc by adding the absolute values of positive and negative half cycles of current to form a current level and subtracting the same from the previous current level. On the contrary our invention refers to an arc detection scheme through a separate analysis of the measured positive and negative half cycles of current making it more sensitive in arc detection. Unlike the US Patent, the measured positive and negative half cycles of current in our disclosure are obtained by charging one or more capacitors of an integrator circuit. The above US Patent is ambiguous as far as the method of measurement of the positive and negative half cycles of current is concerned.

US5839092 detects the series arc by measuring the peak of the half cycle of the current waveform and determines the number of changes in slope at the peak between the half cycles. It also normalizes each of the current samples and measures the waveform shape changes. On the other hand, our invention is based on the comparison of the half cycles of current obtained by charging one or more capacitors through integrator and also through half cycle current width comparison.

US5561605 samples one cycle of the current waveform and subtracts the same from the samples of the preceding cycle of current waveform and in case the difference crosses a threshold limit and the condition persists, circuit is isolated. On the other hand, our invention is based on the comparison of the half cycles of current obtained by charging one or more capacitors through integrator and also through half cycle current width comparison.

US2007/0133134 A1 measures the change in the current peak in the positive and negative half cycle within a specific time period for parallel arc detection. For series arc detection the patent uses a software integrated current signal which is compared against a predetermined threshold value. The arc detection algorithm progress when the alternate samples exceed upper and lower threshold values. In our invention there are separate hardware circuits for integrating positive and negative half cycle of the load waveform. The zero cross detector based integrator eliminates the problem of inaccuracies arising due to variable frequency and low load current sensing problems.

Every arc has a characteristic behavior and the present disclosure therefore provides a low current arc detection logic that recognizes the pattern and isolates the circuit thereby eliminating the hazardous condition created by the arc. It provides a new concept of detecting series arcing. The invention includes integrator that is used to charge one or more capacitors in positive and negative half of current cycles respectively. The measured positive and negative current cycles are compared with at least one reference signal. The reference signal can be one or more preceding cycles. Present invention also disclose a half cycle width measurement logic that measures the width of the signal and compares the same with at least one reference signal in order to improve the sensitivity of the arc detection logic. A trip signal is issued if the tested current signal crosses a predetermined value as mentioned in the decision logic.

OBJECTS OF THE INVENTION

A basic object of the present invention is to overcome the disadvantages/drawbacks of the known art.

Another object of the present invention is to provide an Arc fault circuit interrupter for series arc detection in power line.

Another object of the present invention is to eliminate the inaccuracies arising due to variable frequency and low load current sensing problems.

Yet another object of the present invention is to improve the sensitivity of the arc detection logic so as to detect low current series arc fault.

These and other advantages of the present invention will become readily apparent from the following detailed description read in conjunction with the accompanying drawings.

SUMMARY OF THE INVENTION

There is provided an Arc fault circuit interrupter for series arc detection in power line.

According to one embodiment of the present invention, there is provided an arrangement to eliminate the inaccuracies arising due to variable frequency and low load current sensing problems.

Yet other embodiment of the present invention improves the sensitivity of the arc detection logic so as to detect low current series arc fault.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

Fig 1 illustrates the series arc detection and protection scheme.

Fig 2 illustrates the block diagram of the analog stage of the system.

Fig 3 illustrates the algorithm for series arc detection.

DETAILED DESCRIPTION OF THE ACCOMPANYING DRAWINGS

The following drawings are illustrative of particular examples for enabling methods of the present invention, are descriptive of some of the methods, and are not intended to limit the scope of the invention. The drawings are not to scale (unless so stated) and are intended for use in conjunction with the explanations in the following detailed description.

Reference is first invited to Fig 1 where the series arc detection and protection scheme is shown. It shows arrangement of source, circuit breaker, current sensor, analog interface, control unit, load.

FIG 2 shows the block diagram of the analog stage of the system according to an embodiment of this invention. It shows the power line 1 that runs from the source to the load.

FIG 3 shows the algorithm for series arc detection according to an embodiment of this invention. The outputs from integrators of the analog stage are connected to the ADC of the microcontroller. The ZCD output is also fed to the microcontroller.

DETAILED DESCRIPTION OF THE INVENTION
A series arc detection and protection scheme is shown in the figure 1. The source and load is connected via power line 7 through a circuit breaker 2. A current sensor 3 having a high bandwidth senses the load current flowing through the power line 7. The signal is fed to an analog processing circuit 4 which produces an output optimum for the control unit 5 to analyze the wave pattern. The control unit 5 is a microcontroller based system and contains peripherals like ADCs and timers. The arc detection algorithm is executed by the microcontroller in real time and upon detection of arc fault the trip signal is issued to the circuit breaker 2.

The most common parameter of measurement of alternating current is the RMS value of the waveform. RMS calculation is a math intensive process demanding high end DSPs. In the event of series arc, high frequency components as well as transients may be present in load current. A normal DSP system will have to operate at a sampling frequency much higher than the system frequency to properly acquire the waveform. An analog processing stage that can integrate and provide the magnitude of the sensed waveform at the end of each cycle will greatly reduce the processing requirements of the digital stage. Also the analog processing stage can account for the current spikes and transients that can occur in the arcing state thus reducing loss of information due to digitization.

A method for such an analogue processing of data is proposed in the present invention. The proposed analog processing stage has two parts. The first stage consists of two half wave precision rectifiers which produces separate outputs for the positive and negative half cycles of the sensed signal. These signals are then fed to two analog integrator circuits which form the second stage of the system. The integrator capacitor is ground referenced so that resetting the same is easier. The input signal is also fed to a zero cross detector. The microcontroller receives the zero cross detector output and based on the type of edge (rising or falling) the corresponding integrator value is sampled. Once the ADC conversion is completed the capacitor that holds the integrated value has to be discharged. The circuit has one half cycle time of the current signal to discharge the capacitor. This is the specific advantage of using two independent circuits for positive and negative half cycles. The rectifier output stays at zero while the capacitor is getting reset.

Figure 2 is the block diagram of the analog stage of the system. The power line 1 runs from the source to the load. The current sensor 2 can be an open loop current sensor (ferrite core CT or open loop Hall Effect current sensor) or a simple current sense resistor in series with the power line. The output of the current sensor 2 is fed to the precision rectifier 3 circuits. The half rectified waveforms are fed to the integrator 4. The integrator produces an output proportional to for half cycle period of the waveform. The zero cross detector (ZCD) 5 connected to the current sensor helps the controller to synchronize with system current and to read and reset the integrator.

The algorithm for series arc detection is given in figure 3. The arc detection algorithm is closely associated with the analog interface. The outputs from integrators of the analog stage are connected to the ADC of the microcontroller. The ZCD output is also fed to the microcontroller. On a non inverting logic the rising edge of the ZCD indicates the end of a positive half cycle, which means the output of the positive integrator, is ready to be read. For the negative half cycle the same logic follows. The read values are stored in a positive half cycle buffer and negative half cycle buffer of predefined size. Once the data is stored the integrator is reset and is ready for the next half cycle integration. Once the buffer is filled, each data sample is compared with its adjacent data sample. If the value (difference) exceeds the set threshold, a flag variable is incremented. The flag variable is a direct indication of the number of disturbances in a limited period. Once the entire buffer is analyzed in this fashion the flag variable value is compared with a threshold value. If the flag variable value is greater than the threshold, the condition is considered as a persistent series arc condition and a trip signal is issued. The sensitivity to series arc detection is improved by observing the width of the signal which becomes active when no event indication is available from the zero cross detector for period greater than the reference period.
Although the embodiments herein are described with various specific embodiments, it will be obvious for a person skilled in the art to practice the embodiments herein with modifications. However, all such modifications are deemed to be within the scope of the claims.
It is also to be understood that the following claims are intended to cover all of the generic and specific features of the embodiments described herein and all the statements of the scope of the embodiments which as a matter of language might be said to fall there between.

WE CLAIM:

1. A system for detecting series arcing in power lines, said system comprising:
a source and a load, said load connected to the source;
sensor means having high band width sensing load current;
analog interfacing unit in communication with said sensor means receiving said load current from said sensor means whereby said load current provides an optimum output signal to be fed to a control unit for detection of the arc, wherein said analog interfacing unit comprising plurality of rectifiers defining first stage of series arc detection, said rectifiers producing outputs which are fed to plurality of integrator circuits connected to said rectifiers, said integrator circuits defining second stage of series arc detection, wherein said integrator circuits produce outputs proportional to said outputs from the rectifiers.

2. System as claimed in claim 1 wherein said sensor means is an open loop current sensor.

3. System as claimed in claim 1 wherein said sensor means is optionally a simple current sense resistor.

4. System as claimed in claim 1 wherein said rectifier is a half wave precision rectifier.

5. System as claimed in claim 1 wherein said integrator circuit comprising integrator capacitor.

6. System as claimed in claim 1 further comprising a zero cross detector means for indicating starting and end points of positive and negative half cycles.

7. System as claimed in claim 1 wherein said control unit is a microcontroller based system for execution of an arc detection algorithm for detection of arcs.

8. System as claimed in claim 1 wherein said control unit issues trip signal to the circuit breaker.

9. A method for detecting series arcing in power lines, comprising the steps of:
sensing load current using sensor means having high band width from the power line connecting a source and a load;
said load current from said sensor means fed to analog interfacing unit in communication with said sensor means whereby said load current provides an optimum output signal to be further fed to a control unit for detection of the arc wherein said analog interfacing unit comprising plurality of rectifiers, output from said rectifiers fed to plurality of integrator circuits connected to said rectifiers, said integrator circuit producing output proportional to said outputs from the rectifier.

10. The method for detecting series arcing in power lines as claimed in claim 1 wherein starting and end points of positive and negative half cycles are indicated by a zero cross detector means.

11. The method for detecting series arcing in power lines as claimed in claim 1 comprising the further step of detecting arcs by executing an arc detection algorithm using microcontroller based system present in the control unit.

12. The method for detecting series arcing in power lines as claimed in claim 1 comprising the further step of issuing the trip signal by said control unit to the circuit breaker.

13. A system for use in detecting series arcing in power lines as herein substantially described and illustrated with reference to the accompanying drawings.

14. A method for detecting series arcing in power lines as herein substantially described and illustrated with reference to the accompanying drawings.

Dated this 28th day of December 2011

Abhishek Sen
Of S. Majumdar & Co.
(Applicant’s Agent)