Field of the Invention
The instant invention relates to a system and method for generating pulse width modulated signal having variable duty cycle resolution.
Background of the Invention
Pulse width modulation (PWM) is a commonly used technique for generating precisely timed, repetitive digital waveforms. Resolution of a PWM waveform plays an important role in the quality of output generated. The granularity or resolution of the device output states depends upon the resolution of the PWM output used to control the device. For a given range of output states, higher resolution in the PWM translates into higher resolution of the device being controlled thereby. Resolution enhancements have typically relied upon hardware alterations on the controller side to provide for more PWM states at the output. However, such hardware based approaches are typically fraught with significant cost penalties and use of non-standardized components.
General-purpose microcontrollers are used for generation of Pulse Width Modulation (PWM) waveform for different applications. Sine wave generation is one of the most useful applications where the PWM function of timers can be used. Sine wave resolution can be improved by improving PWM duty cycle resolution. UPS is one of most useful applications where the sine wave resolution is important. Also in some applications if AC Mains frequency changes to a large extent, it may cause temporary or permanent damage to the operating device. During the change in AC Mains frequency, it is necessary to track the same.
While any variety of digital waveforms can be generated by periodically writing to the various ports of digital ICs, using timer output capture and the like, these all require direct CPU time for each output pulse. A great advantage of PWM is that once the registers are set up and enabled, the PWM waveforms are generated without any CPU overhead, so valuable CPU time can be utilized for other tasks.
However there are certain drawbacks to the same. Resolution of the pulse width modulated signal, which must be significantly higher than the input frequency, typically does not approach that of the input itself. A further problem that reduces available PWM accuracy and resolution is associated with timer interrupt latency inherent in current microprocessor-based control schemes. That is, transitions of the pulse width modulated signal from high to low and low to high are handled by a pulse width timer interrupt routine in software. Depending upon the instructions being executed when a pulse width timer interrupt occurs, four to seven microseconds can elapse before the software interrupt routine is executed. There is thus a quasi-random timing error of up to three microseconds, which can be viewed as noise on the PWM signal that adversely affects system performance, particularly in high response systems.
A USPN 5023535 entitled "high resolution pulse width modulation" provides high-resolution pulse width modulation waveform using software, but the change in high time of pulse width modulated waveform is in multiple (s) of microprocessor/microcontroller clock period.
It is therefore required to invent a system that would address the foregoing problems in the art and provide resolution up to a fraction of the time period of Central Processing Unit (Tcpu)- The present technique makes use of only a minimal hardware thus provides a very cost effective solution. There is no computation algorithm required, which makes this efficient without any software overhead.
Objects and Summary of the Invention
To obviate the aforesaid drawbacks, it is an object of the invention to provide a system and method with improved resolution of the pulse width modulated signal.
Yet another object of the invention is to provide PWM waveform whose resolution can be a fraction of TCPU according to the application requirement.
To achieve the aforesaid objects, the instant invention provides a system for generating Pulse Width Modulated signal having variable duty cycle resolution comprising: a microcontroller for generating a master clock output;
a divide by W counter having its input connected to said master clock output of
said microcontroller providing a divided clock output;
a delay circuit having its input connected to the output of said divide by W
counter for introducing a delay in said divided clock output;
a flip flop having its data input connected to a second output of said
microcontroller and its clock being connected to the output of said delay circuit
for shifting said second output of said microcontroller; and
a logic gate receiving the outputs of said flip flop and said second output of said
microcontroller for providing an improved resolution PWM waveform.
Said delay circuit includes a multiplier block that feedbacks the signal M number of times to introduce desired delay.
Said system provides a PWM waveform with resolution up to a fraction of the time period of Central Processing Unit (TCPU)-
Said flip-flop is a D - flip-flop.
Said logic gate is an OR gate.
Said second signal is a pulse width modulated signal.
A method for generating Pulse Width Modulated signal having variable duty cycle resolution
comprising the steps of:
generating master clock output;
providing a divided master clock output;
delaying said divided master clock output;
shifting pulse width modulated signal using said delayed signal as clock; and
performing a logic operation on said pulse width modulated signal and shifted
pulse width modulated signal to obtain the improved resolution PWM waveform.
Said method provides a PWM waveform with resolution up to a fraction of the time period of Central Processing Unit (TCPU)-
Said logic operation is OR operation.
Brief Description of the Accompanying Drawings
The invention will now be described with reference to the accompanying drawings.
Figure 1 relates to the block diagram of a PWM system in accordance with the instant invention. Figure 2 illustrates the waveforms of PWM in accordance with the instant invention. Figure 3 shows the flowchart of the steps of the method in accordance with the invention.
Detailed Description of the Invention
In relation to the drawings, exemplary embodiments of the present invention are described in the following detailed description. However, it will be apparent to a person skilled in the art that numerous other equivalent embodiments or ways of practicing the present invention exist.
Resolution of a PWM output is the granularity with which the duty cycle can be modulated. The PWM duty cycle resolution determines the amount of precision with which the duty cycle can be changed. For example, a 10-bit resolution allows 1024 possible values for the duty cycle where an 8-bit resolution only allows 256 values. The PWM duty cycle resolution is defined as: Resolution = 1/number of divisions available in one PWM cycle
If the X-bit Auto Reload Timer (ART) is used, the resolution of PWM without using the novel apparatus will be:
Resolution = 1/ (2X - Auto-Reload Value)
Where X represents the number of bits.
It will be seen by the foregoing description that by using this invention, if delay is 6(t), and FCOUNTER = FCPU/W and TCPU = N*8(t), the resolution will be
Resolution = 1/ ((2X - Auto-Reload Value)*W*N)
Where FCOUNTER is the frequency of the divide by W counter,
FCPU is the frequency of the microcontroller,
W is the count of the divide by W counter,
TCPU is the time period of the microcontroller,
N is the ratio of time period of CPU to the total delay.
If 6(t) approaches 0, N will approach infinity and resolution will also approach zero. But using the present invention, change in high time of pulse width modulated waveform is in multiple of 8(t), where 6(t) is the delay provided by the delay circuit, which may be tending to 0. Thus, by using this invention, one can get continuous change in high time of pulse width modulated waveform. Thus the resolution is ideally improved to its highest value, which is 0.
Figure 1 shows the block diagram of the present invention. It consists of a microcontroller 1 the outputs of which are connected to the inputs of a divide by W counter 2, a flip-flop 5 and feedback path 4 of delay circuit respectively. The output of the divide by W counter 2 is connected to the delay circuit 3, which in turn is connected to a flip-flop 5. The output of the flip-flop 5 is further connected to one of the inputs of the OR gate 6 while the other input of OR gate 6 is connected to one of the outputs of the microcontroller 1.
A common power supply of 5V can be used for driving all the external components as well as the microcontroller 1. The microcontroller 1 produces the Master Clock Out (MCO) and Pulse Width Modulator (PWM) out which are synchronised at the edges. Further the microcontroller 1 generates the control signal for controlling the delay in MCO out signal depending upon user application. This control signal manages the delay produced in the delay circuit 3 according to the user application.
The value of W in the divide by W counter 2 is a fixed value for a particular configuration of microcontroller 1 and the delay circuit 3. The low frequency output X of the divide by W counter 2 is delayed M times by the delay circuit 3 and fed to the clock of the flip-flop 5. The flip-flop 5 outputs a signal B that is shifted PWM signal A. The OR gate 6 performs ORing between the shifted PWM signal B and normal PWM out A and provides the PWM out signal with changed duty cycle by M*8(f)/TpwM- If M varies from 1 to N*W, the improvement in resolution will be N*W times. It means:
TCOUNTER = Tx = N,*8(t) Where N1 = N*W
TCPU = N*δ(t)
An embodiment of the invention will now be described using 8-bit PWMART timer for PWM duty cycle resolution computation. However, the invention is not restricted to the same. The parameters in case of an 8-bit PWMART timer are as follows:
fcpu is 8MHz
fcouNTER is 4MHz
Auto-Reload value is 00h,
duty cycle register value is 80h,
the value of N is 8 and resolution will be:
Resolution = 1/(2N - Auto-Reload Value) = 1/256.
According to the aforesaid values W = fCPU / fCUNTER - 2.
If 5(t) is 10ns, N = TCPU/5(t) = 12.5. TCOUNTER is divided into W*N = 2*12.5 = 25 parts, so, the resolution improved is 25 times. The improvement in resolution directly depends on W and N.
The invention will now be explained using the waveforms. For the purpose of explaining the waveforms, the value of M is taken as 1. The microcontroller 1 provides the Master Clock Out (MCO) and Pulse Width Modulator (PWM) out A which are synchronised at the edge of PWM out A. The signal X obtained from divide by W counter 2 is a reduced frequency signal as compared to MCO having its rising edge synchronised with the edge of MCO. The signal X is
delayed by the delay circuit 3 to provide an output signal Y that acts as the clock of the flip-flop 5. The flip-flop 5 produces the output signal B that is shifted input signal A. The OR gate 6 in turn performs OR operation on the two signals namely A & B to provide the final output.
Figure 3 shows the flowchart in accordance with the invention. The microcontroller generates PWM pulse (A) whose resolution is to be improved and also generates MCO signal 30. The MCO signal (Fcpu) is passed through the divide by W counter to obtain the divided output X 31. The output X is passed to the delay circuit, which is controllable by microcontroller user application, to get, delayed Fcpu/W 32. This delayed signal represented by Y is used as a clock in D flip-flop to get the shifted PWM signal (B) 33. The signals A and B are ORed to get the desired signal with improved PWM resolution 34.

We claim:
1. A system for generating Pulse Width Modulated signal having variable duty cycle
resolution comprising:
a microcontroller for generating a master clock output;
a divide by W counter having its input connected to said master clock output of
said microcontroller providing a divided clock output;
a delay circuit having its input connected to the output of said divide by W
counter for introducing a delay in said divided clock output;
a flip-flop having its data input connected to a second output of said
microcontroller and its clock being connected to the output of said delay circuit
for shifting said second output of said microcontroller; and
a logic gate receiving the outputs of said flip flop and said second output of said
microcontroller for providing an improved resolution PWM waveform.
2. The system as claimed in claim 1 wherein said delay circuit includes a multiplier block that feedbacks the signal M number of times to introduce desired delay.
3. The system as claimed in claim 1 wherein said system provides a PWM waveform with resolution up to a fraction of the time period of Central Processing Unit (TCPU)-
4. The system as claimed in claim 1 wherein said logic gate is an OR gate.
5. The system as claimed in claim 1 wherein said second signal is a pulse width modulated signal.
6. The system as claimed in claim 1 wherein said flip-flop is D - flip flop.
7. A method for generating Pulse Width Modulated signal having variable duty cycle resolution comprising the steps of:
generating master clock output;
- providing a divided master clock output;
- delaying said divided master clock output;
- shifting pulse width modulated signal using said delayed signal as clock; and - performing a logic operation on said pulse width modulated signal and shifted pulse width modulated signal to obtain the improved resolution PWM waveform.
8. The method as claimed in claim 6 wherein said method provides a PWM waveform with resolution up to a fraction of the time period of Central Processing Unit (TCPU)-
9. The method as claimed in claim 6 wherein said logic operation is OR operation.
10. A system for generating Pulse Width Modulated signal having variable duty cycle resolution substantially as herein described with reference to and as illustrated in the accompanying drawings.
11. A method for generating Pulse Width Modulated signal having variable duty cycle resolution substantially as herein described with reference to and as illustrated in the accompanying drawings.