Claims:What is claimed is:
1. A system for minimizing crosstalk effects of shells and designing multi-walled carbon nanotube models, comprising:

a computing device configured to provide a plurality of simulation models using an analog circuit simulator for design of multi-walled carbon nanotube models, whereby the analog circuit simulator configured to accurately estimate crosstalk effects for different number of shells in Multi-walled carbon nanotube (MWCNT) and perform transient, steady state, frequency domain analyses; and

multi-walled carbon nanotube (MWCNT) models designed based on analyzation of a propagation delay under an influence of dynamic crosstalk for a plurality of shells on the computing device through the analog circuit simulator, whereby the computing device configured to analyze delays for the plurality of shells and terminates a plurality of interconnect lines with load capacitances and measures the propagation delay for different values of load capacitances, the computing device configured to summarize the propagation delay for the plurality of shells at different interconnect lengths 100µm, 200µm, 500µm and 1000µm respectively by using the analog circuit simulator.

2. The system of claim 1, wherein the analog circuit simulator configured to give simulation setup for the MWCNT interconnects with a CMOS inverter on the computing device.

3. The system of claim 1, wherein the CMOS inverter configured to calculate exact delay caused by the crosstalk.

4. The system of claim 1, wherein the multi-walled carbon nanotube (MWCNT) models comprises capacitive coupled lines which are terminated with load capacitances.

5. The system of claim 1, wherein the computing device configured to analyze crosstalk induced delay at varying interconnect lengths for different values of load capacitances (CL) and the plurality of shells such as an outermost shell and inter most shell.

6. A method for minimizing crosstalk effects of shells and designing multi-walled carbon nanotube models, comprising:

using an analog circuit simulator to generate simulation models of multi-walled carbon nanotube (MWCNT) on a computing device, whereby the computing device allows input parameters through the analog circuit simulator;

setting supply voltage on the computing device through the analog circuit simulator and analyzing the delays for a plurality of shells in MWCNT on the computing device by the analog circuit simulator;

terminating a plurality of interconnect lines with load capacitances (CL) and measuring the propagation delays for different values of the load capacitances ranging from 10aF to 10fF;

analyzing the propagation delay under the influence of dynamic crosstalk for different number of shells in MWCNT through the analog circuit simulator on the computing device, whereby the analog circuit simulator reduces the value of interconnect parasitic such as resistance, inductance and capacitance with increasing the plurality of shells; and

designing multi-walled carbon nanotube (MWCNT) models based on analyzation of a propagation delay under the influence of dynamic crosstalk for the plurality of shells on the computing device.

7. The method of claim 6, wherein the computing device summarizes the propagation delay for the plurality of shells at different interconnect lengths 100µm, 200µm, 500µm and 1000µm respectively by the analog circuit simulator. , Description:TECHNICAL FIELD
[001] The disclosed subject matter relates generally to carbon nanotubes. More particularly, the present disclosure relates to a system and method for minimizing crosstalk effects of shells and designing multi-walled carbon nanotube models.

BACKGROUND
[002] Carbon nanotubes are currently considered for a number of applications since they possess a very desirable and unique combination of physical properties such as strength and weight. Depending upon their different structures, the carbon nanotubes can exhibit both metallic and semiconducting properties. Multi-walled carbon nanotube (MWCNT) is a potential candidate in the area of current nanoscale technology. They are more advantageous than other types of CNT structures due to large number of shells. An intershell resistance exists between each shell due to their potential differences. This intershell resistance primarily signifies the electron tunnel transport phenomenon between each of the shells.

[003] The tunneling current between shells of a defect-free infinitely long MWCNT is very small in general, whereas the experimental measurements in show that the conductance between two shells is about ~(10kO)-1/µm which yields a radial resistivity value of ~1(O.m). However, the tunneling effect would be exponentially dependent on the shell interval. The MWCNT with tunneling resistance has lesser effect on the propagation delay under the influence of dynamic crosstalk. Existing systems difficult to reduce delays for the equivalent models and also analyzes structures with different number of shells.

[004] In the light of the aforementioned discussion, there exists a need for a certain system with a novel methodology that would overcome the above-mentioned challenges.
SUMMARY
[005] The following presents a simplified summary of the disclosure in order to provide a basic understanding of the reader. This summary is not an extensive overview of the disclosure and it does not identify key/critical elements of the invention or delineate the scope of the invention. Its sole purpose is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later.

[006] Exemplary embodiments of the present disclosure is directed towards a system and method for minimizing crosstalk effects of shells and designing multi-walled carbon nanotube models.

[007] An objective of the present disclosure is directed towards obtaining MWCNT with tunneling resistance has lesser effect on propagation delay under the influence of dynamic crosstalk.

[008] Another objective of the present disclosure is directed towards analyzing the propagation delay under the influence of dynamic crosstalk for MWCNT structures with different number of shells at global interconnect lengths ranging from 100µm to 1000µm.

[009] Another objective of the present disclosure is directed towards using carbon nanotubes in many fields such as biomedical applications, air and water filtration, structural applications and so forth.

[0010] Another objective of the present disclosure is directed towards calculating normalized conductivity value (0.3(µO.cm2)-1) based on the measurements ~(10kO)-1/µm which yields a radial resistivity value of ~1(O.m).

[0011] Another objective of the present disclosure is directed towards observing effect of electron tunnel transport phenomenon by using equivalent RLC models.

[0012] Another objective of the present disclosure is directed towards analyzing propagation delay under the influence of dynamic crosstalk for MWCNT structures with different number of shells at global interconnect lengths ranging from 100µm to 1000µm.

[0013] Another objective of the present disclosure is directed towards varying MWCNT diameter according to the number of shells present in MWCNT.

[0014] Another objective of the present disclosure is directed towards reducing the propagation delay of MWCNT with increasing number of shells.

[0015] Another objective of the present disclosure is directed towards replacing interconnect lines by the equivalent RLC model of MWCNT structure.

[0016] Another objective of the present disclosure is directed towards simulation setup uses CMOS inverter at 32 nm technology node for which the technology parameters (length and width) for NMOS is taken as 32 nm and 640 nm and for PMOS, these parameters are taken as 32 nm and 1280 nm, respectively.

[0017] Another objective of the present disclosure is directed towards triggering input rise time at 10% of supply voltage whereas the output fall time is target at 90%.

[0018] Another objective of the present disclosure is directed towards analyzing the delay for different number shells in MWCNTs.

[0019] Another objective of the present disclosure is directed towards terminating the interconnect line with a load capacitance CL. Propagation delay is also measured for different values of CL ranging from 10aF to 10fF.

[0020] According to an exemplary aspect, a system comprising a computing device configured to provide a plurality of simulation models using an analog circuit simulator for design of multi-walled carbon nanotube models, the analog circuit simulator configured to accurately estimate crosstalk effects for different number of shells in Multi-walled carbon nanotube (MWCNT) and perform transient, steady state, frequency domain analyses.

[0021] According to another exemplary aspect, the system further comprising multi-walled carbon nanotube (MWCNT) models which are designed based on analyzation of a propagation delay under an influence of dynamic crosstalk for a plurality of shells on the computing device through the analog circuit simulator, the computing device configured to analyze delays for the plurality of shells and terminates a plurality of interconnect lines with load capacitances and measures the propagation delay for different values of load capacitances, the computing device configured to summarize the propagation delay for the plurality of shells at different interconnect lengths 100µm, 200µm, 500µm and 1000µm respectively by using the analog circuit simulator.

BRIEF DESCRIPTION OF THE DRAWINGS
[0022] FIG. 1 is a diagram depicting a system for minimizing crosstalk effects of shells and designing multi-walled carbon nanotube models, in accordance with one or more exemplary embodiments.

[0023] FIG. 2 is a diagram depicting Multi-walled carbon nanotube (MWCNT) interconnects with the CMOS inverter, in accordance with one or more exemplary embodiments.
[0024] FIG. 3 is a diagram depicting an equivalent distributed RLC circuit model of MWCNT with P shells, in accordance with one or more exemplary embodiments.

[0025] FIG. 4 is a diagram depicting an equivalent distributed RLC circuit model MWCNT interconnect, in accordance with one or more exemplary embodiments.

[0026] FIG. 5 is an example diagram depicting an exemplary graph comprising cross induced delays for varying load capacitance at predetermined interconnect length, in accordance with one or more exemplary embodiments.

[0027] FIG. 6 is an example diagram depicting another exemplary graph comprising cross induced delays for varying load capacitance at predetermined interconnect length, in accordance with one or more exemplary embodiments.

[0028] FIG. 7 is an example diagram depicting another exemplary graph comprising cross induced delays for varying load capacitance at predetermined interconnect length, in accordance with one or more exemplary embodiments.

[0029] FIG. 8 is an example diagram depicting another exemplary graph comprising cross induced delays for varying load capacitance at predetermined interconnect length, in accordance with one or more exemplary embodiments.

[0030] FIG. 9 is an example diagram depicting an exemplary method for minimizing crosstalk effects of shells and designing multi-walled carbon nanotube models, in accordance with one or more exemplary embodiments.

[0031] FIG. 10 is a block diagram illustrating the details of digital processing system in which various aspects of the present disclosure are operative by execution of appropriate software instructions.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0032] It is to be understood that the present disclosure is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The present disclosure is capable of other embodiments and of being practiced or of being carried out in various ways. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting

[0033] The use of “including”, “comprising” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. The terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item. Further, the use of terms “first”, “second”, and “third”, and so forth, herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

[0034] Referring to FIG. 1 is a diagram 100 depicting a system for minimizing crosstalk effects of shells and designing multi-walled carbon nanotube models, in accordance with one or more exemplary embodiments. The system 100 includes a computing device 102 configured to provide simulation models for the design of multi-walled carbon nanotube models which can accurately estimate crosstalk effects for different number of shells in Multi-walled carbon nanotube (MWCNT). The computing device 102 may include an analog circuit simulator 104 (for example, HSPICE) configured to perform transient, steady state, frequency domain analyses. The analog circuit simulator 104 may be configured to give simulation setup for Multi-walled carbon nanotube (MWCNT) interconnects with a CMOS inverter. The computing device 102 may be configured to summarize the propagation delay for different number of shells at different interconnect lengths 100µm, 200µm, 500µm and 1000µm respectively by using the analog circuit simulator 104 for designing of multi-walled carbon nanotube models (for example, circuits).

[0035] Referring to FIG. 2 is a diagram 200 depicting Multi-walled carbon nanotube (MWCNT) interconnects with the CMOS inverter, in accordance with one or more exemplary embodiments. The analog circuit simulator 104 may be configured to give simulation setup for MWCNT interconnects with the CMOS inverter on the computing device 102. The simulation setup 200 includes capacitive coupled lines 202, 204 in which one is taken as aggressor and other is used as a victim. The capacitive coupled lines 202, 204 may not be limited to, interconnect lines. The simulation setup 200 also includes the CMOS inverter 206 configured to calculate exact delay caused by the crosstalk. Here the CMOS inverter 206 may be the CMOS driver. Where the CMOS inverter 206 at 32 nm technology node for which parameters (for example, length and width) for NMOS may be taken as 32 nm and 640 nm. Similarly, for PMOS, the parameters may be taken as 32 nm and 1280 nm, respectively. As shown in the simulation setup 200, the input rise time is triggered at 10% of supply voltage whereas the output fall time is target at 90%. The delay may be analyzed for different number shells in MWCNTs on the computing device 102. The capacitive coupled lines 202, 204 may be terminated with load capacitances CL 208a, 208b. Propagation delay may also be measured for different values of load capacitances CL ranging from 10aF to 10fF. For example, in the terminology for crosstalk analysis, each signal is analyzed as a victim with all the neighboring nets functioning as aggressors. When the victim net is quiet, or if there is a separation of the switching windows of the victim net from the aggressor nets, the crosstalk may be analyzed statically. If the aggressor nets cause enough voltage variation in the victim net, a change in the digital state-from level one to zero, or vice versa-is propagated to a flip-flop, and a fault is generated due to crosstalk.

[0036] Referring to FIG. 3 is a diagram 300 depicting an equivalent distributed RLC circuit model of MWCNT with P shells, in accordance with one or more exemplary embodiments. The equivalent distributed RLC circuit model 300 includes outermost shell 301, innermost shell 303, and distributed elements 305. The crosstalk induced delay may be analyzed at varying interconnect lengths for different values of load capacitance (CL) and different number of shells such as the outermost shell 301 and inter most shell 303. The computing device 102 may be configured to provide simulation models using the analog circuit simulator 104 for design of multi-walled carbon nanotube models. The analog circuit simulator 104 may be configured to accurately estimate crosstalk effects for different number of shells in Multi-walled carbon nanotube (MWCNT) and perform transient, steady state, frequency domain analyses. The multi-walled carbon nanotube (MWCNT) models may be designed based on analyzation of a propagation delay under an influence of dynamic crosstalk for the shells on the computing device through the analog circuit simulator. The computing device 102 may be configured to analyze delays for the shells and terminates interconnect lines with load capacitances and measures the propagation delay for different values of load capacitances. The computing device 102 may be configured to summarize the propagation delay for the shells at different interconnect lengths 100µm, 200µm, 500µm and 1000µm respectively by using the analog circuit simulator 104.

[0037] The resistance of a shell in diagram 300 consists of three parts such quantum resistance (RQ), scattering induced resistance (RS) and imperfect metal-nanotube contact resistance (Rmc). The scattering resistance (RS) only occurs if the length of the nanotube (shell) is larger than electron mfp. RQ and RS are intrinsic, and Rmc is due to the fabrication process. The value of intrinsic conductance (G) is determined by,

where h 2e2 ~12.9k? , and L, ? and N are the length, mfp and number of conducting channels of the shell, respectively. The imperfect contact resistance Rmc can range from zero to hundreds of kO for different growth process.

On the other hand, the kinetic inductance (LK) of MWCNT is mainly because of the charge carrier inertia and can be expressed as,

where vF is the Fermi velocity of graphene and CNT which is equal to 8×105m/s. Apart from this, the RLC model of Fig. 2 consists of quantum capacitance which is due to the density of electronic states in CNTs and can be formulated as,

[0038] Referring to FIG. 4 is a diagram 400 depicting an equivalent distributed RLC circuit model MWCNT interconnect, in accordance with one or more exemplary embodiments. The equivalent distributed RLC circuit model 400 includes the outermost shell 401, and the innermost shell 403. The crosstalk induced delay for different values of load capacitance (CL) ranging from 10aF to 10fF. The numbers of shells 401, 403 in MWCNTs may be varied in the range of 10 to 30. Propagation delay under the influence of dynamic crosstalk may also be analyzed for different number of shells 401, 403 in MWCNT. The outermost shell diameter of MWCNT basically depends on number of shells in MWCNT. Table I through Table IV summarizes the propagation delay for different number of shells at different interconnect lengths 100µm, 200µm, 500µm and 1000µm respectively. It has been observed that the delay reduces with increasing number of shells in MWCNT. The reason behind is that the value of interconnect parasitic such as resistance, inductance and capacitance reduces with increasing number of shells. These delay values further becomes minimized as the model considers tunneling conductance which is the adverse effect of electron tunnel transport phenomenon.

TABLE I. CROSSTALK INDUCED DELAY AT 100?M INTERCONNECT LENGTHS
MWCNT SHELLS EFFECT OF TUNNELING RESISTANCE CROSSTALK DELAY (IN PS) FOR DIFFERENT VALUES OF LOAD CAPACITANCE (CL)
10AF 100AF 1FF 10FF
10 Li et al.[14] 38.49 39.52 45.64 74.73
Srivastava et al. [15] 46.24 47.14 54.54 117.24
20 Li et al. [14] 31.37 31.74 33.66 53.61
Srivastava et al. [15] 40.64 41.62 46.81 80.02
30 Li et al. [14] 29.81 30.12 31.86 45.28
Srivastava et al. [15] 37.22 37.89 43.53 67.58

TABLE II. CROSSTALK INDUCED DELAY AT 200?M INTERCONNECT LENGTHS
MWCNT SHELLS EFFECT OF TUNNELING RESISTANCE CROSSTALK DELAY (IN PS) FOR DIFFERENT VALUES OF LOAD CAPACITANCE (CL)
10AF 100AF 1FF 10FF
10 Li et al.[14] 52.56 53.25 59.50 106.86
Srivastava et al. [15] 69.41 70.69 83.41 207.08
20 Li et al. [14] 40.34 40.99 44.50 63.05
Srivastava et al. [15] 56.49 57.18 63.87 126.40
30 Li et al. [14] 33.47 33.70 35.91 55.48
Srivastava et al. [15] 34.16 34.37 36.51 57.44

TABLE III. CROSSTALK INDUCED DELAY AT 500?M INTERCONNECT LENGTHS
MWCNT SHELLS EFFECT OF TUNNELING RESISTANCE CROSSTALK DELAY (IN PS) FOR DIFFERENT VALUES OF LOAD CAPACITANCE (CL)
10AF 100AF 1FF 10FF
10 Li et al.[14] 110.14 111.37 123.30 233.33
Srivastava et al. [15] 222.49 256.98 386.59 566.23
20 Li et al. [14] 60.98 61.41 65.44 93.46
Srivastava et al. [15] 142.47 144.03 160.24 316.26
30 Li et al. [14] 32.78 33.32 38.49 58.04
Srivastava et al. [15] 58.07 59.17 69.80 172.37

TABLE IV. CROSSTALK INDUCED DELAY AT 1000?M INTERCONNECT LENGTHS
MWCNT SHELLS EFFECT OF TUNNELING RESISTANCE CROSSTALK DELAY (IN PS) FOR DIFFERENT VALUES OF LOAD CAPACITANCE (CL)
10AF 100AF 1FF 10FF
10 Li et al.[14] 307.71 309.99 332.04 546.70
Srivastava et al. [15] 774.21 780.43 842.62 1459.90
20 Li et al. [14] 105.17 105.73 111.16 158.45
Srivastava et al. [15] 455.09 458.26 489.75 801.26
30 Li et al. [14] 750.36 753.69 786.39 1038.00
Srivastava et al. [15] 341.63 343.74 365.06 574.44

[0039] Referring to FIG. 5 is an example diagram 500 depicting an exemplary graph comprising cross induced delays for varying load capacitance at predetermined interconnect length, in accordance with one or more exemplary embodiments. The exemplary graph 500 may include load capacitance (CL) values 502 on X-axis and propagation delay values 504 on Y-axis. The load capacitance (CL) values 502 may be varied on the computing device 102 at predetermined interconnect length (for example 100µm) to obtain crosstalk induced delays. The exemplary graph 500 demonstrates the variation of crosstalk induced delay for different values of load capacitance CL502 at interconnect lengths of 100 µm on the computing device 102.

[0040] Referring to FIG. 6 is an example diagram 600 depicting another exemplary graph comprising cross induced delays for varying load capacitance at predetermined interconnect length, in accordance with one or more exemplary embodiments. The exemplary graph 600 may include the load capacitance (CL) values 602 on X-axis and propagation delay values 604 on Y-axis. The load capacitance (CL) values 602 may be varied on the computing device 102 at predetermined interconnect length (for example 200µm) to obtain crosstalk induced delays. The exemplary graph 600 demonstrates the variation of crosstalk induced delay for different values of load capacitance CL 602 at interconnect lengths of 200 µm on the computing device 102.

[0041] Referring to FIG. 7 is an example diagram 700 depicting another exemplary graph comprising cross induced delays for varying load capacitance at predetermined interconnect length, in accordance with one or more exemplary embodiments. The exemplary graph 700 may include the load capacitance (CL) values 702 on X-axis and propagation delay values 704 on Y-axis. The load capacitance (CL) values 702 may be varied on the computing device 102 at predetermined interconnect length (for example 200µm) to obtain crosstalk induced delays. The exemplary graph 700 demonstrates the variation of crosstalk induced delay for different values of load capacitance CL 702 at interconnect lengths of 500 µm on the computing device 102.

[0042] Referring to FIG. 8 is an example diagram 800 depicting another exemplary graph comprising cross induced delays for varying load capacitance at predetermined interconnect length, in accordance with one or more exemplary embodiments. The exemplary graph 800 may include the load capacitance (CL) values 802 on X-axis and propagation delay values 804 on Y-axis. The load capacitance (CL) values 802 may be varied on the computing device 102 at predetermined interconnect length (for example 200µm) to obtain crosstalk induced delays. The exemplary graph 800 demonstrates the variation of crosstalk induced delay for different values of load capacitance CL 802 at interconnect lengths of 1000 µm on the computing device 102.

[0043] Referring to FIG. 9 is an example flowchart 900 depicting an exemplary method for minimizing crosstalk effects of shells and designing multi-walled carbon nanotube models, in accordance with one or more exemplary embodiments. The method 900 may be carried out in the context of the details of FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG.5, FIG. 6, FIG. 7, and FIG. 8. However, the method 900 may also be carried out in any desired environment. Further, the aforementioned definitions may equally apply to the description below.

[0044] The computing device 102 uses the analog circuit simulator to generate simulation models of multi-walled carbon nanotube (MWCNT), at step 902. The computing device allows the input parameters (for example, length and width of NMOS and PMOS) through the analog circuit simulator, at step 904. Sets supply voltage on the computing device through the analog circuit simulator, at step 906. Here, the input rise time is trigged at 10% of supply voltage whereas the output fall time is target at 90%. The computing device analyzes the delays for different number of shells in MWCNT, at step 908. For example, analyzes the crosstalk induced at varying interconnect lengths for different values of load capacitance (CL) and different number of shells. The computing device terminates the interconnect lines with load capacitances (CL) and measures the propagation delays for different values of the load capacitances ranging from 10aF to 10fF, at step 910. The computing device further analyzes the propagation delay under the influence of dynamic crosstalk for different number of shells in MWCNT through the analog circuit simulator, at step 912. The computing device summarizes the propagation delay for different number of shells at different interconnect lengths 100µm, 200µm, 500µm and 1000µm respectively by using the analog circuit simulator for designing of multi-walled carbon nanotube models (for example, circuits), at step 914. The value of interconnect parasitic such as resistance, inductance and capacitance reduces with increasing number of shells, at step 916. Where delay values further become minimized as the model considers tunneling conductance which is the adverse effect of electron tunnel transport phenomenon. Thereafter, at step 918, the multi-walled carbon nanotube (MWCNT) models are designed based on analyzation of a propagation delay under the influence of dynamic crosstalk for the different number of shells on the computing device.

[0045] Referring to FIG. 10, FIG. 10 is a block diagram 900 illustrating the details of digital processing system 1000 in which various aspects of the present disclosure are operative by execution of appropriate software instructions. Digital processing system 1000 may correspond to the computing device 102 (or any other system in which the various features disclosed above can be implemented).

[0046] Digital processing system 1000 may contain one or more processors such as a central processing unit (CPU) 1010, random access memory (RAM) 1020, secondary memory 1030, graphics controller 1060, display unit 1070, network interface 1080, an input interface 1090. All the components except display unit 1070 may communicate with each other over communication path 1050, which may contain several buses as is well known in the relevant arts. The components of Figure 10 are described below in further detail.

[0047] CPU 1010 may execute instructions stored in RAM 1020 to provide several features of the present disclosure. CPU 1010 may contain multiple processing units, with each processing unit potentially being designed for a specific task. Alternatively, CPU 1010 may contain only a single general-purpose processing unit or can be a part of Cloud processing Unit.

[0048] RAM 1020 may receive instructions from secondary memory 1030 using communication path 1050. RAM 1020 is shown currently containing software instructions, such as those used in threads and stacks, constituting shared environment 1025 and/or user programs 1026. Shared environment 1025 includes operating systems, device drivers, virtual machines, etc., which provide a (common) run time environment for execution of user programs 1026.

[0049] Graphics controller 1060 generates display signals (e.g., in RGB format) to display unit 1070 based on data/instructions received from CPU 1010. Display unit 1070 contains a display screen to display the images defined by the display signals. Input interface 1090 may correspond to a keyboard and a pointing device (e.g., touch-pad, mouse) and may be used to provide inputs. Network interface 1080 provides connectivity to a network (e.g., using Internet Protocol), and may be used to communicate with other systems (such as those shown in Figure 1, network module 120) connected to the network.

[0050] Secondary memory 1030 may contain hard drive 1035, flash memory 1036, and removable storage drive 1037. Secondary memory 1030 may store the data software instructions (e.g., for performing the actions noted above with respect to the Figures), which enable digital processing system 1000 to provide several features in accordance with the present disclosure.

[0051] Some or all of the data and instructions may be provided on removable storage unit 1040, and the data and instructions may be read and provided by removable storage drive 1037 to CPU 1010. Floppy drive, magnetic tape drive, CDROM drive, DVD Drive, Flash memory, removable memory chip (PCMCIA Card, EEPROM) are examples of such removable storage drive 1037.

[0052] The removable storage unit 1040 may be implemented using medium and storage format compatible with removable storage drive 1037, or a cloud storage such that removable storage drive 1037 can read the data and instructions. Thus, the removable storage unit 1040 includes a computer readable (storage) medium having stored therein computer software and/or data. However, the computer (or machine, in general) readable medium can be in other forms (e.g., non-removable, random access, etc.).

[0053] In this document, the term "computer program product" is used to generally refer to the removable storage unit 1040 or hard disk installed in hard drive 1035. These computer program products are means for providing instructions to digital processing system 1000. CPU 1010 may retrieve the software instructions, and execute the instructions to provide various features of the present disclosure described above.
[0054] The term “storage media/medium” as used herein refers to any non-transitory media that store data and/or instructions that cause a machine to operate in a specific fashion. Such storage media may comprise non-volatile media and/or volatile media. Non-volatile media includes, for example, optical disks, magnetic disks, or solidstate drives, such as secondary memory 1030. Volatile media includes dynamic memory, such as RAM 1020. Common forms of storage media include, for example, a floppy disk, a flexible disk, hard disk, solid-state drive, magnetic tape, or any other magnetic data storage medium, a CD-ROM, any other optical data storage medium, any physical medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASH-EPROM, NVRAM, any other memory chip or cartridge.

[0055] Storage media is distinct from but may be used in conjunction with transmission media. Transmission media participates in transferring information between storage media. For example, transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise bus 1050. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave and infra-red data communications.

[0056] Reference throughout this specification to “one embodiment”, “an embodiment”, or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases “in one embodiment”, “in an embodiment” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0057] Furthermore, the described features, structures, or characteristics of the disclosure may be combined in any suitable manner in one or more embodiments. Although the present disclosure has been described in terms of certain preferred embodiments and illustrations thereof, other embodiments and modifications to preferred embodiments may be possible that are within the principles and spirit of the invention. The above descriptions and figures are therefore to be regarded as illustrative and not restrictive.

[0058] Thus the scope of the present disclosure is defined by the appended claims and includes both combinations and sub-combinations of the various features described hereinabove as well as variations and modifications thereof, which would occur to persons skilled in the art upon reading the foregoing description.