Claims:1. A system for multi-channel radio frequency (RF) sampling with down conversion, the system comprising:
one or more RF connectors configured to receive one or more RF input signals;
one or more analog to digital converters (ADCs) operatively configured with the one or more RF connectors to receive the one or more RF signals;
one or more clock synthesizers are electrically configured with the one or more ADCs for selecting sampling rate of the one or more ADCs;
one or more clock buffers electrically configured with the one or more clock synthesizers for providing one or more clock signals to the one or more ADCs; and
a programmable chip operatively configured with the one or more ADCs and the one or more clock buffers, wherein the programmable chip is configured to facilitate, through the one or more ADCs, digital down conversion (DDC)of the one or more RF signals.
2. The system as claimed in claim 1, wherein the one or more clock buffers are configured to receive a first reference signal and a second reference signal and generate the one or more clock signals for the one or more ADCs.
3. The system as claimed in claim 2, wherein the one or more clock signals are synchronous phase coherent sampling clocks signals.
4. The system as claimed in claim 1, wherein the programmable chip comprises a field programmable gate-array (FPGA).
5. The system as claimed in claim 3, wherein the FPGA is operatively configured with the one or more ADCs using JESD interface.
6. The system as claimed in claim 1, wherein output from the one or more ADCs,can be configured from FPGA for digital down conversion and output data rate can be selected by configuring the decimation filters of one or more ADCs through FPGA
7. The system as claimed in claim 5, wherein the system comprises a clock distributer electrically configured with the one or more clock buffer, and the clock distributer is configured to generate a first clock signal for the FPGA, one or more system reference signals for the one or more ADCs and the one or more clock synthesizers.

, Description:TECHNICAL FIELD
[0001] The present disclosure relates to the field of radar receivers. More particularly the present disclosure relates to a system for multi-channel radio frequency (RF) sampling with down conversion in radar receivers.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Conventionally, in modern radar utilize some type of down-conversion to an intermediate frequency or base band before analog-to-digital conversion takes place. Several microwave components are needed for this down-conversion process. The components can include a tunable local oscillator, band pass filters, amplifiers, and other signal conditioning devices. This makes the receiver components big, complex. Also, the receiver having such components requires increased operation, maintenance, and manufacturing cost. Large number of components are also increase chances of failure of the receiver thereby reduces reliability sometimes.
[0004] There is, therefore, a need of a system for down-conversion of input radio frequency signals without the added components to the receiver hardware.

OBJECTS OF THE PRESENT DISCLOSURE
[0005] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below.
[0006] It is an object of the present disclosure to provide a system for multi-channel radio frequency (RF) sampling with down conversion.
[0007] It is an object of the present disclosure to provide a system for multi-channel radio frequency (RF) sampling with down conversion without requiring any microwave components.
[0008] It is an object of the present disclosure to provide a system for multi-channel radio frequency (RF) sampling with down conversion with reduced size.
[0009] It is an object of the present disclosure to provide a system for multi-channel radio frequency (RF) sampling with down conversion with reduced operation and maintenance cost.
[0010] It is an object of the present disclosure to provide a system for multi-channel radio frequency (RF) sampling with better utilization of frequency band and simplified receiver hardware.
[0011] It is an object of the present disclosure to provide a system for multi-channel radio frequency (RF) sampling with increased reliability and stability.
[0012] It is an object of the present disclosure to provide a system for multi-channel radio frequency (RF) sampling with down conversion.
[0013] It is an object of the present disclosure to provide a system for multi-channel radio frequency (RF) sampling that can be upgraded.

SUMMARY
[0014] The present disclosure relates to the field of radar receivers. More particularly the present disclosure relates to a system for multi-channel radio frequency (RF) sampling with down conversion in radar receivers.
[0015] An aspect of the present disclosure pertains to a system for multi-channel radio frequency (RF) sampling with down conversion. The system includes one or more RF connectors configured to receive one or more RF input signals. One or more analog to digital converters (ADCs) operatively configured with the one or more RF connectors to receive the one or more RF signals. One or more clock synthesizers are electrically configured with the one or more ADCs for selecting sampling rate of the one or more ADCs. One or more clock buffers electrically configured with the one or more clock synthesizers for providing one or more clock signals to the one or more ADCs. A programmable chip operatively configured with the one or more ADCs and the one or more clock buffers, wherein the programmable chip is configured to facilitate, through the one or more ADCs, digital down conversion (DDC) of the one or more RF signals.
[0016] In an aspect, the one or more clock buffers may be configured to receive a first reference signal and a second reference signal and may generate the one or more clock signals for the one or more ADCs. The one or more clock signals may be synchronous phase coherent sampling clocks signals.
[0017] In an aspect, the programmable chip may include a field programmable gate-array (FPGA) that may be operatively configured with the one or more ADCs using JESD interface. One or more ADCs can be configured from FPGA for digital down conversion and output data rate can be selected by configuring the decimation filters of one or more ADCs.
[0018] In an aspect, the system may include a clock distributer electrically configured with the one or more clock buffer, and the clock distributer may be configured to generate a first clock signal for the FPGA, one or more system reference signals for the one or more ADCs and the one or more clock synthesizers.
[0019] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF DRAWINGS
[0020] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The diagrams are for illustration only, which thus is not a limitation of the present disclosure.
[0021] In the figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label with a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
[0022] FIG. 1 illustrates an exemplary block diagram of a system for multi-channel radio frequency (RF) sampling with down conversion, in accordance with an embodiment of the present disclosure.
[0023] FIG. 2 illustrates an exemplary functional diagram of the systemfor eight-channel radio frequency (RF) sampling with down conversion, in accordance with an embodiment of the present disclosure.
[0024] FIG. 3 illustrates an exemplary diagram of clock scheme for the systemfor multi-channel radio frequency (RF) sampling with down conversion, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0025] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0026] In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details.
[0027] The present disclosure relates to the field of radar receivers. More particularly the present disclosure relates to a system for multi-channel radio frequency (RF) sampling with down conversion in radar receivers.
[0028] An embodiment of the present disclosure pertains to a system for multi-channel radio frequency (RF) sampling with down conversion. The system includes one or more RF connectors configured to receive one or more RF input signals. One or more analog to digital converters (ADCs) operatively configured with the one or more RF connectors to receive the one or more RF signals. One or more clock synthesizers are electrically configured with the one or more ADCs for selecting sampling rate of the one or more ADCs. One or more clock buffers electrically configured with the one or more clock synthesizers for providing one or more clock signals to the one or more ADCs. A programmable chip operatively configured with the one or more ADCs and the one or more clock buffers, wherein the programmable chip is configured to facilitate, through the one or more ADCs, digital down conversion (DDC) of the one or more RF signals.
[0029] In an embodiment, the one or more clock buffers can be configured to receive a first reference signal and a second reference signal and can generate the one or more clock signals for the one or more ADCs.
[0030] In an embodiment, the one or more clock signals can be synchronous phase coherent sampling clocks signals.
[0031] In an embodiment, the programmable chip can include a field programmable gate-array (FPGA).
[0032] In an embodiment, the FPGA can be operatively configured with the one or more ADCs using JESD interface.
[0033] In an embodiment, one or more ADCs can be configured from FPGA for digital down conversion and output data rate can be controlled by configuring the decimation filters of one or more ADCs.
[0034] In an embodiment, the system can include a clock distributer electrically configured with the one or more clock buffer, and the clock distributer can be configured to generate a first clock signal for the FPGA, one or more system reference signals for the one or more ADCs and the one or more clock synthesizers.
[0035] FIG. 1 illustrates an exemplary block diagram of a system for multi-channel radio frequency (RF) sampling with down conversion, in accordance with an embodiment of the present disclosure.
[0036] FIG. 2 illustrates an exemplary functional diagram of the systemfor eight-channel radio frequency (RF) sampling with down conversion, in accordance with an embodiment of the present disclosure.
[0037] As illustrated, a proposed system 100 for multi-channel radio frequency (RF) sampling with down conversion can includes one or more RF connectors 102 that can be configured to receive one or more RF input signals. One or more analog to digital converters (ADCs)104-1, 104-2, 104-3...104-n collectively known as ADCs 104 and individually known as ADC 104. The ADCs 104 can be operatively configured with the one or more RF connectors 102to receive the one or more RF signals. The ADCs 104 can directly sample input frequencies from DC to 10 GHz and can support sampling rates up to 5.2Gbps in dual channel mode. The ADCs 104 can be used to sample the RF input signals directly without any requirement of down converting elements that are conventionally used. The one or more ADCs 104 can include but without limiting to direct sampling dual channel ADCs.
[0038] In an embodiment, one or more clock synthesizers106-1, 106-2...106-n collectively known as clock synthesizers 106 and individually known as clock synthesizer 106. The clock synthesizers 106 can be electrically configured with the one or more ADCs104 for controlling sampling rate of the one or more ADCs 104. Programmable clock synthesizers (also referred as clock synthesizers) approach is used to cover the entire sampling range of the ADC 104 without the need of hardware replacement for different sampling clock requirements. One or more clock buffers 108 can be electrically configured with the one or more clock synthesizers 106 for providing one or more clock signals to the one or more ADCs104. A programmable chip 110 can be operatively configured with the one or more ADCs104 and the one or more clock buffers 108.
[0039] In an embodiment, the programmable chip 110 can be but without limiting to field programmable Gate array (FPGA). The ADCs 104 internal registers can be configured from the FPGA 110 for digital down conversion through serial programming interface. The programmable chip 110 can be configured to facilitate, through the one or more ADCs104, digital down conversion (DDC) of the one or more RF signals. The system can further include an ethernet module 122, BPI 118 (Byte Peripheral Interface is a flash memory serves as external memory and can be used to store the data), QSPI120 (Quad Serial Peripheral Interface is a serial flash memory used to store FPGA configuration bit stream to enable power on programming) can be included and placed in compact form factor. The FPGA 110 can be operatively configured with the ADCs 104 using a JESD interface. The FPGA 110 can receive the decimated baseband data of 8 channels over the JESD protocol/interface (as shown in FIG. 2). Multiplexing of I,Q data of 8 channels can be performed inside FPGA 110 and sent to signal processor for further processing over optical 10G interface 124.
[0040] FIG. 3 illustrates an exemplary diagram of clock scheme for the systemfor multi-channel radio frequency (RF) sampling with down conversion, in accordance with an embodiment of the present disclosure.
[0041] As illustrated, the clock buffers 108can be configured to receive a first reference signal 112 (also referred as int_ref, herein) and a second reference signal 114 (also referred as ext_ref) and can generate the one or more clock signals OSCin (also referred as clock buffer outputs, herein) for the one or more ADCs104. The int_ref112 (internal reference clock) can be for bench level testing and the ext_ref114 (external reference clock) can be used for system level testing. An input frequency can be varied at run-time and the DDC can be performed without making any changes in the hardware. Multiplexing of I,Q data of 8 channels is performed inside FPGA 110 and sent to the Signal Processor for further processing over Optical 10G interface 124.
[0042] In an embodiment, the one or more clock signals OSC in can be synchronous phase coherent sampling clocks signals. The system can include a clock distributer 130 that can be electrically configured with the clock buffers 108, and the clock distributer 130can be configured to generate a first clock signal for the FPGA 110, one or more system reference signals (SYREF) for the one or more ADCs 104 and the one or more clock synthesizers 106.The clock buffer outputs (OSCin) are given to 2no’s of clock synthesizers (106-1, 106-2) and the clock distributor130. Clock synthesizers106 generate the sampling clocks (also referred as CLK in FIG. 3) required for all the ADCs 104. The clock distributor 130 generates clocks required for the Transceivers of FPGA 110, SYSREF signals for all the ADCs 104 and SYSREF for clock synthesizers 106. All the clock synthesizers 106 are synchronised to achieve synchronization between ADC 104 sampling clocks.
[0043] Moreover, in interpreting the specification, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refer to at least one of something selected from the group consisting of A, B, C ….and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc.
[0044] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE INVENTION
[0045] The proposed invention provides a system for multi-channel radio frequency (RF) sampling with down conversion.
[0046] The proposed invention provides a system for multi-channel radio frequency (RF) sampling with down conversion without requiring any microwave components.
[0047] The proposed invention provides a system for multi-channel radio frequency (RF) sampling with down conversion with reduced size.
[0048] The proposed invention provides a system for multi-channel radio frequency (RF) sampling with down conversion with reduced operation and maintenance cost.
[0049] The proposed invention provides a system for multi-channel radio frequency (RF) sampling with better utilization of frequency band and simplified receiver hardware.
[0050] The proposed invention provides a system for multi-channel radio frequency (RF) sampling with increased reliability and stability.
[0051] The proposed invention provides a system for multi-channel radio frequency (RF) sampling with down conversion.
[0052] The proposed invention provides a system for multi-channel radio frequency (RF) sampling that can be upgraded.