Claims:What is claimed is:
1. A system for reducing crosstalk delays in electronic devices, comprising:
a computing device configured to provide a plurality of simulation models of multi-line bus architecture by a multi-line bus architecture simulator, whereby the multi-line bus architecture simulator configured to provide simulation setup for a plurality of interconnect lines on the computing device, the computing device configured to calculate the dynamic crosstalk induced delay of the plurality of interconnect lines for a plurality of global interconnect lengths and perform a comparative analysis of crosstalk induced delay for equivalent area of the plurality of interconnect lines;

a CMOS inverter is configured to drive the plurality of interconnect lines of the multi-line bus architecture on the computing device by the multi-line bus architecture simulator to demonstrate the crosstalk effect of the multi-line bus architecture, whereby the multi-line bus architecture simulator configured to reduce crosstalk delay in the plurality of interconnect lines; and

a multi-line bus architecture designed based on the comparative analysis of crosstalk induced delay for equivalent area of the plurality of interconnect lines.

2. The system of claim 1, wherein the multi-line bus architecture includes a plurality of load capacitances configured to terminate the interconnect lines.

3. The system of claim 1, wherein the multi-line bus architecture includes a plurality of inter-line coupling capacitance configured to depend on the spacing between an aggressor and a victim to analyze the crosstalk induced delay.

4. The system of claim 1, wherein the multi-line bus architecture configured to use the CMOS inverters at 32 nm technology node for which the technology parameters (length and width) for NMOS is taken as 32 nm and 640 nm and for PMOS the technology parameters are taken as 32 nm and 1280 nm.

5. A method for reducing crosstalk delays in electronic devices, comprising:
using a multi-line bus architecture simulator on a computing device to calculate dynamic crosstalk induced delay of a plurality of interconnect lines;
allowing a plurality of input the parameters (for example, length and width of NMOS and PMOS) on the computing device through the multi-line bus architecture simulator;
adjusting a supply voltage on the computing device through the multi-line bus architecture simulator;
triggering the input rise time at 10% of supply voltage whereas the output fall time is target at 90%;
varying the plurality of shells in MWCNTs in the range of 10 to 15 on the computing device;
Performing the simulations on the computing device using the multi-line bus architecture simulator wherein each line is represented by equivalent models of Cu, MWCNT and MLGNR interconnects;
Varying the interconnect length in the range of 30 µm to 90 µm on the computing device; and
Obtaining the reduced crosstalk induced delay for MLGNR with more number of layers compared to equivalent Cu and MWCNT interconnects. , Description:TECHNICAL FIELD
[001] The present disclosure generally relates to the field of nanoscale technology. More particularly, the present disclosure relates to a system for reducing crosstalk delays in electronic devices using a complementary metal–oxide–semiconductor.

BACKGROUND
[002] The feature size is reducing in the current deep submicron (DSM) technology whereas the clock frequency continues to increase. This advancement leads the interconnect technology into a new era where it has to face certain challenges such as electro-migration, higher resistivity due to surface boundary scattering, skin effect, signal integrity, delay uncertainty, power dissipation, etc.

[003] The portable devices are much smaller in dimension and faster in comparison with technology scaling as the connecting wires are placed closer to each other with higher aspect ratios. This leads to the large coupling capacitance that causes crosstalk noise and excessive signal delay. The inductive effects are also facing an upward trend due to higher clock frequency, faster transition (rise/fall) time and longer signal wires. The inductive effects are also facing an upward trend due to higher clock frequency, faster transition (rise/fall) time and longer signal wires. With the scaling of feature size, more and more transistors are accommodated in an integrated chip. To further increase the functionality and subsequently the number of transistors, a larger number of interconnect levels are required that leads to multi-layer interconnect system. This results in a significant increase of design complexity that requires new design tools to deal with the newer challenges. However, with advancement of technology, it has been found that the resistivity of Cu increases rapidly with reduced cross-sectional area. It is due to the enhanced grain, surface scattering, longer interconnects, joules heating and increase in power dissipation. Moreover, at higher frequency operation, problems like skin effects, signal integrity, crosstalk induced propagation delay are become noticeable and challenging to handle. Due to these issues, researchers have found an alternative to aluminum and copper materials for high speed VLSI interconnects.

[004] Due to the above mentioned challenges, the designing of global interconnects is one of the major design concerns for achieving high-performance chips. Hence, there is a need of novel technology to fulfill the above mentioned challenges and are of more advantageous than copper (Cu) and multi-walled carbon nanotube (MWCNT) due to more number of conducting channels.

[005] In the light of the aforementioned discussion, there exists a need for a certain system with novel methodologies that would overcome the above-mentioned disadvantages.

SUMMARY
[006] The following presents a simplified summary of the disclosure in order to provide a basic understanding to the reader. This summary is not an extensive overview of the disclosure and it does not identify key/critical elements of the invention or delineate the scope of the invention. Its sole purpose is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later.

[007] An objective of the invention directed towards a multi-line bus architecture driven by a CMOS inverter is employed to demonstrate the crosstalk effect.

[008] Another objective of the invention directed towards an accurate analytical model is employed for MLGNR and MWCNT interconnects considering the effect of inter-layer/ inter-shell coupling capacitance, mutual inductance and tunneling resistance.

[009] Another objective of the invention directed towards improving the performance of the portable device by increasing the chip size and scaling.

[0010] Another objective of the invention directed towards enhancing the leakage of power dissipation in the portable devices.

[0011] Another objective of the invention directed towards emerging interconnect materials like carbon nanotube (CNT), graphene nanoribbon (GNR), for high speed VLSI interconnects.

[0012] Another objective of the invention directed towards increasing the resistivity of copper rapidly by reducing the cross-sectional area due to the enhanced grain, surface scattering, longer interconnects, joules heating and increase in power dissipation.

[0013] Another objective of the invention directed towards using a multi-line bus architecture (for example, five line) for the simulation purpose.

[0014] Another objective of the invention directed towards using CMOS inverter to drive the interconnect lines of the multi-line bus architecture (for example, five line).

[0015] Another objective of the invention directed towards coupling the CMOS driver over a resistive driver to operate partially in linear and partially in the saturation region during switching.

[0016] Another objective of the invention directed towards a transistor is modeled by a resistor in the linear region.

[0017] Another objective of the invention directed towards the transistor is more accurately modeled as a current source with parallel high resistance in the saturation region. Therefore, the analysis of crosstalk using a CMOS driver reveals an improved performance over the resistive driver.

[0018] According to an exemplary aspect a computing device configured to provide a plurality of simulation models of multi-line bus architecture by a multi-line bus architecture simulator.

[0019] According to another exemplary aspect, the multi-line bus architecture simulator configured to provide simulation setup for a plurality of interconnect lines on the computing device, the computing device configured to calculate the dynamic crosstalk induced delay of the plurality of interconnect lines for a plurality of global interconnect lengths and perform a comparative analysis of crosstalk induced delay for equivalent area of the plurality of interconnect lines.

[0020] According to another exemplary aspect, a CMOS inverter is configured to drive the plurality of interconnect lines of the multi-line bus architecture on the computing device by the multi-line bus architecture simulator to demonstrate the crosstalk effect of the multi-line bus architecture, the multi-line bus architecture simulator configured to reduce crosstalk delay in the plurality of interconnect lines.

[0021] According to another exemplary aspect, a multi-line bus architecture designed based on the comparative analysis of crosstalk induced delay for equivalent area of the plurality of interconnect lines.

BRIEF DESCRIPTION OF THE DRAWINGS
[0022] FIG. 1 is a block diagram depicting a computing device assisting a user to minimize crosstalk delays, in accordance with one or more exemplary embodiments.

[0023] FIG. 2 is an example diagram depicting a schematic representation of cross-section of multi-walled carbon nanotubes with number of shells, in accordance with one or more embodiments.

[0024] FIG. 3 is an example diagram depicting a schematic representation of multi-conductor transmission line (MTL) model of multi-walled carbon nanotubes, in accordance with one or more embodiments.

[0025] FIG. 4 is an example diagram depicting a schematic representation of a multi-line bus architecture simulation setup for Cu/ MWCNT/ MLGNR interconnects with CMOS inverter, in accordance with one or more embodiments.

[0026] FIG. 5 is an example diagrams depicting an exemplary graph comprising cross induced delays at aggressor line for equivalent multi-walled carbon nanotube shell, in accordance with one or more exemplary embodiments.

[0027] FIG. 6 is an example diagram depicting another exemplary graph comprising cross induced delays for varying load capacitance at predetermined interconnect length, in accordance with one or more exemplary embodiments.

[0028] FIG. 7 is an example diagram depicting another exemplary graph comprising cross induced delays for varying load capacitance at predetermined interconnect length, in accordance with one or more exemplary embodiments.

[0029] FIG. 8 is an example diagram depicting another exemplary graph comprising cross induced delays for varying load capacitance at predetermined interconnect length, in accordance with one or more exemplary embodiments.

[0030] FIG. 9 is a flowchart depicting an exemplary method for obtaining the reduced crosstalk induced delay in MLGNR and MWCNT interconnects, in accordance with one or more exemplary embodiments.

[0031] FIG. 10 is a block diagram illustrating the details of a digital processing system 1000 in which various aspects of the present disclosure are operative by execution of appropriate software instructions.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0032] It is to be understood that the present disclosure is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The present disclosure is capable of other embodiments and of being practiced or of being carried out in various ways. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting.

[0033] The use of “including”, “comprising” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. The terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item. Further, the use of terms “first”, “second”, and “third”, and the like, herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

[0034] In current nanoscale technology, the portable device performance mostly depends on interconnects material used, transistor delay and power dissipation. The performance may be improved by increasing the chip size and scaling that further enhances the leakage power dissipation in the portable devices. Scaling also has opposing effect on RLC delay in VLSI circuits that causes an increase in resistivity of the metal interconnects and hence degrading the performance of the devices.

[0035] Referring to FIG. 1, is a block diagram 100 depicting a computing device assisting a user to minimize crosstalk delays, in accordance with one or more exemplary embodiments. The computing device 102 may include a multi-line bus architecture simulator 104 (for example, HSPICE) configured to perform transient, steady state, frequency domain analyses. The multi-line bus architecture simulator 104 may be configured to provide simulation setup for interconnect lines with a complementary metal–oxide–semiconductor (CMOS) inverter. The interconnect lines may include, but not limited to, Copper, Multi-walled carbon nanotube (MWCNT), Multi-layered graphene nanoribbons (MLGNR), and so forth.

[0036] Referring to FIG. 2 is an example diagram 200 depicting a schematic representation of cross-section of multi-walled carbon nanotubes with number of shells, in accordance with one or more embodiments. The diagram 200 depicts total number of shells 202a-202n. The total number of shells 202a-202n may be primarily depends on the inter-shell distance (d=0.34nm) and the diameters of inner and outer shells. The ith shell of multi-walled carbon nanotubes may be characterized by the number of conducting channels (Ni) of 1D-energy sub-bands crossing the fermi level. The Ni is dependent on the diameter of ith shell, Di.

[0037] Referring to FIG. 3 is an example diagram 300 depicting a schematic representation of multi-conductor transmission line (MTL) model of multi-walled carbon nanotubes, in accordance with one or more embodiments. The diagram 300 comprises a quantum/internal resistance (RQ) 302 and contact resistance (RC) 304, Induced resistance (RS) 306, kinetic Inductance (L’Ki) 308, magnetic inductance (L’Mi) 310, quantum capacitance (C’Qi) 312, electrostatic capacitance (C’e) 314, intershell coupling capacitance (C’Sij) 316, coupling capacitance (C’C) 318. The quantum/internal resistance (RQ) 302 and contact resistance RC 304 are may be the length independent resistance. The induced resistance (RS) 306 may be a length dependent resistance. The kinetic Inductance (L’Ki) 308 accounts for the kinetic energy of electrons. The magnetic inductance (L’Mi) 310 primarily arises due to the magnetic field of multi-walled carbon nanotubes. The quantum capacitance (C’Qi) 312 that accounts for the density of electronic states in MWCNTs. The electrostatic capacitance (C’e) 314 and intershell coupling capacitance (C’Sij) 316 are positioned between two shells i, j. The coupling capacitance (C’C) 318 may be positioned between any two MWCNTs.

[0038] The interconnect parasitics are may be obtained based on the total number of conducting channels in MWCNT. The conducting channels in MWCNT accounting the diameter dependency can be expressed as

[0039] The resistance offered by ith shell in MWCNT can be expressed as

[0040] Where l and ? represents the length of interconnect line and mean free paths, respectively. For a particular shell (i.e., i), R’Ti, R’Si and RQi represents the resistances whereas Ni is the number of conducting channels for that particular shell.
[0041] The kinetic inductance for ith shell can be expressed as

[0042] where vF is the Fermi velocity of graphene and is approximately equal to 8×105m/s.

[0043] where ht and DM are the distance from the ground plane and outermost shell diameter, respectively.

[0044] Referring to FIG. 4 is an example diagram 400 depicting a schematic representation of a multi-line bus architecture simulation setup for Cu/ MWCNT/ MLGNR interconnects with CMOS inverter, in accordance with one or more embodiments. The diagram 400 includes Cu/ MWCNT/ MLGNR interconnect lines 401a-401e, CMOS inverter 404a-404e, load capacitances (CL) 406a-406e, coupling capacitance (Ccm) 408a-408d. The multi-line bus architecture 400 may be used to demonstrate the effect of crosstalk induced delay. The multi-line bus architecture 400 is used for simulation setup for Cu/ MWCNT/ MLGNR interconnects with a CMOS inverter. The multi-line bus architecture 400 includes Cu/ MWCNT/ MLGNR lines 401a-401e in which the first line is taken as an aggressor and second line is taken as a victim.

[0045] The equivalent models of Cu, MWCNT and MLGNR are may be used to represent each line of the bus architecture model. The CMOS inverter 404a-404e may be used to drive the interconnect lines 401a-401e of the multi-line bus architecture bus architecture. The bus architecture driven by the CMOS inverters 404a-404e may be employed to demonstrate the crosstalk effect. The crosstalk effect may result in an average of 35.71% and 20.21% improved crosstalk delay. The reduced cross talk delay may be observed for the multi-layered graphene nanoribbons with more number of layers compared to equivalent Cu and MWCNT interconnects. The multi-line bus architecture may be replaced the equivalent RLC model of Cu, multiwall carbon nanotubes, and multi-layered graphene nanoribbons. The multi-line bus architecture 400 may use the CMOS inverters 404a-404e at 32 nm technology node for which the technology parameters (length and width) for NMOS is taken as 32 nm and 640 nm and for PMOS the technology parameters are taken as 32 nm and 1280 nm.

[0046] The input rise time may be triggered at 10% of supply of voltage whereas the output fall time is target at 90%. The delay may be analyzed for similar Cu area, MWCNT outer-shell diameter and MLGNR thickness. The load capacitances (CL) 406a-406e may be configured to terminate the interconnect line. For example, the load capacitance (CL) 406a-406e is of 10 aF. The inter-line coupling capacitance (Ccm) 408 may depends on spacing between aggressor and victim (Sa-v = 32nm) to analyze the crosstalk induced delay.

[0047] The propagation delay under the influence of dynamic crosstalk may be primarily dependent on the area of copper (Cu), number of shells in MWCNT and number of layers in MLGNR. For more area and interconnect lengths of Cu, the quantitative value of line resistance increases that further increase the delay of Cu interconnects. However, for more number of shells in MWCNT and layers in MLGNR, the number of conducting channel increases that drastically reduces the overall resistance whereas increases the quantum capacitance. However, the overall capacitance remains constant due to the effect of electrostatic capacitance. Therefore, the cumulative effect of resistance and capacitance is the primary reason for reduced crosstalk induced delay in MLGNR and MWCNT interconnects. Additionally, for an equivalent area, the more number of layers in MLGNR compared to shells in MWCNT also increase the total number of conducting channels and hence the overall propagation delay under the influence of dynamic crosstalk is reduced. Using victim lines, the percentage reduction in crosstalk induced delay of MLGNR with respect to Cu and MWCNT are also summarized in the below tables.

Interconnect length (µm) % reduction in crosstalk induced delay for MLGNR (Nlayer = 22) as compared to
MWCNT(Nshell = 10) Cu (Area = 40 nm2)
30 3.957 12.566
60 4.505 17.68
90 5.418 21.0226

Interconnect length (µm) % reduction in crosstalk induced delay for MLGNR (Nlayer = 32) as compared to
MWCNT(Nshell = 15) Cu (Area = 86 nm2)
30 13.794 29.54
60 16.284 31.116
90 20.021 35.010

[0048] Referring to FIG. 5 is an example diagrams 500 depicting an exemplary graph comprising cross induced delays at aggressor line for equivalent multi-walled carbon nanotube shell, in accordance with one or more exemplary embodiments. The exemplary graph 500 may include interconnect length values 502 on X-axis and crosstalk delay values 504 on Y-axis. The interconnect length values 502 may be varied on the computing device 102 at predetermined interconnect length (for example 100µm) to obtain crosstalk induced delays. The crosstalk induced delay at aggressor at for equivalent MWCNT shell may be 10, MLGNR layers may be 22 and Cu area may be 40 nm2.

[0049] For example, the numbers of shells in the multiwall carbon nanotubes are may be varied in the range of 10 to 15. The equivalent number of layers in multi-layer graphene nanoribbons are may be considered as 22 and 32 for the given outer-shell diameter of multiwall carbon nanotubes. Similarly, the area of copper (Cu) may be considered as 40 nm2 and 86 nm2, respectively. The simulations are may be performed on the computing device 102 using a multi-line bus architecture wherein each line is represented by equivalent models of Cu, MWCNT and MLGNR interconnects. The interconnect length may be varied in the range of 30 µm to 90 µm.
[0050] Referring to FIG. 6 is an example diagram 600 depicting another exemplary graph comprising cross induced delays for varying load capacitance at predetermined interconnect length, in accordance with one or more exemplary embodiments. The exemplary graph 600 may include interconnect length values 602 on X-axis and crosstalk delay values 604 on Y-axis. The interconnect length values 602 may be varied on the computing device 102 at predetermined interconnect length (for example 100µm) to obtain crosstalk induced delays. The crosstalk induced delay at aggressor at for equivalent MWCNT shell may be 15, MLGNR layers may be 32 and Cu area may be 86 nm2.

[0051] Referring to FIG. 7 is an example diagram 700 depicting another exemplary graph comprising cross induced delays for varying load capacitance at predetermined interconnect length, in accordance with one or more exemplary embodiments. The exemplary graph 700 may include interconnect length values 702 on X-axis and crosstalk delay values 704 on Y-axis. The interconnect length values 702 may be varied on the computing device 102 at predetermined interconnect length (for example 100µm) to obtain crosstalk induced delays. The crosstalk induced delay at aggressor at for equivalent MWCNT shell may be 10, MLGNR layers may be 22 and Cu area may be 40 nm2.

[0052] Referring to FIG. 8 is an example diagram 800 depicting another exemplary graph comprising cross induced delays for varying load capacitance at predetermined interconnect length, in accordance with one or more exemplary embodiments. The exemplary graph 800 may include interconnect length values 802 on X-axis and crosstalk delay values 804 on Y-axis. The interconnect length values 802 may be varied on the computing device 102 at predetermined interconnect length (for example 100µm) to obtain crosstalk induced delays. The crosstalk induced delay at aggressor at for equivalent MWCNT shell may be 15, MLGNR layers may be 32 and Cu area may be 86 nm2.

[0053] Referring to FIG. 9 is a flowchart 900 depicting an exemplary method for obtaining the reduced crosstalk induced delay in MLGNR and MWCNT interconnects, in accordance with one or more exemplary embodiments. As an option, the method 900 is carried out in the context of the details of FIG. 1, FIG. 2 FIG. 3, FIG. 4 FIG.5, FIG. 6, FIG. 7, and FIG. 8. However, the method 900 is carried out in any desired environment. Further, the aforementioned definitions are equally applied to the description below.

[0054] The exemplary method 900 commences at step 902, the computing device uses the multi-line bus architecture simulator to calculate the dynamic crosstalk induced delay of Cu, MWCNT and MLGNR, at step 902. The computing device allows the inputs the parameters (for example, length and width of NMOS and PMOS) through the multi-line bus architecture simulator, at step 904. Sets supply voltage on the computing device through the multi-line bus architecture simulator, at step 906. Triggering the input rise time at 10% of supply voltage whereas the output fall time is target at 90%, at step 908. Varying the numbers of shells in MWCNTs in the range of 10 to 15 on the computing device, at step 910. For the given outer-shell diameter of MWCNT, the equivalent number of layers in MLGNR are considered as 22 and 32 and the area of Cu is also considered as 40 nm2 and 86 nm2. Performing the simulations on the computing device using a multi-line bus architecture simulator wherein each line is represented by equivalent models of Cu, MWCNT and MLGNR interconnects, at step 912. Varying the interconnect length in the range of 30 µm to 90 µm on the computing device, at step 914. Obtaining the reduced crosstalk induced delay for MLGNR with more number of layers compared to equivalent Cu and MWCNT interconnects, at step 916.

[0055] Referring to FIG. 10, FIG. 10 is a block diagram 1000 illustrating the details of a digital processing system 1000 in which various aspects of the present disclosure are operative by execution of appropriate software instructions. The digital processing system 1000 may correspond to the computing device 102 (or any other system in which the various features disclosed above can be implemented).

[0056] Digital processing system 1000 may contain one or more processors such as a central processing unit (CPU) 1010, random access memory (RAM) 1020, secondary memory 1027, graphics controller 1060, display unit 1070, network interface 1080, and input interface 1090. All the components except display unit 1070 may communicate with each other over communication path 1050, which may contain several buses as is well known in the relevant arts. The components of Figure 10 are described below in further detail.

[0057] CPU 1010 may execute instructions stored in RAM 1020 to provide several features of the present disclosure. CPU 1010 may contain multiple processing units, with each processing unit potentially being designed for a specific task. Alternatively, CPU 1010 may contain only a single general-purpose processing unit.

[0058] RAM 1020 may receive instructions from secondary memory 1030 using communication path 1050. RAM 1020 is shown currently containing software instructions, such as those used in threads and stacks, constituting shared environment 1025 and/or user programs 1026. Shared environment 1025 includes operating systems, device drivers, virtual machines, etc., which provide a (common) run time environment for execution of user programs 1026.

[0059] Graphics controller 1060 generates display signals (e.g., in RGB format) to display unit 1070 based on data/instructions received from CPU 1010. Display unit 1070 contains a display screen to display the images defined by the display signals. Input interface 1090 may correspond to a keyboard and a pointing device (e.g., touch-pad, mouse) and may be used to provide inputs. Network interface 1080 provides connectivity to a network (e.g., using Internet Protocol), and may be used to communicate with other systems (such as those shown in Figure 1) connected to the network.

[0060] Secondary memory 1030 may contain hard drive 1035, flash memory 1036, and removable storage drive 1037. Secondary memory 1030 may store the data software instructions (e.g., for performing the actions noted above with respect to the Figures), which enable digital processing system 1000 to provide several features in accordance with the present disclosure.

[0061] Some or all of the data and instructions may be provided on removable storage unit 1040, and the data and instructions may be read and provided by removable storage drive 1037 to CPU 1010. Floppy drive, magnetic tape drive, CD-ROM drive, DVD Drive, Flash memory, removable memory chip (PCMCIA Card, EEPROM) are examples of such removable storage drive 1037.

[0062] Removable storage unit 1040 may be implemented using medium and storage format compatible with removable storage drive 1037 such that removable storage drive 1037 can read the data and instructions. Thus, removable storage unit 1040 includes a computer readable (storage) medium having stored therein computer software and/or data. However, the computer (or machine, in general) readable medium can be in other forms (e.g., non-removable, random access, etc.).

[0063] In this document, the term "computer program product" is used to generally refer to removable storage unit 1040 or hard disk installed in hard drive 1035. These computer program products are means for providing software to digital processing system 1000. CPU 1010 may retrieve the software instructions, and execute the instructions to provide various features of the present disclosure described above.

[0064] The term “storage media/medium” as used herein refers to any non-transitory media that store data and/or instructions that cause a machine to operate in a specific fashion. Such storage media may comprise non-volatile media and/or volatile media. Non-volatile media includes, for example, optical disks, magnetic disks, or solid-state drives, such as storage memory 1030. Volatile media includes dynamic memory, such as RAM 1020. Common forms of storage media include, for example, a floppy disk, a flexible disk, hard disk, solid-state drive, magnetic tape, or any other magnetic data storage medium, a CD-ROM, any other optical data storage medium, any physical medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASH-EPROM, NVRAM, any other memory chip or cartridge.

[0065] Storage media is distinct from but may be used in conjunction with transmission media. Transmission media participates in transferring information between storage media. For example, transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise bus (communication path) 1050. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave and infra-red data communications.

[0066] Reference throughout this specification to “one embodiment”, “an embodiment”, or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases “in one embodiment”, “in an embodiment” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0067] Furthermore, the described features, structures, or characteristics of the disclosure may be combined in any suitable manner in one or more embodiments. In the above description, numerous specific details are provided such as examples of programming, software modules, user selections, network transactions, database queries, database structures, hardware modules, hardware circuits, hardware chips, etc., to provide a thorough understanding of embodiments of the disclosure.

[0068] Although the present disclosure has been described in terms of certain preferred embodiments and illustrations thereof, other embodiments and modifications to preferred embodiments may be possible that are within the principles and spirit of the invention. The above descriptions and figures are therefore to be regarded as illustrative and not restrictive.

[0069] Thus the scope of the present disclosure is defined by the appended claims and includes both combinations and sub-combinations of the various features described hereinabove as well as variations and modifications thereof, which would occur to persons skilled in the art upon reading the foregoing description.