Claims:We claim:

1. A short circuit protection system (100) for a power converter, the power converter comprises at least two semiconductor switches T1 and T2 driven by at least two by separate gate drive sources SQG1 and SQG2 that provide input voltages V1 and V2, at least two independent gate driver circuits GD1 and GD2,
DC bus (VDC1) connected to the power converter, wherein R1 internal resistance and L1 inductance of connecting wire or bus system, the power converter converts voltage inputs (V1 and V2) onto a power input line into another voltage to output as an output voltage to a load through a power output line, the short circuit protection system (100) comprising:
at least six logic gate circuits (IC) (U1, U2, U4, U5, U6 and U7);
at least two comparator circuits (U8 and U9);
at least two isolated supply for circuit operation (VDC2 and VDC3);
at least four current limiting resistances (R2, R3, R4 and R5);
at least two diodes (D1 and D2) and
at least two zener diodes (Z1 and Z2) that are electrically coupled with each other;
wherein, the system (100) prevents DC (VDC1) short circuit incase if the gate drive sources SQG1 and SQG2 are overlapped, or incase if any one of the two semiconductor switches T1 or T2 already in state of fault or short.

2. The short circuit protection system (100) as claimed in claim 1 is electrically coupled between the gate drive sources SQG1 and SQG2 and the gate driver circuits GD1 and GD2.

3. The short circuit protection system (100) as claimed in claim 1, wherein the at least six logic gate circuits (IC) includes at least two NOT gates (U1 and U2) and at least four AND gated (U4, U5, U6 and U7) that are electrically coupled with each other.

4. The short circuit protection system (100) as claimed in claim 1, wherein
a first IC U1 (NOT gate) is electrically coupled to the gate drive source SQG2 to receive an input voltage V2 therefrom,
a second IC U2 (NOT gate) is electrically coupled to the gate drive source SQG1 to receive an input voltage V1 therefrom,
a third IC U4 (AND gate) is electrically coupled to receive an input signal V1 from the gate drive source SQG1 and an inverted signal V2 from the first IC U1 (NOT gate),
a fourth IC U5 (AND gate) is electrically coupled to receive an input signal V2 from the gate drive source SQG2 and an inverted signal V1 from the second IC U2 (NOT gate),
a fifth IC U6 (AND gate) is electrically coupled to receive an output of the third IC U4 (AND gate) and an output of the fifth IC U6 is provided to the gate driver circuit GD1, and
a sixth IC U7 (AND gate) is electrically coupled to receive an output of the fourth IC U5 (AND gate) and an output of the sixth IC U7 is provided to the gate driver circuit GD2.

5. The short circuit protection system (100) as claimed in claim 1, wherein
a first comparator circuit U8 is electrically coupled with a first semiconductor switch T1 such that the first comparator circuit U8 has
• two inputs including an inverting input that is connected fixed voltage reference (VR2) generated by zener diode Z2 and non-inverting input that is connected to anode of D2 (VD2), and
• an output (V6) connected to one input of the sixth IC U7 (AND gate), and
a second comparator circuit U9 is electrically coupled with a second semiconductor switch T2 such that the second comparator circuit U9 has
• two inputs including inverting input that is connected fixed voltage reference (VR1= 5V DC) generated by the zener diode Z1 and non-inverting input that is connected to anode of the diode D1 (VD1), and
• an output (V5) connected to one input of the fifth IC U6 (AND gate).

6. The short circuit protection system (100) as claimed in claim 1, wherein two current limiting resistances (R3 and R5) are connected in series with the zener diodes (Z1 and Z2) and remaining two current limiting resistances (R2 and R4) are connected in series with the diodes (D1 and D2).

7. The short circuit protection system (100) as claimed in claim 1, wherein each of the two isolated supply for circuit operation (VDC2 and VDC3) has +15V voltage.

8. The short circuit protection system (100) as claimed in claim 1, wherein each zener diode (Z1 and Z2) has 5V voltage.

9. The short circuit protection system (100) as claimed in claim 1 is coupled to each leg of the power converter.

10. The short circuit protection system (100) as claimed in claim 1, wherein each of the semiconductor switches T1 and T2 are selected from group consisting of an insulated-gate bipolar transistor (IGBT), a bipolar junction transistor (BJT) and a metal-oxide semiconductor field-effect transistor (MOSFET) and like.

Dated this 27th day of August 2020

Prafulla Wange
(Agent for the Applicant)
(IN/PA-2058) , Description:SYSTEM FOR SHORT CIRCUIT PROTECTION IN POWER CONVERTER

Field of the invention:

The present invention generally relates to power converter circuits and more particularly relates to system for short circuit protection in a power converter.

Background of the invention:

A power converter is an electrical or electro-mechanical device for converting electrical energy. The power converter converts alternating current (AC) to or from direct current (DC), or the voltage or frequency, or combinations thereof. The power converter is used in many electronic systems and products based on their efficiency, power dissipation, thermal management, converter size and weight, battery life, and tight voltage regulation. The power converter can be classified according to whether the input and output are the alternating current (AC) or the direct current (DC) for example, AC to DC, DC to AC, DC to DC and AC to AC. The power converter consists of number of legs depending on configuration. Each leg consists of two semiconductor devices in series.

Figure 1 shows single leg configuration of a bridge type power converter, in accordance with an embodiment of the present invention. Figure 2 shows single phase bridge type power converter with two legs and figure 3 shows three phase bridge type power converter with three legs, in accordance with alternate embodiments of the present invention.

A short-circuit protection system for the power converter is becoming essential to comply with safety standards. In accordance with a prior art, figure 4 shows a short circuit protection system in one leg configuration of the bridge type power converter system (as shown in figure 1). The bridge type power converter system consists of T1 and T2 are semiconductor switch that are connected in series and driven two by separate gate drive sources SQG1 and SQG2 ideally 180 degree phase shifted with amplitude equal to +15V so that I1 shall be near to zero. GD1 and GD2 are two independent gate driver circuit required because T1 and T2 gate drive signals (V3 and V4) are completely isolated. VDC1 is DC bus connected to power converter and R1 and L1 are internal resistance and inductance of connecting wire or bus.

Problems in existing prior art:

Referring to Figure 4, semiconductor element T1 and T2 are connected in series and driven two by separate gate drive sources SQG1 and SQG2 typically 180 degree phase shifted so that I1 shall be near to zero.

Problem 1: If the separate gate drive sources (SQG1 and SQG2) are not 180 degree shifted then large amount of current (I1) flow through the semiconductor elements T1 and T2. Typically this current is limited by wire resistance R1 and wire inductance L1. T1 and T2 may get damaged if the current I1 exceeds safe operating limit of T1 and T2. Figure 5 shows simulated result when the SQG1 and SQG2 are 10 degree overlapped.

Problem 2: If any one of the semiconductor elements T1 or T2 damaged by any reason and resulted in short or always ON, then other series element T1 or T2 may get damaged if gate drive is applied.

Existing solutions for the problems mentioned in the prior art and their drawbacks:

1. A dead time is provided in SQG1 and SQG2 so that overlapping can be avoided. But, the dead time is always limited by propagation delay, rise time, fall time of gate driver circuit and semiconductor rating. Also, large value of dead time adversely affects the output.

2. The current I1 is sensed using current transformer and disconnect gate drive SQG1 and SQG2 incase if the fault is detected. This method will be effective if the control circuit is enough fast to take action. Also, in this method, both T1 and T2 are switched ON to detect state of failure.

Accordingly, there exists a need to provide system and method for short circuit protection in power converter that overcomes the above mentioned drawbacks in the prior art.

Objects of the invention:

An object of the present invention is to provide a reliable short circuit protection circuit for a power converter from an overcurrent due to a short circuit caused in a load.

Another object of the present invention is to provide immunity to a power converter against malfunctioning of hardware circuit or software.

Yet, one more object of the present invention is to avoid failure of power devices used in the power converter.

Summary of the invention:

Accordingly, the present invention provides a short circuit protection system for a power converter. The power converter comprises at least two semiconductor switches T1 and T2 driven by at least two by separate gate drive sources SQG1 and SQG2 that provide input voltages V1 and V2, at least two independent gate driver circuits GD1 and GD2. Each of said semiconductor switches T1 and T2 are selected from the group consisting of a BJT, MOSFET, IGBT and like. DC bus (VDC1) is connected to the power converter. R1 is internal resistance and L1 is inductance of connecting wire or bus system. The power converter converts voltage inputs (V1 and V2) onto a power input line into another voltage to output as an output voltage to a load through a power output line. The short circuit protection system comprises at least six logic gate circuits (IC) (U1, U2, U4, U5, U6 and U7); at least two comparator circuits (U8 and U9); at least two isolated supply for circuit operation (VDC2 and VDC3); at least four current limiting resistances (R2, R3, R4 and R5); at least two diodes (D1 and D2) and at least two zener diodes (Z1 and Z2) that are electrically coupled with each other. The short circuit protection system is electrically coupled between the gate drive sources SQG1 and SQG2 and the gate driver circuits GD1 and GD2. The at least six logic gate circuits (IC) includes at least two NOT gates (U1 and U2) and at least four AND gated (U4, U5, U6 and U7) that are electrically coupled with each other. Each of the two isolated supply for circuit operation (VDC2 and VDC3) has +15V voltage. Each zener diode (Z1 and Z2) has 5V voltage. The short circuit protection system is coupled to each leg of the power converter. The short circuit protection system prevents DC (VDC1) short circuit incase if the gate drive sources SQG1 and SQG2 are overlapped, or incase if any one of the two semiconductor switches T1 or T2 already in state of fault or short.

Brief description of the drawings:

Other features as well as the advantages of the invention will be clear from the following description.

In the appended drawings:
Figure 1 shows single leg configuration of a bridge type power converter, in accordance with an embodiment of the present invention;

Figure 2 shows a single phase bridge type power converter with two legs, in accordance with an alternate embodiment of the present invention;

Figure 3 shows a three phase bridge type power converter with three legs, in accordance with another alternate embodiment of the present invention;

Figure 4 shows a short circuit protection system in one leg configuration of the bridge type power converter system, in accordance with a prior art;

Figure 5 shows graphical waveforms of input voltages, output voltages and current in the power converter, when the gate drive signals overlapped, in accordance with a prior art;

Figure 6 shows a short circuit protection system for a power converter, in accordance with the present invention;

Figure 7 shows graphical waveforms of input voltages, output voltages and current in the power converter, when the gate drive signals overlapped, in accordance with the present invention;

Figures 8 and 9 indicate graphical waveforms of input voltages, output voltages and current in the power converter, when any one of the semiconductors is short, in accordance with the present invention; and

Figure 10 shows graphical waveforms of input voltages, output voltages and current, when the power converter is in healthy condition, in accordance with the present invention.

Detailed description of the invention:

The foregoing objects of the present invention are accomplished and the problems and shortcomings associated with the prior art, techniques and approaches are overcome by the present invention as described below in the preferred embodiments.

The present invention provides a reliable short circuit protection system for a power converter from an overcurrent due to a short circuit caused in a load. The short circuit protection system provides immunity to the power converter against malfunctioning of hardware circuit or software and avoids failure of power devices used in the power converter.

This present invention is illustrated with reference to the accompanying drawings, throughout which reference numbers indicate corresponding parts in the various figures.

Referring now to figure 6, a short circuit protection system (100) (hereinafter referred as, “the system (100)”) for a power converter, in accordance with the present invention is shown. In an embodiment, the power converter is single leg configuration of a bridge type power converter as shown in figure 1. However, in alternate embodiments, the system (100) can be used in any types of the power converter selected from a single phase bridge type power converter with two legs (as shown in figure 2) and a three phase bridge type power converter with three legs (as shown in figure 3). However, each leg of the power converter system requires separate proposed new system (100).

In an exemplary embodiment, the power converter is a single leg configuration of the bridge type power converter that coverts direct current signals into alternating current (DC to AC). The power converter comprises at least two semiconductor switches T1 and T2 that are connected in series. The semiconductor devices can be selected from an insulated-gate bipolar transistor (IGBT), bipolar junction transistor (BJT) and a metal-oxide semiconductor field-effect transistor (MOSFET) and like, but not limited thereto. The semiconductor switches T1 and T2 are driven by at least two by separate gate drive sources SQG1 and SQG2 that provide input voltages V1 and V2. Ideally, the separate gate drive sources SQG1 and SQG2 have gate drive signals 180 degree phase shifted with amplitude equal to +15V, so that an output current I1 across the semiconductor switches T1 and T2 shall be near to zero. At least two independent gate driver circuits GD1 and GD2 are required because T1 and T2 gate drive signals (V3 and V4) are completely isolated. VDC1 is DC bus connected to the power converter and R1 and L1 are internal resistance and inductance of connecting wire or bus system.

The system (100) is electrically coupled between the gate drive sources SQG1 and SQG2 and the gate driver circuits GD1 and GD2, The system (100) prevents DC (VDC1) short circuit incase if the gate drive sources SQG1 and SQG2 are not exactly 180 degree phase shifted, or incase if any one of the two semiconductor switches T1 or T2 already in state of fault or short. The system (100) comprises at least six logic gate circuits (IC) including at least two NOT gates (U1 and U2), at least four AND gated (U4, U5, U6 and U7), at least two comparator circuits (U8 and U9). At least two isolated supply for circuit operation (VDC2 and VDC3), at least four current limiting resistances (R2, R3, R4 and R5), at least two diodes (D1 and D2) and at least two zener diodes (Z1 and Z2) that are electrically coupled with each other. Each of the two isolated supply for circuit operation (VDC2 and VDC3) has +15V voltage. Each zener diode (Z1 and Z2) has 5V voltage.

A first IC U1 (NOT gate) is electrically coupled to the gate drive source SQG2 to receive an input voltage V2 therefrom and a second IC U2 (NOT gate) is electrically coupled to the gate drive source SQG1 to receive an input voltage V1 therefrom. A third IC U4 (AND gate) is electrically coupled to receive an input signal V1 from the gate drive source SQG1 and an inverted signal V2 from the first IC U1 (NOT gate). A fourth IC U5 (AND gate) is electrically coupled to receive an input signal V2 from the gate drive source SQG2 and an inverted signal V1 from the second IC U2 (NOT gate). A fifth IC U6 (AND gate) is electrically coupled to receive an output of the third IC U4 (AND gate), whereas a sixth IC U7 (AND gate) is electrically coupled to receive an output of the fourth IC U5 (AND gate). An output of the fifth IC U6 is provided to the gate driver circuit GD1 and an output of the sixth IC U7 is provided to the gate driver circuit GD2.

A first comparator circuit U8 is electrically coupled with a first semiconductor switch T1. The first comparator circuit U8 has two inputs including an inverting input is connected fixed voltage reference (VR2 = 5V DC) generated by the zener diode Z2 and non-inverting input is connected to anode of the diode D2 (VD2). For ideal semiconductor T1 and ideal diode D2, when the first semiconductor switch T1 is in ON condition or short, a voltage drop across T1 become Zero and voltage drop across the second diode D2 become zero; hence the voltage VD2 remains zero. When the first semiconductor switch T1 is in OFF condition or open, the voltage VD2 remain +15V DC. When VD2>VR2, an output of the first comparator circuit U8 become high and when VD2VR1, an output of second comparator circuit U9 become high and when VD1