FORM 2
THE PATENT ACT 1970 [39 OF 1970]
&
The Patents Rules, 2003
COMPLETE SPECIFICATION
[See section 10; rule 13]
“SYSTEM GENERATING EDGE TRIGGERED INTERRUPT USING ON-CHIP
UART AND A METHOD THEREOF”
Name of the Applicant: Tata Motors Limited; Bombay House, 24 Homi Mody
Street, Hutatma Chowk, Mumbai 400 001 Maharashtra, India.
Nationality: Indian
The following specification particularly describes the invention and the manner in which it is to be performed

TECHNICAL FIELD
This disclosure relates to edge triggered interrupt system and more particularly it relates to edge triggered interrupt system which is based on universal asynchronous serial communication.
BACKGROUND AND PRIOR ART
Electronic Systems based on micro-controllers needs to generate Edge-triggered interrupts for applications require processing asynchronous events such as switch closures, level transitions, pulses etc.
Micro-controller based electronic systems generally suffer from lack of on-chip resources to process such interrupts. This idea describes how an unused on-chip UART can be tricked into interrupting the micro-controller to detect edges in the input wave-form. This concept comes handy when all the conventional on-chip resources for edge-triggered interrupts have been exhausted due to the application requirements and we need to process one more edge-driven input without switching-over to a costly micro-controller.
Although the conventional technique suffers from following drawbacks as:
They ties-up an on-chip edge triggered interrupt hardware only for detection of edges of
the signal although signals are processed by other ports.
Use of on-chip external interrupt is mutually exclusive with on-chip digital input-output
and analog to digital conversion system.
Hence applications requiring ADC cannot use Edge triggered interrupt.
MC33199 k-line transceiver chip datasheet describes a simplified application diagram for interfacing k-line transceiver chip and microcontroller. The application uses two separate hardware pins; one for detection of wake up pattern which is a 25msec low signal on external interrupt pin and other is for further receiving communication messages serially over receiver pin.
This approach requires a separate hardware module of microcontroller for detection of wake up pattern falling edge.

SUMMARY OF THE DISCLOSURE
Edge triggered interrupt generation technique which makes use of on-chip resources comprising of serial asynchronous receiver circuits. This technique basically uses an on-chip embedded algorithm to generate Edge triggered interrupt at of the “receiver Pin” which is connected to input signal interface circuit. Edge triggered input generated is used for measuring the pulse width or processing asynchronous events for application involving switch closure, level transitions, pulses etc.
Method of generating Edge triggered interrupt comprises the steps, initialization of serial communication receiver pin in asynchronous mode with high baud rate; the input signal in the form of digital input (pulses in case of PWM input) is assigned to the receiver pin; and Edge interrupt is detected as receiving byte at receiver pin with break error.
Edge triggered interrupt system based on serial communication in accordance with this invention basically comprises of embedded micro-controller with input interface and an on-chip serial Asynchronous receiver. Wherein said micro-controller is connected with input interfaces. The micro-controller is further interfaced with Edge triggered interrupt generator using its on-chip serial receiver hardware means. The micro-controller apart from interacting with the said input/output interfaces runs an algorithm to generate a Edge triggered interrupt on serial receiver channel. The receiving byte with high baud rate with break error thus generated edge triggered interrupt.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
Referring to the drawings wherein the illustrations are for the purpose of demonstrating a preferred embodiment of the disclosure only, and not for the purpose of limiting the same:
Figure 1 shows block diagram of Edge triggered interrupt system based on serial communication.
Figure 2 shows a flowchart of the method used in Edge triggered interrupt system based on serial communication.

Figure 3 shows example of input signal bit pattern used to detect Edge triggered interrupt based on serial communication.
DETAILED DESCRIPTION
The primary embodiment of the present disclosure is a method of generating edge triggered interrupt using universal asynchronous receiver transmitter (UART) in a microcontroller, said method comprising acts of initialising serial communication of the microcontroller to a predetermined baud rate; receiving input data byte by of the UART using the serial communication via receiver pin; storing the received data in received buffer; comparing the received data byte and break error bit with predefined values to detect an edge in the received data; and generating an interrupt signal to interrupt the microcontroller upon detecting the edge.
In yet another embodiment the received data byte is compared with the predefined value 0x00.
In still another embodiment the break error bit is compared with the predefined value one.
Another embodiment of the present disclosure is a processing device to generate edge triggered interrupt using universal asynchronous receiver transmitter (UART) (4) comprises input interface circuit (2) connected to the communication ports of a processing device; processing unit (5) comprising communication ports, on-chip universal asynchronous receiver transmitter (UART) (4), comparator and peripherals, said UART (4) receives input data from the interface circuit (2) using receiver pin and stores the input data in received buffer, said comparator compares the received data byte with predefined value to detect an edge and generate edge triggered interrupt.
In yet another embodiment of the present disclosure the input interface circuit (2) sends input data to the processing device at a predetermined rate.
In still another embodiment of the present disclosure the processing unit is selecting from a group comprising microcontroller, field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC).

In still another embodiment of the present disclosure the communication ports of the processing unit is selected from a group comprising serial ports and parallel ports.
In still another embodiment of the present disclosure the UART receiver receives data using the serial communication port.
Another embodiment of the present disclosure is a system to generate edge triggered interrupt using universal asynchronous receiver transmitter (UART) comprises an universal asynchronous receiver transmitter (UART) (12) to receive input data (11); an interfacing circuit (13) to interface the UART with a processing unit (14); and processing unit (14) to receive the data from the UART (12), said processing unit (14) comprise communication ports, comparator and peripherals, the comparator compares the received data byte with predefined value to detect an edge in the received data and generate edge triggered interrupt.
In yet another embodiment of the present disclosure the processing unit (14) is selecting from a group comprising microcontroller, field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC).
In still another embodiment of the present disclosure the communication ports of the processing unit is selected from a group comprising serial ports and parallel ports.
In still another embodiment of the present disclosure the received data byte is stored in a received buffer of the UART.
Figure 1 shows an Edge triggered interrupt system based on serial communication comprises of processing unit, where embedded micro-controller is used as a processing unit as shown with an input interface and an on-chip serial asynchronous receiver. Wherein said micro-controller is connected with said input interfaces. The said microcontroller is further interfaced with Edge triggered interrupt generator using its on-chip serial receiver hardware means. The micro-controller apart from interacting with the said input/output interfaces runs an algorithm to generate an edge triggered interrupt on serial

receiver channel. The receiving byte with high baud rate with break error thus generated edge triggered interrupt.
Figure 2 shows another embodiment of the Edge triggered interrupt system where the UART (12) is external to the processing unit (14). An interfacing circuit (13) connects UART (12) with the processing unit (14). Here the processing unit used is a microcontroller. UART (12) receives input data (11) and sends for processing to processing unit (14). The processing unit (14) comprises a comparator to compares the received data byte with predefined value 0x00 and also a break error bit is check whether it is set or not to detect an edge in the received data and generate edge triggered interrupt.
As per application requirements Edge triggered interrupts detected are used for processing switch closure, level transitions, and may be used for measuring the pulse width in case of PWM signal or applications require detection of edge triggered interrupt.
The following are the Signal Interfaces and Applications:
For the digital input signal, the typical automatic applications are Switch closure and
level detection.
For the pulse input signal, the typical automatic applications are PWM analog inputs detection and wake up signal detection in case communication protocols. Internal timer resource is also used to measure the pulse width.
Method of generating Edge triggered interrupt comprises the steps, initialization of serial communication receiver pin in asynchronous mode with high baud rate; the input signal in the form of digital input (pulses in case of PWM input) is assigned to the receiver pin; and Edge interrupt is detected as receiving byte at receiver pin with break error.
Figure 3 explains the method used to generate Edge triggered interrupt which comprises of the following steps:

First the initialization of the serial communication in asynchronous mode (201) and configure the baud rate high enough to detect the edge as well as able to differentiate between a successful edge as well as spurious noise.
The next step is looking for a start bit i.e. a falling edge (202). As edge triggered interrupt is defined as system should interrupt when a falling/rising edge encounters. In serial communication start bit also treated as wake up bit or start of byte data. As start bit received, serial communication receiver system starts reading next 8 bits followed by stop bit (203). After completion of reception of 8 bits, serial communication receiver system generates an interrupt to inform that data (byte) received is available in the receiving buffer.
The next step is that the byte received in received buffer is read for differentiating between noise and edge.
In the final step the byte read is compared with 0x00 and also checks whether break error bit is set (204). Break error bit is set when while receiving a byte no stop bit is received which is defined as rising edge. If the byte is 0x00 then edge trigged software interrupt flag bit set (206) as shown in figure 4 and if it is not equal to 0x00 then it is treated as noise (205) as it will tell the microcontroller is after an edge the signal level is not maintain. The baud rate is set high so that even in a single byte after start bit if there is transition then that start bit is not treated as edge else treated as noise and is ignored.
Referring figure 4, shows actual signal with falling edge, two different patterns of receiving byte is shown. In first pattern it is shown that a byte 0b00000000 is received and treated as falling edge and serial receiver is generating an edge triggered interrupt for the same. In second pattern, due to the start bit, receiver receives a byte and the start bit is nothing but it is due to noise in the signal, therefore the byte received is not equal to 0b00000000 instead as shown in figure 3 obooo11111 is received and is ignored.
Finally, while the present disclosure has been described with reference to a few specific embodiments, the description is illustrative of the disclosure and is not to be construed as limiting the disclosure. Various modifications may occur to those skilled in the art

without departing from the true spirit and scope of the disclosure as defined by the appended claims.

We claim:
1. A method of generating edge triggered interrupt using universal asynchronous
receiver transmitter (UART) in a microcontroller, said method comprising acts of:
initialising serial communication of the microcontroller to a predetermined baud rate;
receiving input data byte by of the UART using the serial communication via receiver pin;
storing the received data in received buffer;
comparing the received data byte and break error bit with predefined values to detect an edge in the received data; and
generating an interrupt signal to interrupt the microcontroller upon detecting the edge.
2. The method as claimed in claim 1, wherein the received data byte is compared with the predefined value 0x00.
3. The method as claimed in claim 1, wherein the break error bit is compared with the predefined value one.
4. A processing device to generate edge triggered interrupt using universal asynchronous receiver transmitter (UART) comprises:
input interface circuit (2) connected to the communication ports of a processing device;
processing unit (5) comprising communication ports, on-chip UART (4), comparator and peripherals, said UART (4) receives input data (1) from the interface circuit (2) using receiver pin (3) and stores the input data in received buffer, said comparator compares the received data byte with predefined value to detect an edge and generate edge triggered interrupt.
5. The device as claimed in claim 4, wherein the input interface circuit (2) sends input data to the processing unit (5) at a predetermined rate.
6. The device as claimed in claim 4, wherein the processing unit (5) is selecting from a

group comprising microcontroller, field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC).
7. The device as claimed in claim 4, wherein the communication ports of the processing unit is selected from a group comprising serial ports and parallel ports.
8. The device as claimed in claims 4 and 7, wherein the UART receiver receives data using the serial communication port.
9. A system to generate edge triggered interrupt using universal asynchronous receiver transmitter (UART) comprises:
an universal asynchronous receiver transmitter (UART) (12) to receive input data
(11);
an interfacing circuit (13) to interface the UART with a processing unit; and processing unit (14) to receive the data from the UART (12), said processing
unit(14) comprises communication ports, comparator and peripherals, the comparator
compares the received data byte with predefined value to detect an edge in the
received data and generate edge triggered interrupt.
10. The system as claimed in claim 9, wherein the processing unit is selecting from a group comprising microcontroller, field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC).
11. The system as claimed in claim 9, wherein the communication ports of the processing unit is selected from a group comprising serial ports and parallel ports.
12. The system as claimed in claim 9, wherein the received data byte is stored in a received buffer of the UART (12).

13. A method to generate edge triggered interrupt using universal asynchronous receiver transmitter (UART), a device to generate edge triggered interrupt using universal asynchronous receiver transmitter (UART) and a system thereof as herein substantiated in the description along with accompanied drawings.