Description:RELATED APPLICATION
[0001] The present application claims priority to U.S. Non-Provisional Patent Application No. 17/556,751 filed on 20 December 2021 and titled “System, Method And Apparatus For High Level Microarchitecture Event Performance Monitoring Using Fixed Counters” the entire disclosure of which is hereby incorporated by reference.

BACKGROUND
[0002] Modern processors typically include performance monitoring capabilities to enable skilled users to perform debug and code analysis functions. In some processors, a top-down microarchitecture analysis (TMA) methodology is provided for use in identifying software performance issues. This TMA methodology is a hierarchical organization of event-based metrics that identifies dominant performance bottlenecks in an application. Its aim is to show, on average, how well processor pipeline(s) are utilized while running an application. However, current mechanisms for accessing this information can suffer from lack of precision and/or resource impacts.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] FIG. 1 is block diagram of a processor in accordance with an embodiment.
[0004] FIG. 2 is a flow diagram of a method in accordance with an embodiment.
[0005] FIGS. 3A and 3B illustrate a block diagram of a more specific exemplary in-order core architecture.
[0006] FIG. 4 is a block diagram of a processor according to embodiments of the invention.
[0007] FIG. 5 is a block diagram of a first more specific exemplary system in accordance with an embodiment of the present invention.
[0008] FIG. 6 is a block diagram of a SoC in accordance with an embodiment of the present invention.
[0009] FIG. 7 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention.
DETAILED DESCRIPTION
[0010] In various embodiments, a processor may be configured with multiple dedicated or fixed counters of a performance monitoring unit to enable counting of raw events of a highest hierarchical level of a multi-level performance monitoring methodology (also referred to herein equally as a “performance monitoring arrangement,” “performance monitoring organization,” and “performance monitoring system”). Although embodiments are applicable to any performance monitoring arrangement, a particular implementation described herein is for an Intel® Top-Down Microarchitecture Analysis (TMA) methodology. In this methodology, there can be multiple levels of performance metrics that may monitor from a highest level to a lowest level of a hierarchy. In different cases there may be 2, 3 or more levels of performance metrics.
[0011] In one or more examples, a set of fixed counters may be provided, each associated with a particular highest level performance metric, which according to the above TMA methodology is a TMA level 1 (L1). In this way, the need for allocating programmable counters for counting such metric information or obtaining the information through a performance metric model specific register (MSR) can be avoided.
[0012] Through these counters, a low-cost mechanism is realized to offload precious programmable counters. These fixed counters reduce multiplexing by allowing particular highest level events to be collected alongside programmable events (which may be programmed for lower level events). These fixed counters are very precise and fast to access, as they provide raw counts and have a size that may incur clearing on overflow at a relatively long duration, e.g., approximately 400 seconds.
, Claims:1. An apparatus comprising:
at least one core to execute instructions; and
a plurality of fixed counters coupled to the at least one core, the plurality of fixed counters to count events during execution on the at least one core, at least some of the plurality of fixed counters to count event information of a highest level of a hierarchical performance monitoring organization.