DESC:CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This applications claims priority to Indian Provisional Application No. 202241022013, filed on April 13, 2022, the entire contents of which are incorporated herein by reference.
FIELD
The present application generally relates to the field of electronic circuits and, more specifically, to optimization of low power states of an electronic device and associated apparatuses, systems, and methods.
BACKGROUND
[0002] Additionally, wired local area networks (LANs) may be a reliable network interface as compared to wireless LANs (WLANs) or wireless wide area networks (WWANs). Typically, in legacy systems, one or more physical layer (PHY) circuits may remain powered and actively attempting to detect the connection of a cable to a LAN port, regardless of whether such a cable is present or not.
In mobile systems, battery life may be considered an important parameter. Two use cases that relate to battery life may include: (1) How long a system can stay in standby mode without charging; and (2) The maximum battery life without charging for a typical system workload. During the daily usage of a mobile device, user behavior may exist in three generalized segments. A first segment may relate to user engagement, a second segment may relate to user short-term disengagement, and a third segment may relate to user long-term disengagement.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.
[0004] Figure 1 illustrates an example of a LAN port, in accordance with various embodiments.
[0005] Figure 2 illustrates an alternative view of the example LAN port of Figure 1, in accordance with various embodiments.
[0006] Figure 3 illustrates an alternative view of the example LAN port of Figure 1, in accordance with various embodiments.
[0007] Figure 4 depicts an example circuit diagram related to the LAN port of Figure 1, in accordance with various embodiments.
[0008] Figure 5 depicts a detailed view of a portion of the example circuit diagram of Figure 4, in accordance with various embodiments.
[0009] Figure 6 depicts an alternative example circuit diagram related to the LAN port of Figure 1, in accordance with various embodiments.
[0010] Figure 7 relates to an example flow chart for power state control, in accordance with various embodiments.
[0011] Figure 8 depicts a simplified example block diagram for power state control, in accordance with various embodiments.
[0012] Figure 9 depicts an example circuit diagram related to the example block diagram of Figure 8, in accordance with various embodiments.
[0013] Figure 10 depicts an example process flow related to power state control, in accordance with various embodiments.
Figure 11 illustrates a smart device or a computer system or a System-on-Chip (SoC) with apparatus and/or software for LAN cable detection, in accordance with some embodiments.
DETAILED DESCRIPTION
[0014] In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.
[0015] Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
[0016] The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/- 10% of a target value. Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
[0017] For the purposes of the present disclosure, the phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
[0018] The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
As used herein, the term “circuitry” may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. As used herein, “computer-implemented method” may refer to any method executed by one or more processors, a computer system having one or more processors, a mobile device such as a smartphone (which may include one or more processors), a tablet, a laptop computer, a set-top box, a gaming console, and so forth.
WIRED LAN POWER CONTROL
[0019] As previously noted, wired LANs may be a reliable network interface as compared to wireless LANs (WLANs) or wireless wide area networks (WWANs). Typically, in legacy systems, one or more physical layer (PHY) circuits may remain powered and actively attempting to detect the connection of a cable to a wired LAN port, regardless of whether such a cable is present or not. Specifically, the PHY circuitry may remain in a powered-on state (e.g., an S0ix active idle state or some other power state such as an Advanced Configuration and Power Interface (ACPI) S3, S4, or S5 power state) when other elements of the electronic device go into an unpowered state such as a G3 state, a PG3 state, or some other ACPI “off” or “low-power” power state). In some embodiments, this active monitoring may result in approximately 7-10 milliwatts (mW) of power loss if the PHY circuitry is in the S0ix power state.
[0020] One example of a wired LAN interface may be an Ethernet interface. In other embodiments, other examples of wired LAN interfaces may be used such as a peripheral component interconnect express (PCIe) interface, a universal chiplet interconnect express (UCIe) interface, medium dependent interface (MDI), or some other type of wired interface that allows for data communication between two electronic devices, or between two elements of an electronic device.
[0021] In the case of data centers, an increasing number of inter-chassis connections between different computing devices (e.g., different server blades, etc.) may be accomplished through a wired LAN interface. The wired LAN interface may be desirable because it may be relatively lower cost as compared to an optical interface, and may be more reliable than a wireless interface. The multiple connections of the wired LAN interface may be accomplished through use of a wired LAN router or switch. In general, the switch/router may come with a high density of wired ports that enable the use of the switch/router as the data center wired LAN interface requirements grow. As noted above, each port may consume approximately 7-10 mW of power when the electronic device is in a lower power (e.g., S0ix or other similar state). Therefore, having a large number of these ports may result in significant power consumption. As such, reducing the active monitoring of these ports may result in significant power and/or cost savings.
[0022] Embodiments herein relate to techniques and devices that may enable such power savings. Specifically, embodiments relate to a wired LAN port and associated logic or circuitry that passively senses the presence of a cable coupled with the wired LAN port. Because such passive sensing may be accomplished, the PHY circuitry may be put into an even lower power state (e.g., a G3 state, a PG3 state, a D3 COLD state, or some other “off” state), which may result in the above-described power savings.
[0023] Specifically, in embodiments a wired LAN port may have at least one additional pin that is unused for communication in accordance with the wired LAN protocol. When the cable is inserted into the wired LAN port, then the pin may be physically moved to complete an electrical circuit that is detected by the electronic device of which the wired LAN port is a part. In some embodiments, rather than a pin, a “push button” type structure may be included as part of the wired LAN port. The push button may be physically moved when the cable is inserted into the wired LAN port, and again complete a circuit that is detected by the electronic device. In another embodiment, the pin or push button may be part of a completed circuit that is opened when the cable is inserted into the wired LAN port.
[0024] In embodiments, the detection of the change in state (e.g., opening or closing) of the circuit may be accomplished through the use of a small electronic circuit that is configured to detect the change in state and drive the power enable/disable for the PHY circuitry (e.g., turn the PHY circuitry on or off based on the change in state).
[0025] Figures 1-3 depict an example of a wired LAN port 100 that includes such a push button 115. The LAN port may be, for example, an RJ45 port. Such a port 100 may be referred to as an “Ethernet port,” a “network port,” an adapter, a jack, etc.
[0026] The port 100 may include a housing 101 with an opening 102. The opening 102 may have a number of pins positioned therein. The opening 102 may be configured to receive a plug 125 of a cable and provide electrical communication with one or more pads of the plug 125 via the pins 103. That is, the pins 103 may communicatively mate with the pads of the plug. It will be understood that the plug 125 is a terminal end of a cable that may be part of, or coupled with, another element of the same or a different electronic device (e.g., another port or directly coupled to an element of an electronic device such as a printed circuit board (PCB)).
[0027] In the embodiment of Figures 1-3, the port 100 may include or be coupled with a signal pin 105 and a ground pin 110 (which may additionally or alternatively be referred to as a signal wire/ground wire). Specifically, the signal pin 105 may be communicatively coupled with one or more other elements or circuits of the electronic device, while the ground pin 110 may short to ground.
[0028] The port 100, as shown, may include a push button 115 that is configured to actuate a lever 120. In the specific embodiment shown, the lever 120 may be formed of a conductive metal material, while the button 115 may be formed of an insulative material such as plastic or some other material. When the plug 125 is inserted into the port, it may push the button 115 outward. This force may cause the lever 120 likewise to move outward and come into contact with the signal pin 105. When the lever 120 contacts the signal pin 105, it may close a circuit. When the plug 125 is removed from the port 100, the lever 120 may get disengaged from the signal pin 105.
[0029] As has been previously noted, the embodiments of Figures 1-3 is intended as one example embodiment, and other embodiments may include variations. For example, the specific configuration of the lever and/or push button, or the coupling of the lever with the signal pin, may be different in other embodiments. For example, in some embodiments the lever may be couplable with the ground pin rather than the signal pin. In some embodiments, pushing the push button may open rather than close the circuit. In some embodiments, the push button may be replaced with a pin of the port such as one of pins 103 that does not otherwise serve a communicative function in accordance with the protocol of the port 100. Other embodiments may vary.
[0030] Figures 4 and 5 depict an example circuit diagram related to the LAN port of Figure 1, in accordance with various embodiments. Specifically, Figure 4 depicts an electronic device 200. Such an electronic device may be, for example, a server blade, a laptop computer, a desktop computer, a mobile electronic device, or some other type of electronic device.
[0031] The electronic device 200 may include one or more system-on-chips (SoCs) 210 that are communicatively coupled with a display 205. The SoCs 210 may be, for example, a processor, a central processing unit (CPU), a graphics processing unit (GPU), a memory (e.g., a volatile or non-volatile memory such as a flash memory, a double data rate (DDR) memory, etc.), a multi-core processor, and/or some other type of SoC 210. The display 205 may be, for example, a touch screen, a non-touch screen, or some other type of display.
[0032] The electronic device 200 may be coupled with a wired LAN router/switch 215 via a cable 220. The cable 220 may be, for example, an Ethernet cable or some other type of wired LAN cable. Specifically, the cable 220 may include a plug such as plug 125 described above. In some embodiments, the router/switch 215 may be an element of the electronic device (e.g., contained within a same housing as some or all of the elements of the electronic device 200). In these embodiments, the cable 220 may likewise be at least partially within the housing of the electronic device 200. In other embodiments, the router/switch 215 may be physically separate from, and communicatively coupled with, the electronic device 200 by the cable 220.
[0033] In some embodiments, the electronic device 200 may include wired LAN circuitry 225. Figure 5 depicts a detailed example of the wired LAN circuitry 225.
[0034] Specifically, Figure 5 depicts a detailed example of the circuitry of a port 300, which may be similar to port 100. It will be understood that the circuitry depicted with respect to port 300 may be considered to be one example of such circuitry, and other ports may include different circuit diagrams including different numbers of pins, different connections between the pins, etc.
[0035] The port 300 may include a switch 310 that is coupled with a weak pull-up 305. The switch 310 may be considered analogous to the mechanism of the push button 115 and the lever 120 described above. That is, when the plug 125 is inserted into the port 100, the push button 115 may actuate the lever 120, thereby closing the switch 310. However, it will be reiterated that this is only one embodiment of such a switch, and other embodiments may vary as described above (e.g., using a pin instead of a push button, having a circuit default to closed rather than open, etc.).
[0036] The weak pull-up 305 may be a resistor that may provide a default state to the signal pin 105 as a logical “1” by the resistor pulled to the power supply. Once the cable is plugged in (e.g., the plug 125 is inserted into the port 100), closing the switch 310, the signal pin 105 and the ground pin 110 may short. This short may cause the line to move from a logical state of “1” to a logical state of “0,” thereby letting the system know that the cable is present. It will be recognized that, in other embodiments, the state change may be from a logical “0” to a logical “1,” dependent on the particular wiring of the system of which the port 100 is a part.
[0037] When the switch 310 is activated (e.g., closed), a signal may be transmitted to AND logic 315. Such a signal may be, for example, a “CABLE_DET” signal or some other type of signal. The AND logic 315 may be coupled with the SoC 210 and configured to receive a SLP_LAN signal from the SoC 210.
[0038] Generally, the SLP_LAN signal may be a signal provided by the SoC 210 that indicates that the wired LAN PHY circuitry 325 is in a powered-off state (e.g., a state where there is no Ethernet cable detected). Such a state may be the present if the system is using a WWAN or WLAN as a network interface. When the AND logic 315 receives the indication of SLP_LAN as well as the signal received from the switch 310, then the AND logic may provide a signal to the Power Switch 320 to begin waking up the wired LAN PHY circuitry 325. Specifically, based on the signal received from the AND logic 315, the power switch 320 may draw power from the system power supply 330, and provide that power to the wired LAN PHY circuitry 325. It will be noted that the wired LAN PHY circuitry 325 is depicted in Figures 4 and 5 as PHY-only, such as may be present in an integrated chip. In some embodiments the wired LAN PHY circuitry may additionally include medium access control (MAC) circuitry such as may be present in an integrated device.
Figure 6 depicts an example block diagram of an alternative circuit that includes elements similar to those of Figures 4 and 5. Specifically, in the embodiment of Figure 6, a sense circuit 400 may be coupled with a pin (R1/R2) of a port 405. Such a pin may be similar to one of pins 103 of port 100. Generally, the port 405 may be similar to port 100, but may not include elements such as the push button 115 and/or lever 120. Rather, this circuit diagram may relate to the embodiment wherein actuation of the pin 410 may close (or open) a circuit as described above.
SYSTEM POWER STATE CONTROL
[0039] As was previously noted, in mobile systems, battery life may be considered an important parameter. Two use cases that relate to battery life may include: (1) How long a system can stay in standby mode without charging; and (2) The maximum battery life without charging for a typical system workload. During the daily usage of a mobile device, user behavior may exist in three generalized segments. A first segment may relate to user engagement, a second segment may relate to user short-term disengagement, and a third segment may relate to user long-term disengagement.
[0040] Typically, the mobile system may be expected to spend approximately 30% of a 24-hour period (i.e., a day) in the user engagement segment. In this segment, it may be presumed that the user is actively interacting with the mobile device such as performing input events or otherwise manipulating the mobile device.
[0041] The mobile system may be expected to spend approximately 32% of the 24-hour period in the short-term disengagement segment. This segment relates to the user not interacting with the mobile device for a given time threshold. Such a time threshold may be, for example, between 5 minutes and 12 hours, although in other embodiments the time threshold may be longer or shorter. Generally, the short-term disengagement segment may correspond to a use case in which the user has walked away from the mobile device without performing a full shutdown of the mobile device. In this use case, the user may return within a relatively short time period (e.g., after the user has eaten lunch), and so it may be desirable to allow for a quick return to the active engagement segment.
[0042] The mobile system may be expected to spend approximately 38% of the 24-hour period in the long-term disengagement segment. This segment relates to the user not interacting with the mobile device for a time period longer than short-term disengagement segment (e.g., longer than 12 hours). This segment may correspond to the use case in which the user has walked away from the mobile device and is not expected to return quickly. Additionally or alternatively, this segment may relate to a situation in which a user has powered their system down in some way (e.g., closing the lid of a laptop computer, deactivating a mobile device, shutting down an operating system (OS) of an electronic device, etc.).
[0043] It will be noted that the 5-minute and 12-hour time thresholds are only provided herein as an example, and other systems may have longer or shorter time periods. For example, in some embodiments the time threshold between the short-term disengagement and the long-term disengagement segments may be 1 hour, 8 hours, etc.
[0044] Some systems may include mechanisms to enhance a user experience, for example user-detection sensors. When the system is in the second or third segments, if a user is detected, then the system may move to the user engagement segment. In order to accomplish this enhancement, the system may only be placed into a “sleep” type state (e.g., the S0ix state, the advanced configuration and power interface (ACPI) S4 or S5 state, or some other low power state) rather than a “powered-off” type state (e.g., a G3 state, a pseudo-G3 (PG3) state or some other powered-off state), regardless of whether the system is in the second or third segments. However, placement of the system into the sleep state rather than the powered-off state may result in significant power usage by active components of the mobile device such as systems-on-chip (SoCs) or other active components that are kept in the sleep state rather than the powered-off state, even if the system has been instructed (implicitly or explicitly) to move to the powered-off state.
[0045] Embodiments herein may resolve one or more of the above issues by allowing the active components (e.g., the SoCs or other components) of the mobile device to move into the powered-off state while the user detection circuitry remains in the sleep state. Specifically, during the second segment (e.g., short-term disengagement), active components of the mobile device may be placed into the powered-off state (e.g., a PG3 state) while the user detection circuitry may be placed into the sleep state (e.g., a S0ix state). These states may generate significant power savings on the order of between 50 to 75 milliwatts (mW) over the approximately 32% of the 24 hour time period. In other embodiments, the power savings can be up to 300 mW, which may result in a total power savings over six hours of approximately 1.8 Watt hours (Whr). Then, upon entrance into the third segment (either based on the time threshold being met or direction by the user), the user detection circuitry may be additionally placed into the powered-off state, which may result in an additional 10 mW of power savings over the approximately 32% of the 24 hour time period, resulting in even further time savings.
[0046] Significant advantages may be realized based on these embodiments. Specifically, the battery life of the mobile device may be extended without removing user experience features such as wake-on-motion, face unlock, etc. Specifically, for a 40 Watt-hour (WHr) battery, reducing the standby current from 80 mW to 60 mW may result in an additional 7 days of use before the battery of the mobile device will go to deep discharge in standby mode. As used herein, "deep discharge” may refer to a state related to a very low battery or dead battery. In this state, if a user wants to power on the device, the device may not power-on until the battery is charged with an external alternating current (AC) adaptor.
[0047] Figure 7 relates to an example flow chart for power state control, in accordance with various embodiments. It will be noted that the flow chart of Figure 7 is not intended to be exhaustive (e.g., including each and every logic loop), nor to necessarily describe the actions of a single element of the system (e.g., the logic of a power controller such as a power management controller (PMC) or an electronic controller (EC)). Rather, Figure 7 is intended to provide a high level description of the system power states for the sake of discussion herein. It will be recognized that, in other embodiments, the process flow may include more or fewer elements, elements performed in an order that is different than depicted, etc.
[0048] Generally, it may be considered that the process flow of Figure 7 may be performed by physical layer (PHY) circuitry, a PMC, an EC, a SoC that is communicatively coupled with user detection circuitry, and/or some combination thereof. More generally, the process flow may be performed by hardware, software, firmware, and/or some combination thereof. Such elements may be referred to herein with respect to the process flow of Figure 7 as “logic.” More specifically, in some embodiments the logic of Figure 7 may be performed by an EC such as EC 620 (described in greater detail below).
[0049] In embodiments, the system may be powered on at 505. Such a power-on may be based on a user opening the lid of a laptop computer, pressing a button on a mobile phone, pressing a power button of a laptop computer, or some other type of power-on.
[0050] As part of the power-on process, active elements of the system such as an SoC may be initialized at 505. Similarly, user detection circuitry may likewise be initialized at 505. The system may then be put into an active state at 510. For example, the active state may be an ACPI S0 state, while in other embodiments the active state may be some other active state.
[0051] The state of the system may then be monitored at 515. Specifically, it may be monitored whether the system is in the user engagement segment as described above (e.g., whether the user is actively using the system). If the user is actively using the system, then a loop may be created wherein the process flow returns to element 510. The check may be performed periodic\ally (e.g., every 100 milliseconds (ms) or according to some other time scale). In other embodiments, the check may be performed based on an interrupt (e.g., such as may be generated based on user use of the system) or some other factor.
[0052] If the system is not in the user engagement segment, then the logic may start/increment a timer at 520. Specifically, once it is detected that the user is not active or engaged with the system, then a timer may be started at 520. Such disengagement may be based on an input from an accelerometer that indicates that the system has been still. Additionally or alternatively, such disengagement may be based on a user not entering input to the system (e.g., using a touchscreen or some other system input), a camera that detects that the user is not within proximity of, or otherwise actively engaging with, the system, or some other factor.
[0053] The logic may then continue to identifying whether the system is in the short-term disengagement segment at 525 as described above. In other words, the logic may identify whether the user has interacted with the system within a given time threshold such as 5 minutes. If there has been no user interaction, but the time threshold has not elapsed, then the system may return to element 515 to identify whether user engagement has occurred. If it has not, then the timer may be incremented at 520 and the check may be performed again at 525.
[0054] However, if it is identified at 525 that the user disengagement has occurred for longer than the first time threshold, then the logic may proceed to 530 where the user detection circuitry is placed into a sleep (e.g., S0ix) state and the active element(s) of the system (e.g., one or more processors, SoCs, etc.) are placed into a powered-off (e.g., PG3) state.
[0055] The logic may then monitor at 535 for user activity/engagement. Specifically, the logic may monitor for an explicit indication of user presence such as the user pressing a power-button. Additionally or alternatively, the user detection circuitry may monitor for an indication of proximity/activity/engagement of a user. Such indication may be based on, for example, a camera detection the presence of the user within proximity of the system. In some embodiments, the camera (and/or logic) may additionally or alternatively include facial recognition circuitry or some other means of user identification. Because the user detection circuitry is only placed in the sleep state, such user detection may occur even though the active element(s) of the system are in the powered-off state.
[0056] If user activity/engagement is detected at 535, then the system may be placed in the active state at 510. However, if user activity/engagement is not detected at 535, then the timer may continue to increment at 540. A check may be performed at 545 to identify whether the time of user disengagement has exceeded a second threshold (e.g., 12 hours) as described above.
[0057] If the time of user disengagement has not exceeded the second time threshold, then the system may again check for user activity/engagement at 535. However, if the user disengagement has continued for a time beyond the second threshold, then the logic may continue to element 550 where the user detection circuitry is placed into the powered-off state until a system power-on/initialization is detected at 505.
[0058] Figure 8 depicts a simplified example block diagram of a circuit for power state control, in accordance with various embodiments. It will be recognized that the diagram of Figure 8 is intended as a highly simplified version of such a circuit, and not all connections or communication pathways may be shown in this diagram. For example, the communication between PG3 logic 625 and power source 635 is depicted as one-way communication, wherein real-world embodiments may allow for bidirectional communication along different circuit pathways between the PG3 logic 625 and the power source 635. Generally, the various elements may be implemented using some form of hardware, software, firmware, and/or some combination thereof.
[0059] In embodiments, an SoC such as SoC 615 may identify that there has been user inactivity/idleness, and provide an indication of such to an EC 620. Responsive to this indication, the EC 620 may start and/or monitor a timer as described previously with respect to Figure 7. Upon expiration of a first time threshold (e.g., the 5-minute time threshold described above), the EC 620 may provide a signal to power-off logic 625 and user detection circuitry power state control logic 640. Generally, the power-off logic may control system power when the system is being placed into the power-off state (e.g., PG3). The user detection circuitry power state control logic 640 may control the power state of the user detection circuitry 605.
[0060] As previously noted, the user detection circuitry 605 may include a user detection sensor such as a camera. In other embodiments, the user detection sensor may include an element such as a LiDAR, a radar, an accelerometer, a capacitive coupling able to detect a user’s proximity, and/or some other sensor element. The user detection circuitry 605 may additionally include logic capable of processing the input from the user detection sensor. Such logic may include logic for, for example, facial recognition or some other logic.
[0061] Based on the indication from the EC 620, the power-off logic 625 may direct a power source 635 of the system to put an active element of the system (e.g., SoC 610) into the power-off state (e.g., PG3). In some embodiments, the power source 635 may be or include a battery, a battery charging apparatus, an electronic coupling to an external power source (e.g., a wall outlet), and/or some other type of power source.
[0062] Similarly, based on the indication from the EC 620, the user detection circuitry power state control logic 640 may direct the user detection circuitry 605 to enter a sleep state such as an S0ix state or some other sleep or low-power state. In some embodiments, the power source 635 may be a power source such as a battery or an adapter. In embodiments, in the case of a sleep or power-off state, one or more voltage regulators may be controlled to reduce or eliminate power to the system of Figure 8, or a portion thereof. For example, as described herein, one or more voltage regulators may remove power to the SoC 610 to put the SoC 610 into the power-off state (e.g., the PG3 state) while power to elements such as the user detection circuitry 605 and/or the EC 620 remain “on” (e.g., in the S0ix state).
[0063] As previously described, when the user detection circuitry 605 may be configured to, while in the sleep state, identify the proximity/activity/engagement of a user of the mobile device. In this case, the user detection circuitry 605 may provide an indication of user presence to the EC 620. The EC 620 may be monitoring a timer (e.g., the timer described with respect to Figure 7 and initiated above based on the signal received from the SoC 615). If the second time threshold (e.g., the 12-hour time threshold) has not expired, then the EC 620 may instruct the power-off logic 625 and the user detection circuitry power state control logic 640 to wake the active elements of the system (e.g., SoC 610) and user detection circuitry 605, respectively.
[0064] The EC 620 may further be responsible for continuing to monitor the timer described above. Upon expiration of the second time threshold (e.g, the 12-hour time threshold), the EC 620 may instruction the user detection circuitry power state control logic 640 to place the user detection circuitry 605 into the powered-off state as described with respect to Figure 7.
[0065] Figure 9 depicts an example circuit diagram relate to the example block diagram of Figure 8, in accordance with various embodiments. Specifically, Figure 9 depicts specific circuit elements and communication pathways that may accomplish the functions described with respect to Figures 7 and 8. Specifically, Figure 9 may include SoC 715, EC 720, power-off logic (also referred to as “Pseudo-G3” or “PG3” logic) 725, user detection circuitry 705, user detection circuitry power state control logic 740, and an active element 710 (depicted as an SoC), which may be respectively similar to SoC 615, EC 620, power-off logic 625, user detection circuitry 605, user detection circuitry power state control logic 640, and active element 610. Figure 9 may further depict a power source 735 that is communicatively coupled with a battery charging logic 730. The power source 735 and battery charging logic 730 may together be similar to power source 635.
[0066] In this specific implementation, when the system is idle and/or the user has been disengaged for a duration less than the first threshold (e.g., 5 minutes), the user detection circuitry 705 may be operable to make the system to an active (e.g., S0) state from a system-idle state (e.g., one of S1-S4) upon detection of proximity/activity/engagement of a user to the mobile device as described above.
[0067] When the time threshold is between the first threshold and the second threshold (e.g., 12 hours), the active element 710 may be in the power-off state and the user detection circuitry 705 may be in the sleep state. In this case, upon detection of proximity/activity/engagement of a user, the user detection circuitry 705 may indicate user presence/usage to the EC 720 through provision of a signal such as CVF_INDICATION_EC. In turn, the EC 720 may provide an indication of the user activity to the user detection circuitry power control logic 740. Such an indication may be, for example, a CVF_PG3_entry signal. As a result the logic 740 may turn on a transistor such as transistor 741 (which may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET)). Activating the transistor 741 may turn off (e.g., power-off) the SoC 710 and associated components with the exception of, for example, a backup power (e.g., real-time clock (RTC)) power source to the SoC 710. Similarly, the power supply for the user detection circuitry 705 may switch to a low drop-out (LDO) power rail related to the PG3 state (as shown with respect to power source 735) from an active power rail related to the active state (e.g., an S0 power rail). Upon detecting user engagement/proximity/activity, the user detection circuitry 705 may provide an indication of such user engagement/proximity/activity to the EC 720 (e.g., via a CVF_INDICATION_EC signal), and the EC may wake the system by providing a PG3_entry and/or CVF_PG3_entry signal to logic 725 and logic 740, respectively.
[0068] When the time threshold being monitored by the EC 720 has exceeded the second threshold (e.g., 12 hours), then the EC 720 may put the user detection circuitry 705 into a power-off (e.g., PG3) state as described with respect to Figure 7. It will be noted that, in some embodiments, although the majority of elements in this state are in the power-off state, in some embodiments certain functional blocks such as the PG3 logic 725 and/or the EC 720 may remain in a power state higher than the PG3 state. More specifically, in embodiments, elements 720, 725, 730, and 735 may remain in a non-powered-off state higher than the sleep/PG3 state (e.g., S0ix or some other state) while the remaining elements depicted in Figure 7 may go to a sleep state (e.g., the PG3 state).
[0069] Figure 10 depicts an example process flow related to power state control, in accordance with various embodiments. In embodiments, the process flow may be performed, in whole or in part, by an EC such as EC 620 or 720 as described above.
[0070] The process may include detecting, at 805, that an electronic device is to be put in a powered-off state. Such detection may be based on user inactivity or device idleness as described above. Specifically, such detection may be based on elapsement of a time threshold such as the first time threshold (e.g., 5 minutes of idleness) as described above. In some embodiments the detection may be based on input from one or more of an SoC such as SoC 615/715 and/or input from user detection circuitry such as user detection circuitry 605/705.
[0071] The process may further include facilitating, at 810 based on the detection that the electronic device is to be put in the powered-off state, placement of an active element of the electronic device in the powered-off state. Such a powered-off state may be, for example, a PG3 state. The active element may be, for example, an SoC such as SoC 610/710. Facilitating placement of the active element in the powered-off state may include, for example, providing a direction to a power-off logic such as power-off logic 625/725, as described above.
[0072] The process may further include facilitating, at 815 based on the detection that the electronic device is to be put in the powered-off state, placement of user detection circuitry (e.g., user detection circuitry 605/705) into a low power state (e.g., a sleep state such as an S0ix state) that is different than the powered-off state (e.g., the PG3 state). Facilitating placement of the user detection circuitry into this state may include providing instructions to a logic such as logic 640/740.
It will be noted that this process is intended as an example process in accordance with some embodiments of the present disclosure, but other embodiments may vary. For example, other embodiments may include more or fewer elements, elements performed in an order different than that depicted, or element (e.g., element 810 and 815) performed at least partially concurrently. Other embodiments may vary.
EXAMPLE EMBODIMENTS
[0073] Figure 11 illustrates a smart device or a computer system or a System-on-Chip (SoC) with a port or circuit such as one of the ports or circuits described with respect to any of Figures 1-10, in accordance with some embodiments.
[0074] In some embodiments, device 1100 represents an appropriate computing device, such as a computing tablet, a mobile phone or smart-phone, a laptop, a desktop, an Internet-of-Things (IOT) device, a server, a wearable device, a set-top box, a wireless-enabled e-reader, or the like. It will be understood that certain components are shown generally, and not all components of such a device are shown in device 1100. The apparatus and/or software for controlling wake sources in a system to reduce power consumption in sleep state can be in the wireless connectivity circuitries 1131, PCU 1110, and/or other logic blocks (e.g., operating system 1152) that can manage power for the computer system.
[0075] In an example, the device 1100 comprises an SoC (System-on-Chip) 1101. An example boundary of the SoC 1101 is illustrated using dotted lines in Figure 11, with some example components being illustrated to be included within SoC 1101 – however, SoC 1101 may include any appropriate components of device 1100.
[0076] In some embodiments, device 1100 includes processor 1104. Processor 1104 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, processing cores, or other processing means. The processing operations performed by processor 1104 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, operations related to connecting computing device 1100 to another device, and/or the like. The processing operations may also include operations related to audio I/O and/or display I/O.
[0077] In some embodiments, processor 1104 includes multiple processing cores (also referred to as cores) 1108a, 1108b, 1108c. Although merely three cores 1108a, 1108b, 1108c are illustrated in Figure 11, processor 1104 may include any other appropriate number of processing cores, e.g., tens, or even hundreds of processing cores. Processor cores 1108a, 1108b, 1108c may be implemented on a single integrated circuit (IC) chip. Moreover, the chip may include one or more shared and/or private caches, buses or interconnections, graphics and/or memory controllers, or other components.
[0078] In some embodiments, processor 1104 includes cache 1106. In an example, sections of cache 1106 may be dedicated to individual cores 1108 (e.g., a first section of cache 1106 dedicated to core 1108a, a second section of cache 1106 dedicated to core 1108b, and so on). In an example, one or more sections of cache 1106 may be shared among two or more of cores 1108. Cache 1106 may be split in different levels, e.g., level 1 (L1) cache, level 2 (L2) cache, level 3 (L3) cache, etc.
[0079] In some embodiments, processor core 1104 may include a fetch unit to fetch instructions (including instructions with conditional branches) for execution by the core 1104. The instructions may be fetched from any storage devices such as the memory 1130. Processor core 1104 may also include a decode unit to decode the fetched instruction. For example, the decode unit may decode the fetched instruction into a plurality of micro-operations. Processor core 1104 may include a schedule unit to perform various operations associated with storing decoded instructions. For example, the schedule unit may hold data from the decode unit until the instructions are ready for dispatch, e.g., until all source values of a decoded instruction become available. In one embodiment, the schedule unit may schedule and/or issue (or dispatch) decoded instructions to an execution unit for execution.
[0080] The execution unit may execute the dispatched instructions after they are decoded (e.g., by the decode unit) and dispatched (e.g., by the schedule unit). In an embodiment, the execution unit may include more than one execution unit (such as an imaging computational unit, a graphics computational unit, a general-purpose computational unit, etc.). The execution unit may also perform various arithmetic operations such as addition, subtraction, multiplication, and/or division, and may include one or more an arithmetic logic units (ALUs). In an embodiment, a co-processor (not shown) may perform various arithmetic operations in conjunction with the execution unit.
[0081] Further, execution unit may execute instructions out-of-order. Hence, processor core 1104 may be an out-of-order processor core in one embodiment. Processor core 1104 may also include a retirement unit. The retirement unit may retire executed instructions after they are committed. In an embodiment, retirement of the executed instructions may result in processor state being committed from the execution of the instructions, physical registers used by the instructions being de-allocated, etc. Processor core 1104 may also include a bus unit to enable communication between components of processor core 1104 and other components via one or more buses. Processor core 1104 may also include one or more registers to store data accessed by various components of the core 1104 (such as values related to assigned app priorities and/or sub-system states (modes) association.
[0082] In some embodiments, device 1100 comprises connectivity circuitries 1131. For example, connectivity circuitries 1131 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and/or software components (e.g., drivers, protocol stacks), e.g., to enable device 1100 to communicate with external devices. Device 1100 may be separate from the external devices, such as other computing devices, wireless access points or base stations, etc.
[0083] In an example, connectivity circuitries 1131 may include multiple different types of connectivity. To generalize, the connectivity circuitries 1131 may include cellular connectivity circuitries, wireless connectivity circuitries, etc. Cellular connectivity circuitries of connectivity circuitries 1131 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, 3rd Generation Partnership Project (3GPP) Universal Mobile Telecommunications Systems (UMTS) system or variations or derivatives, 3GPP Long-Term Evolution (LTE) system or variations or derivatives, 3GPP LTE-Advanced (LTE-A) system or variations or derivatives, Fifth Generation (5G) wireless system or variations or derivatives, 5G mobile networks system or variations or derivatives, 5G New Radio (NR) system or variations or derivatives, or other cellular service standards. Wireless connectivity circuitries (or wireless interface) of the connectivity circuitries 1131 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), and/or other wireless communication. In an example, connectivity circuitries 1131 may include a network interface, such as a wired or wireless interface, e.g., so that a system embodiment may be incorporated into a wireless device, for example, a cell phone or personal digital assistant.
[0084] In some embodiments, device 1100 comprises control hub 1132, which represents hardware devices and/or software components related to interaction with one or more I/O devices. For example, processor 1104 may communicate with one or more of display 1122, one or more peripheral devices 1124, storage devices 1128, one or more other external devices 1129, etc., via control hub 1132. Control hub 1132 may be a chipset, a Platform Control Hub (PCH), and/or the like. Generally, the control hub 1132 may include one or more of the ports and/or wired LAN PHY circuitries described with respect to any one of the Figures 1-10.
[0085] For example, control hub 1132 illustrates one or more connection points for additional devices that connect to device 1100, e.g., through which a user might interact with the system. For example, devices (e.g., devices 1129) that can be attached to device 1100 include microphone devices, speaker or stereo systems, audio devices, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.
[0086] As mentioned above, control hub 1132 can interact with audio devices, display 1122, etc. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of device 1100. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display 1122 includes a touch screen, display 1122 also acts as an input device, which can be at least partially managed by control hub 1132. There can also be additional buttons or switches on computing device 1100 to provide I/O functions managed by control hub 1132. In one embodiment, control hub 1132 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in device 1100. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).
[0087] In some embodiments, control hub 1132 may couple to various devices using any appropriate communication protocol, e.g., PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus), Thunderbolt, High Definition Multimedia Interface (HDMI), Firewire, etc.
[0088] In some embodiments, display 1122 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with device 1100. Display 1122 may include a display interface, a display screen, and/or hardware device used to provide a display to a user. In some embodiments, display 1122 includes a touch screen (or touch pad) device that provides both output and input to a user. In an example, display 1122 may communicate directly with the processor 1104. Display 1122 can be one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment display 1122 can be a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.
[0089] In some embodiments, and although not illustrated in the figure, in addition to (or instead of) processor 1104, device 1100 may include Graphics Processing Unit (GPU) comprising one or more graphics processing cores, which may control one or more aspects of displaying contents on display 1122.
[0090] Control hub 1132 (or platform controller hub) may include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections, e.g., to peripheral devices 1124.
[0091] It will be understood that device 1100 could both be a peripheral device to other computing devices, as well as have peripheral devices connected to it. Device 1100 may have a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on device 1100. Additionally, a docking connector can allow device 1100 to connect to certain peripherals that allow computing device 1100 to control content output, for example, to audiovisual or other systems.
[0092] In addition to a proprietary docking connector or other proprietary connection hardware, device 1100 can make peripheral connections via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.
[0093] In some embodiments, connectivity circuitries 1131 may be coupled to control hub 1132, e.g., in addition to, or instead of, being coupled directly to the processor 1104. In some embodiments, display 1122 may be coupled to control hub 1132, e.g., in addition to, or instead of, being coupled directly to processor 1104.
[0094] In some embodiments, device 1100 comprises memory 1130 coupled to processor 1104 via memory interface 1134. Memory 1130 includes memory devices for storing information in device 1100.
[0095] In some embodiments, memory 1130 includes apparatus to maintain stable clocking as described with reference to various embodiments. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory device 1130 can be a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment, memory 1130 can operate as system memory for device 1100, to store data and instructions for use when the one or more processors 1104 executes an application or process. Memory 1130 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of device 1100.
[0096] Elements of various embodiments and examples are also provided as a machine-readable medium (e.g., memory 1130) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1130) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).
[0097] In some embodiments, device 1100 comprises temperature measurement circuitries 1140, e.g., for measuring temperature of various components of device 1100. In an example, temperature measurement circuitries 1140 may be embedded, or coupled or attached to various components, whose temperature are to be measured and monitored. For example, temperature measurement circuitries 1140 may measure temperature of (or within) one or more of cores 1108a, 1108b, 1108c, voltage regulator 1114, memory 1130, a mother-board of SoC 1101, and/or any appropriate component of device 1100.
[0098] In some embodiments, device 1100 comprises power measurement circuitries 1142, e.g., for measuring power consumed by one or more components of the device 1100. In an example, in addition to, or instead of, measuring power, the power measurement circuitries 1142 may measure voltage and/or current. In an example, the power measurement circuitries 1142 may be embedded, or coupled or attached to various components, whose power, voltage, and/or current consumption are to be measured and monitored. For example, power measurement circuitries 1142 may measure power, current and/or voltage supplied by one or more voltage regulators 1114, power supplied to SoC 1101, power supplied to device 1100, power consumed by processor 1104 (or any other component) of device 1100, etc.
[0099] In some embodiments, device 1100 comprises one or more voltage regulator circuitries, generally referred to as voltage regulator (VR) 1114. VR 1114 generates signals at appropriate voltage levels, which may be supplied to operate any appropriate components of the device 1100. Merely as an example, VR 1114 is illustrated to be supplying signals to processor 1104 of device 1100. In some embodiments, VR 1114 receives one or more Voltage Identification (VID) signals, and generates the voltage signal at an appropriate level, based on the VID signals. Various type of VRs may be utilized for the VR 1114. For example, VR 1114 may include a “buck” VR, “boost” VR, a combination of buck and boost VRs, low dropout (LDO) regulators, switching DC-DC regulators, constant-on-time controller-based DC-DC regulator, etc. Buck VR is generally used in power delivery applications in which an input voltage needs to be transformed to an output voltage in a ratio that is smaller than unity. Boost VR is generally used in power delivery applications in which an input voltage needs to be transformed to an output voltage in a ratio that is larger than unity. In some embodiments, each processor core has its own VR, which is controlled by PCU 1110a/b and/or PMIC 1112. In some embodiments, each core has a network of distributed LDOs to provide efficient control for power management. The LDOs can be digital, analog, or a combination of digital or analog LDOs. In some embodiments, VR 1114 includes current tracking apparatus to measure current through power supply rail(s).
[00100] In some embodiments, device 1100 comprises one or more clock generator circuitries, generally referred to as clock generator 1116. Clock generator 1116 generates clock signals at appropriate frequency levels, which may be supplied to any appropriate components of device 1100. Merely as an example, clock generator 1116 is illustrated to be supplying clock signals to processor 1104 of device 1100. In some embodiments, clock generator 1116 receives one or more Frequency Identification (FID) signals, and generates the clock signals at an appropriate frequency, based on the FID signals.
[00101] In some embodiments, device 1100 comprises battery 1118 supplying power to various components of device 1100. Merely as an example, battery 1118 is illustrated to be supplying power to processor 1104. Although not illustrated in the figures, device 1100 may comprise a charging circuitry, e.g., to recharge the battery, based on Alternating Current (AC) power supply received from an AC adapter.
[00102] In some embodiments, device 1100 comprises Power Control Unit (PCU) 1110 (also referred to as Power Management Unit (PMU), Power Controller, etc.). In an example, some sections of PCU 1110 may be implemented by one or more processing cores 1108, and these sections of PCU 1110 are symbolically illustrated using a dotted box and labelled PCU 1110a. In an example, some other sections of PCU 1110 may be implemented outside the processing cores 1108, and these sections of PCU 1110 are symbolically illustrated using a dotted box and labelled as PCU 1110b. PCU 1110 may implement various power management operations for device 1100. PCU 1110 may include hardware interfaces, hardware circuitries, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks), to implement various power management operations for device 1100.
[00103] In some embodiments, device 1100 comprises Power Management Integrated Circuit (PMIC) 1112, e.g., to implement various power management operations for device 1100. In some embodiments, PMIC 1112 is a Reconfigurable Power Management ICs (RPMICs) and/or an IMVP (Intel® Mobile Voltage Positioning). In an example, the PMIC is within an IC chip separate from processor 1104. The may implement various power management operations for device 1100. PMIC 1112 may include hardware interfaces, hardware circuitries, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks), to implement various power management operations for device 1100.
[00104] In an example, device 1100 comprises one or both PCU 1110 or PMIC 1112. In an example, any one of PCU 1110 or PMIC 1112 may be absent in device 1100, and hence, these components are illustrated using dotted lines.
[00105] Various power management operations of device 1100 may be performed by PCU 1110, by PMIC 1112, or by a combination of PCU 1110 and PMIC 1112. Specifically, the PCU 1110 and/or PMIC 1112 may include one or more of the elements depicted with respect to Figures 8 or 9. For example, PCU 1110 and/or PMIC 1112 may select a power state (e.g., P-state) for various components of device 1100. For example, PCU 1110 and/or PMIC 1112 may select a power state (e.g., in accordance with the ACPI (Advanced Configuration and Power Interface) specification) for various components of device 1100. Merely as an example, PCU 1110 and/or PMIC 1112 may cause various components of the device 1100 to transition to a sleep state, to an active state, to an appropriate C state (e.g., C0 state, or another appropriate C state, in accordance with the ACPI specification), etc. In an example, PCU 1110 and/or PMIC 1112 may control a voltage output by VR 1114 and/or a frequency of a clock signal output by the clock generator, e.g., by outputting the VID signal and/or the FID signal, respectively. In an example, PCU 1110 and/or PMIC 1112 may control battery power usage, charging of battery 1118, and features related to power saving operation.
[00106] The clock generator 1116 can comprise a phase locked loop (PLL), frequency locked loop (FLL), or any suitable clock source. In some embodiments, each core of processor 1104 has its own clock source. As such, each core can operate at a frequency independent of the frequency of operation of the other core. In some embodiments, PCU 1110 and/or PMIC 1112 performs adaptive or dynamic frequency scaling or adjustment. For example, clock frequency of a processor core can be increased if the core is not operating at its maximum power consumption threshold or limit. In some embodiments, PCU 1110 and/or PMIC 1112 determines the operating condition of each core of a processor, and opportunistically adjusts frequency and/or power supply voltage of that core without the core clocking source (e.g., PLL of that core) losing lock when the PCU 1110 and/or PMIC 1112 determines that the core is operating below a target performance level. For example, if a core is drawing current from a power supply rail less than a total current allocated for that core or processor 1104, then PCU 1110 and/or PMIC 1112 can temporality increase the power draw for that core or processor 1104 (e.g., by increasing clock frequency and/or power supply voltage level) so that the core or processor 1104 can perform at higher performance level. As such, voltage and/or frequency can be increased temporality for processor 1104 without violating product reliability.
[00107] In an example, PCU 1110 and/or PMIC 1112 may perform power management operations, e.g., based at least in part on receiving measurements from power measurement circuitries 1142, temperature measurement circuitries 1140, charge level of battery 1118, and/or any other appropriate information that may be used for power management. To that end, PMIC 1112 is communicatively coupled to one or more sensors to sense/detect various values/variations in one or more factors having an effect on power/thermal behavior of the system/platform. Examples of the one or more factors include electrical current, voltage droop, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, etc. One or more of these sensors may be provided in physical proximity (and/or thermal contact/coupling) with one or more components or logic/IP blocks of a computing system. Additionally, sensor(s) may be directly coupled to PCU 1110 and/or PMIC 1112 in at least one embodiment to allow PCU 1110 and/or PMIC 1112 to manage processor core energy at least in part based on value(s) detected by one or more of the sensors.
[00108] Also illustrated is an example software stack of device 1100 (although not all elements of the software stack are illustrated). Merely as an example, processors 1104 may execute application programs 1150, Operating System 1152, one or more Power Management (PM) specific application programs (e.g., generically referred to as PM applications 1158), and/or the like. PM applications 1158 may also be executed by the PCU 1110 and/or PMIC 1112. OS 1152 may also include one or more PM applications 1156a, 1156b, 1156c. The OS 1152 may also include various drivers 1154a, 1154b, 1154c, etc., some of which may be specific for power management purposes. In some embodiments, device 1100 may further comprise a Basic Input/output System (BIOS) 1120. BIOS 1120 may communicate with OS 1152 (e.g., via one or more drivers 1154), communicate with processors 1104, etc.
[00109] For example, one or more of PM applications 1158, 1156, drivers 1154, BIOS 1120, etc. may be used to implement power management specific tasks, e.g., to control voltage and/or frequency of various components of device 1100, to control wake-up state, sleep state, and/or any other appropriate power state of various components of device 1100, control battery power usage, charging of the battery 1118, features related to power saving operation, etc.
[00110] In some embodiments, battery 1118 is a Li-metal battery with a pressure chamber to allow uniform pressure on a battery. The pressure chamber is supported by metal plates (such as pressure equalization plate) used to give uniform pressure to the battery. The pressure chamber may include pressured gas, elastic material, spring plate, etc. The outer skin of the pressure chamber is free to bow, restrained at its edges by (metal) skin, but still exerts a uniform pressure on the plate that is compressing the battery cell. The pressure chamber gives uniform pressure to battery, which is used to enable high-energy density battery with, for example, 20% more battery life.
[00111] In some embodiments, pCode executing on PCU 1110a/b has a capability to enable extra compute and telemetries resources for the runtime support of the pCode. Here pCode refers to a firmware executed by PCU 1110a/b to manage performance of the SoC 1101. For example, pCode may set frequencies and appropriate voltages for the processor. Part of the pCode are accessible via OS 1152. In various embodiments, mechanisms and methods are provided that dynamically change an Energy Performance Preference (EPP) value based on workloads, user behavior, and/or system conditions. There may be a well-defined interface between OS 1152 and the pCode. The interface may allow or facilitate the software configuration of several parameters and/or may provide hints to the pCode. As an example, an EPP parameter may inform a pCode algorithm as to whether performance or battery life is more important.
[00112] This support may be done as well by the OS 1152 by including machine-learning support as part of OS 1152 and either tuning the EPP value that the OS hints to the hardware (e.g., various components of SoC 1101) by machine-learning prediction, or by delivering the machine-learning prediction to the pCode in a manner similar to that done by a Dynamic Tuning Technology (DTT) driver. In this model, OS 1152 may have visibility to the same set of telemetries as are available to a DTT. As a result of a DTT machine-learning hint setting, pCode may tune its internal algorithms to achieve optimal power and performance results following the machine-learning prediction of activation type. The pCode as example may increase the responsibility for the processor utilization change to enable fast response for user activity, or may increase the bias for energy saving either by reducing the responsibility for the processor utilization or by saving more power and increasing the performance lost by tuning the energy saving optimization. This approach may facilitate saving more battery life in case the types of activities enabled lose some performance level over what the system can enable. The pCode may include an algorithm for dynamic EPP that may take the two inputs, one from OS 1152 and the other from software such as DTT, and may selectively choose to provide higher performance and/or responsiveness. As part of this method, the pCode may enable in the DTT an option to tune its reaction for the DTT for different types of activity.
[00113] Some non-limiting Examples of various embodiments are presented below.
[00114] Example 1 includes a power control module for use in an electronic device, wherein the power control module is to: detect that the electronic device is to be put in a powered-off state; facilitate, based on the detection that the electronic device is to be put in the powered-off state, placement of an active element of the electronic device in the powered-off state; and facilitate, based on the detection that the electronic device is to be put in the powered-off state, placement of user detection circuitry into a low power state that is different than the powered-off state.
[00115] Example 2 includes the power control module of example 1, and/or some other example herein, wherein the detection that the electronic device is to be put in a powered-off state is based on a detection, by the power control module, that the electronic device has been idle for a first time period that is longer than a first time threshold.
[00116] Example 3 includes the power control module of example 2, and/or some other example herein, wherein the power control module is further to facilitate, based on a detection that the electronic device has been idle for a second time period that is longer than a second time threshold, placement of the user detection circuitry into the powered-off state, wherein the second time threshold is longer than the first time threshold.
[00117] Example 4 includes the power control module of any of examples 1-3, and/or some other example herein, wherein the powered off state is a PG3 state.
[00118] Example 5 includes the power control module of any of examples 1-4, and/or some other example herein, wherein the low power state is a S0ix state.
[00119] Example 6 includes the power control module of any of examples 1-5, and/or some other example herein, wherein the active element is a processor of the electronic device.
[00120] Example 7 includes the power control module of any of examples 1-6, and/or some other example herein, wherein the user detection circuitry is related to a camera configured to detect proximity of a user to the electronic device.
[00121] Example 8 includes the power control module of any of examples 1-7, and/or some other example herein, wherein the power control module is further to: detect, from the user detection circuitry, an indication of proximity of a user to the electronic device; and facilitate, based on the indication, placement of the active element into an active power state that is different from the powered-off state.
[00122] Example 9 includes the power control module of example 8, and/or some other example herein, wherein the active power state is an S0 state.
[00123] Example 10 includes a wired local area network (LAN) communication port comprising: an opening to receive a plug; a signal pin; a ground pin; and an actuator positioned at least partially within the opening, such that when the plug is inserted into the opening, the actuator is moved and electrically coupled with one of the signal pin or the ground pin.
[00124] Example 11 includes the wired LAN communication port of example 10, and/or some other example herein, wherein the communication port is an Ethernet port.
[00125] Example 12 includes the wired LAN communication port of any of examples 10-11, and/or some other example herein, wherein the actuator is a lever positioned within a side of a body of the communication port.
[00126] Example 13 includes the wired LAN communication port of any of examples 10-12, and/or some other example herein, wherein the actuator is a pin of the port that is configured to make contact with an electrical contact of the plug when the plug is positioned within the opening.
[00127] Example 14 includes the wired LAN communication port of example 13, and/or some other example herein, wherein the pin is unused for data communication between the communication plug and the port.
[00128] Example 15 includes the wired LAN communication port of any of examples 10-14, and/or some other example herein, wherein, when the actuator is electrically coupled with the one of the signal pin or the ground pin, the signal pin and the ground pin are electrically shorted.
[00129] Example 16 includes a circuit for use with a wired local area network (LAN) communication port, wherein the circuit comprises: wired LAN physical layer (PHY) circuitry coupled with the wired LAN communication port; logic to: identify a first signal that indicates that the wired LAN communication port is powered down; identify a second signal that indicates that a physical switch of the wired LAN communication port has been closed; and generate a third signal that indicates the presence of the first and second signals; and a power switch to provide, based on receipt of the third signal, power to the wired LAN PHY circuitry.
[00130] Example 17 includes the circuit of example 16, and/or some other example herein, wherein the second signal is generated by the wired LAN communication port based on a plug being inserted into the wired LAN communication port.
[00131] Example 18 includes the circuit of any of examples 16-17, and/or some other example herein, wherein the second signal is generated based on physical movement of a switch that is located at least partially within a housing the wired LAN communication port.
[00132] Example 19 includes the circuit of any of examples 16-18, and/or some other example herein, wherein the second signal is generated based on physical movement of a pin of the wired LAN communication port.
[00133] Example 20 includes the circuit of any of examples 16-19, and/or some other example herein, wherein the second signal is a change in logical state of a signal wire of the communication port based on closure of the physical switch.
[00134] Example 21 includes the circuit of any of examples 16-20, and/or some other example herein, wherein the second signal is a CABLE_DET signal.
[00135] Example 22 includes the circuit of any of examples 16-21, and/or some other example herein, wherein the first signal is a SLP_LAN signal.
[00136] Example 23 includes the circuit of any of examples 16-22, and/or some other example herein, wherein the wired LAN PHY circuitry is an element of a PHY chip.
[00137] Example 24 includes the circuit of any of examples 16-23, and/or some other example herein, wherein the wired LAN PHY circuitry is an element of an integrated device that includes PHY circuitry and medium access control (MAC) circuitry.
[00138] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional elements.
[00139] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.
[00140] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.
[00141] In addition, well-known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.
[00142] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.
,CLAIMS:1. A power control module for use in an electronic device, wherein the power control module is to:
detect that the electronic device is to be put in a powered-off state;
facilitate, based on the detection that the electronic device is to be put in the powered-off state, placement of an active element of the electronic device in the powered-off state; and
facilitate, based on the detection that the electronic device is to be put in the powered-off state, placement of user detection circuitry into a low power state that is different than the powered-off state.

2. The power control module of claim 1, wherein the detection that the electronic device is to be put in a powered-off state is based on a detection, by the power control module, that the electronic device has been idle for a first time period that is longer than a first time threshold.

3. The power control module of claim 2, wherein the power control module is further to facilitate, based on a detection that the electronic device has been idle for a second time period that is longer than a second time threshold, placement of the user detection circuitry into the powered-off state, wherein the second time threshold is longer than the first time threshold.

4. The power control module of claim 1, wherein the powered off state is a PG3 state.

5. The power control module of claim 1, wherein the low power state is a S0ix state.

6. The power control module of claim 1, wherein the active element is a processor of the electronic device.

7. The power control module of claim 1, wherein the user detection circuitry is related to a camera configured to detect proximity of a user to the electronic device.

8. The power control module of claim 1, wherein the power control module is further to:
detect, from the user detection circuitry, an indication of proximity of a user to the electronic device; and
facilitate, based on the indication, placement of the active element into an active power state that is different from the powered-off state.

9. The power control module of claim 8, wherein the active power state is an S0 state.

10. A wired local area network (LAN) communication port comprising:
an opening to receive a plug;
a signal pin;
a ground pin; and
an actuator positioned at least partially within the opening, such that when the plug is inserted into the opening, the actuator is moved and electrically coupled with one of the signal pin or the ground pin.

11. The wired LAN communication port of claim 10, wherein the communication port is an Ethernet port.

12. The wired LAN communication port of claim 10, wherein the actuator is a lever positioned within a side of a body of the communication port.

13. The wired LAN communication port of claim 10, wherein the actuator is a pin of the port that is configured to make contact with an electrical contact of the plug when the plug is positioned within the opening.

14. The wired LAN communication port of claim 13, wherein the pin is unused for data communication between the communication plug and the port.

15. The wired LAN communication port of claim 10, wherein, when the actuator is electrically coupled with the one of the signal pin or the ground pin, the signal pin and the ground pin are electrically shorted.

16. A circuit for use with a wired local area network (LAN) communication port, wherein the circuit comprises:
wired LAN physical layer (PHY) circuitry coupled with the wired LAN communication port;
logic to:
identify a first signal that indicates that the wired LAN communication port is powered down;
identify a second signal that indicates that a physical switch of the wired LAN communication port has been closed; and
generate a third signal that indicates the presence of the first and second signals; and
a power switch to provide, based on receipt of the third signal, power to the wired LAN PHY circuitry.

17. The circuit of claim 16, wherein the second signal is generated by the wired LAN communication port based on a plug being inserted into the wired LAN communication port.

18. The circuit of claim 16, wherein the second signal is generated based on physical movement of a switch that is located at least partially within a housing the wired LAN communication port.

19. The circuit of claim 16, wherein the second signal is generated based on physical movement of a pin of the wired LAN communication port.

20. The circuit of claim 16, wherein the second signal is a change in logical state of a signal wire of the communication port based on closure of the physical switch.

21. The circuit of claim 16, wherein the second signal is a CABLE_DET signal.

22. The circuit of claim 16, wherein the first signal is a SLP_LAN signal.

23. the circuit of claim 16, wherein the wired LAN PHY circuitry is an element of a PHY chip.

24. The circuit of claim 16, wherein the wired LAN PHY circuitry is an element of an integrated device that includes PHY circuitry and medium access control (MAC) circuitry.