FORM -2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE
Specification
(See Section 10; rule 13)
AN ARRANGEMENT AND METHOD FOR SENSING INTERFERENCE DUE TO NOISE IN AN ELECTRONIC
CIRCUIT
DHOOT TRANSMISSION PRIVATE LIMITED
an Indian Company of 15 km. Stone, Gut no 100, Farola, Paithan Road,
Aurangabad-431105, Maharashtra, India.
Inventor:
1. Thombre Rajendra
The following specification particularly describes the invention and the manner in which
it is to be performed

FIELD OF THE DISCLOSURE
The present disclosure generally relates to arrangements for sensing interference due to noise in an electronic circuit.
Particularly, the present disclosure relates to an electronic system with Serial Peripheral Interface used to reduce discrete component count in an electronic control unit, which is immune to noise pick-up and data corruption.
BACKGROUND
Generally, in a circuit arrangement to reduce the number of I/O lines and discrete components and to save board size, serial peripheral interface (SPI) enabled Master-Slave configuration is used, wherein master is a logic controller and slave can be power MOSFETs or sensors such as direction sensor or acceleration sensor.
Communication interface between master and slave is through following I/O pins: master out- slave in (DO/MOSI), master in- slave out (DI/MISO), clock (CLK) and slave select (SS), wherein all the inputs and outputs are synchronized with respect to CLK. However, such conventional circuit arrangements are prone to malfunction due to noise such as electromagnetic or electrostatic pick-up in harsh environment. For example in the case of an automobile, pick on CLK line due to repetitive ignition sparks, data pattern may become unreadable. Also, if these conventional SPI based devices are used to drive a headlamp and a blinker, a slight malfunction may put a rider's life at risk. A SPI based sensor may provide an undesired output in any undesired condition which may lead to wrong indication or a hazard to a rider.
The above-mentioned problems occur due to: • unintelligent slave device;

• unavailability of system and method to detect and correct errors between SPI master and slave device;
• high impendence of digital input pin makes CLK and signal lines prone to pick up noise from other system components; and
• high level spark plug noise in automobiles.
Accordingly, there is need of a system to avoid malfunction generated due to noise interference. Further, there is need of a system that is reliable against any malfunction on CLK and signal lines of an electronics circuit having serial peripheral interface configuration.
OBJECTS
Some of the objects of the system of the present disclosure, which at least one embodiment herein satisfies, are as follows:
It is an object of the present disclosure to ameliorate one or more problems of the prior art or to at least provide a useful alternative.
An object of the present disclosure is to provide an arrangement which is immune to electromagnetic interference, electrostatic noise and pick-up on clock (CLK) line.
Another object of the present disclosure is to provide an arrangement immune to noise pick-up on CLK and data lines of SPI communication interface.
Further, an object of the present disclosure is to provide a system that is reliable against any malfunction on CLK and signal lines of SPI communication interface using control and communication logic.

Other objects and advantages of the system of the present disclosure will be more apparent from the following description when read in conjunction with the accompanying figures, which are not intended to limit the scope of the present disclosure.
SUMMARY
In accordance with an embodiment of the present disclosure, there is provided an arrangement for sensing interference due to noise in an electronic circuit having at least a master device communicating with at least one slave device. The arrangement includes:
• at least one communication channel that facilitates communication between the master device and the at least one slave device;
• at least one impedance element that reduces impedance of the at least one communication channel; and
• at least one comparator that detects short circuit condition by comparing potential, generated due to noise, of the at least one communication channel with a predefined reference voltage and send a detection signal to the master device for selectively disabling communication between the master device and the at least one slave device.
In accordance with an embodiment, the at least one impedance element is at least one resistor.
In accordance with the present disclosure, the communication channel is configured at a predefined potential.

Each of the resistors includes two terminals, one of the terminals is electrically , connected to the communication channel and other terminal is configured at a potential lower than the predefined potential.
In accordance with an embodiment, the arrangement includes an analog feedback channel.
The analog feedback channel facilitates communication of a multiplexed output from at least two slave devices or at least two elements of slave devices to the master device.
The comparator includes two input ports and a output port, one of the input port is electrically connected to the analog feedback channel and other input port is configured at the reference voltage, the output port is electrically connected to an interrupt port of the master device.
The comparator is an analog comparator.
The comparator send the detection signal to the master device for selectively disabling at least one of an output element and an input element within the at least one slave device.
In accordance with an embodiment, there is provided a method for sensing interference due to noise in an electronic circuit having a master device communicating with at least one slave. The method includes the following steps:
• comparing voltage, on an analog feedback channel, with a reference voltage;
• sending an interrupt signal to an interrupt pin of the master device; and

• selectively disabling communication between the master device and the at least one slave device based on the interrupt signal.
BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
The arrangement of the present disclosure will now be explained in relation to the non-limiting accompanying drawings, in which:
Figure 1 illustrates a prior art circuit arrangement of a serial peripheral interface having a Master device communicating with a slave device;
Figure 2 illustrates an arrangement to sense interference due to noise in a serial peripheral interface configuration having a master device and a slave device, in accordance with an embodiment of the present disclosure; and '
Figure 3 illustrates an arrangement to sense interference due to noise in a serial peripheral interface configuration having a master device and two slave devices, in accordance with an embodiment of the present disclosure.
DETAILED DESCRIPTION
The arrangement to sense interference due to noise in a serial peripheral interface configuration of the present disclosure will now be described with reference to the accompanying drawings which do not limit the scope and ambit of the disclosure. The description provided is purely by way of example and illustration.
The embodiments herein and the various features and advantageous details thereof are explained with reference to the non-limiting embodiments in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments

herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein.
The description hereinafter, of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the embodiments as described herein.
Figure 1 illustrates a prior art circuit arrangement 10 of a SPI having a master device 12 communicating with a slave device 14. Generally, the Master device 12 refers to an SPI controller and the slave device 14 refers to an SPI enabled power MOSFET. The master device 12 and the slave device 14 are interfaced with four digital signal lines where series resistor R is used to limit emission related issues. Also, slew rate of signal and CLK pins can be controlled by the master device 12 and the slave device 14 to reduce emission, but the circuit arrangement 10 as a whole is not immune to electromagnetic interface and electrostatic discharges. The circuit arrangement 10 also lacks concrete method to detect and correct communication errors which can be easily detected in a case where the master device 12 and the slave device 14 both are intelligent devices and an error checking and correction mechanism is present in the master device 12 and the

slave device 14. Lack of error correction and detection mechanism makes the prior art circuit arrangement 10 prone to malfunction in harsh environment with EMI (Electromagnetic interference) and ESD (Electrostatic discharge) and is a common problem related to edge trigger circuit and capacitor filters may not be used due to high switching speed of signal and CLK lines.
Accordingly, to ameliorate one or more problems of the prior art or to at least provide a useful alternative, an arrangement 100 to avoid malfunction generated due to interference of noise is illustrated. In accordance with the present disclosure, an electronic arrangement to sense interference due to noise in a serial peripheral interface configuration is disclosed. The electronic arrangement is immune to noise pick-up and data corruption on SPI lines using at least an analog feedback channel, for comparing actual load status with status stored in at least one register of the slave device and at least one interrupt port of the master device to warn master device in case of a short-circuit condition and using read at least twice and write once logic to avoid decision and diagnostic errors due to malfunction on communication channel and CLK lines.
Referring to Figure 2, the system 100 includes a master device 102 and a slave device 104. The slave device 104includes at least one SPI communication buffer register 106, at least one SPI communication control register 108 and at least one power MOSFET 110.
In accordance with an embodiment of the present disclosure, at least one resistor R2 is electrically connected in parallel to internal impedance of each digital pin of SPI communication which reduces total impedance of each communication channel below the value of R2. R2 is chosen such that it does not have any loading effect on the communication channels. In the case of EMI or ESD, due to low impendence of communication channels low energy pick-ups on input and CLK lines does not cause signal levels to go beyond a predefined threshold

window and hence causes no effect on existing communication between the master device 102 and the slave device 104.
As, the system 100 is immune to EMI or ESD pick-ups, the system 100 does not caters any malfunction on communication channels. In accordance with an embodiment of the present disclosure, the master device 102 communicates with the slave device 104 with the SPI data lines and clock lines, at least one analog pin Ai and at least one interrupt pin of the master device 102. The interrupt pin is driven by a comparator 112 which compares instantaneous load wattage with the predetermined threshold reference voltage for short circuit determination. Figure 2 also illustrates a SPI slave and possible internal structure including the at least one SPI communication buffer register 106, the at least one SPI communication control register 108 and the at least one power MOSFET110.
Following are the bi-directional read instructions from the master device 102 to the buffer register 106: Read Instructions:
Read instruction from buffer register for status of actual function
1) Read from buffer 106, status of actual function save as datal;
2) Read from buffer 106, status of actual function save as data 2; 3)EX-ORDatal&Data2;

4) If (Datal Ex-OR Data 2) = 0, Return(O); and
5) Else Return (1).
Following are the write instructions from the buffer register 106 to the communication control register 108:
Write Instructions:
Write instruction to write into control register 108, 1) Write Datal into Buffer 106;

2) Read buffer 106 using read instructions;
3) If read instruction returns (0), write command Data 2 to transfer Datal into Control register 108 using step 1 to 3; and
4) Else follow instructions 1 to 3.
Short Circuit Detection
Short circuit bit is set in the control register 108 with output short to ground and which is further used by master device 102 to shut down the power MOSFET 110. Generally, a number of times the short circuit status bit is corrupted due to EMI and ESD. Such corruption of data may cause a wrong decision to shut down certain critical functions which can put the system and user life at risk.
To avoid such a situation, at least one comparator 112 is used to compare if short circuit bit set in control register 108 is due to short circuit at the output of MOSFET 110 or is a result of data corruption due to EMI or ESD conditions. In one embodiment, the comparator 112 is an analog comparator. Analog feedback channel Ai is a multiplexed pin for N number of MOSFETs 110 within slave device 104. The comparator 112 compares voltage on the feedback channel Ai with a predefined reference voltage. When voltage on the feedback channel Ai exceeds beyond the predetermined threshold voltage, the comparator 112 provides a pulse output to the interrupt port INT of the master device 102. In embodiment, the comparator 112 is an integral part of the master device 112. In an alternate embodiment, the comparator 112 is electrically connected externally to the master device 102, as shown in Figure 2.
The method for short circuit detection is as follows:
1) Read control register 108 status bits using read instructions;
2) Turn On the channel for which short circuit bit is set;

3) Check for interrupt on INT port of the master device 102;
4) If interrupt received, shutdown the corresponding channel;
5) Else restore corresponding control register 108 short circuit status bit.
In an alternate embodiment of the present disclosure, as shown in Figure 3, an arrangement 200 to avoid malfunction generated due to noise interference (is disclosed. The arrangement 200 includes a plurality of slave devices 104. Sensors may be connected together to form a complete system such as body control unit in an automobile for driving headlamps and other loads such as starter, blinkers, horns, illumination, parking lamps by using an SPI enabled MOSFET by taking small signal inputs (low current switching inputs) from non-contact / contact type switches. Additional sensors such as a direction sensor /an acceleration sensor/a gyrometer sensor may be connected to the slave device 114 of the arrangement 200. Upon knowing desired turn direction from switches and estimating actual turn direction from the direction or acceleration and gyrometer, auto/self-cancellation of blinkers, flashers may be achieved. In one embodiment, the direction sensor/ acceleration sensor/ gyrometer sensor is within the controller.
TECHNICAL ADVANCEMENTS AND ECONOMICAL SIGNIFICANCE
The technical advancements offered by the system of the present disclosure which add to the economic significance of the disclosure include the realization
of:
• a system which is immune to electromagnetic interference, electrostatic noise and pick-up on CLK line;
• a system immune to noise pick-up on CLK and signal pins on SPI communication;
• a system that can be used for diagnostic purpose; and

• a system that is reliable against any malfunction on CLK and signal lines of SPI communication interface using control and communication logic.
Throughout this specification the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element, integer or step, or group of elements, integers or steps, but not the exclusion of any other element, integer or step, or group of elements, integers or steps.
The use of the expression "at least" or "at least one" suggests the use of one or more elements or ingredients or quantities, as the use may be in the embodiment to achieve one or more of the desired objects or results.
Any discussion of documents, acts, materials, devices, articles or the like that has been included in this specification is solely for the purpose of providing a context for the disclosure. It is not to be taken as an admission that any or all of these matters form part of the prior art base or were common general knowledge in the field relevant to the disclosure as it existed anywhere before the priority date of this application.
The numerical values mentioned for the various physical parameters, dimensions or quantities are only approximations and it is envisaged that the values higher/lower than the numerical values assigned to the parameters, dimensions or quantities fall within the scope of the disclosure, unless there is a statement in the specification specific to the contrary.

WE CLAIM:
1. An arrangement for sensing interference due to noise in an electronic circuit having at least a master device communicating with at least one slave device, said arrangement comprising:
• at least one communication channel adapted to facilitate communication between the master device and the at least one slave device;
• at least one impedance element adapted to reduce impedance of said at least one communication channel; and
• at least one comparator adapted to detect short circuit condition by comparing potential, generated due to noise, of said at least one communication channel with a predefined reference voltage and send a detection signal to said master device for selectively disabling communication between the master device and the at least one slave device.

2. The arrangement as claimed in claim 1, wherein said at least one impedance element is at least one resistor.
3. The arrangement as claimed in claim 1, wherein said communication channel is configured at a predefined potential.
4. The arrangement as claimed in any of the preceding claims, wherein each of said resistor includes two terminals, one of said terminals is electrically connected to said communication channel and other terminal is configured at a potential lower than said predefined potential.
5. The arrangement as claimed in claim I further includes an analog feedback channel.
6. The arrangement as claimed in claim 5, wherein said analog feedback channel facilitates communication of a multiplexed output from at least two slave devices to said master device.

7. The arrangement as claimed in claim 1 and claim 3, wherein said comparator includes two input ports and a output port, one of said input port is electrically connected to said analog feedback channel and other input port is configured at said reference voltage, said output port is electrically connected to an interrupt port of said master device.
8. The arrangement as claimed in claim 1, wherein said comparator is an analog comparator.
9. The arrangement as claimed in claim 1, wherein said comparator send said detection signal to said master device for selectively disabling at least one of an output element and an input element within the at least one slave
device.
10.A method for sensing interference due to noise in an electronic circuit having a master device communicating with at least one slave, said method comprising the following steps:
• comparing voltage, on an analog feedback channel, with a reference voltage;
• sending an interrupt signal to an interrupt pin of the master device; and
• selectively disabling communication between the mater device and the at least one slave device based on said interrupt signal.