Claims:What is claimed is:
1. A system to obtain finite gain and noise of an electrocardiogram (ECG) amplifier, comprising:
a computing device may include an electrocardiogram simulator configured to analyze the performance of at least one operational trans-conductance amplifier by simulating using cadence virtuoso analog design environment at 0.18 ??m, 0.5 µm and 0.9 µm CMOS technology nodes, wherein the electrocardiogram simulator configured to provide an improved performance at 0.18 µm CMOS technology.
2. The system of claim 1, wherein the electrocardiogram simulator comprises at least comb-c filter.

3. The system of claim 2, wherein the at least comb-c filter constructed with the at least one operational trans-conductance amplifier and at least one capacitor that makes it suitable for implementation of monolithic integrated circuits (ICs).

4. The system of claim 2, wherein the comb filter is configured to eliminate undesired signals of fundamental frequency of 60 Hz in ECG signal.

5. The system of claim 1, wherein the electrocardiogram simulator increases the width of at least one transistor and at least one channel length at higher technology nodes to increase passage of current through the transistor for overall gain and phase of at least one operational trans-conductance amplifier . , Description:TECHNICAL FIELD
[001] The present disclosure generally relates to the field of electrocardiogram signal processing system. More particularly, the present disclosure relates to a system to obtain finite gain and noise of an electrocardiogram amplifier at standard complementary metal-oxide-semiconductor (CMOS) technology.

BACKGROUND
[002] The computerized electroencephalogram (EEG), electrocardiogram (ECG), and magneto-encephalogram (MEG) systems widely used in clinical practices for processing and recording of different biomedical signals. The EEG and the ECG signals are categorized to weak signals with an amplitude up to 100 V and 5 mV for the EEG and the ECG signals, respectively. To preprocess an ECG signal, it is required to amplify the ECG signal by 10-100 times by using a preamplifier with low input noise. One of the most popular techniques of implementing an ECG monitoring system is the switched-capacitor (SC) integrated circuit topology. However, the sample & hold circuits of this switch-based topologies are not suitable for ECG monitoring due to its leakage problem and large time constant (in the order of millisecond or more). In order to remove the leakage, it is normally required to adopt the leakage-reducing mechanism in SC integrated circuitry and to reduce the device weight and size without compromising the quality of recording.

[003] In the light of the aforementioned discussion, there exists a need for a certain system with novel methodologies that would overcome the above-mentioned disadvantages.

SUMMARY
[004] The following presents a simplified summary of the disclosure in order to provide a basic understanding to the reader. This summary is not an extensive overview of the disclosure and it does not identify key/critical elements of the invention or delineate the scope of the invention. Its sole purpose is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later.

[005] An objective of the invention directed towards a supplying of bias current can provide an improved bandwidth performance at advanced CMOS technology.

[006] Another objective of the invention directed towards eliminating the undesired signals of fundamental frequency of 60 Hz in ECG signal.

[007] Another objective of the invention directed towards obtaining a large integrator loss by a ?nite resistance due to the channel length modulation.

[008] Another objective of the invention directed towards designing the amplifier to remove the selected frequencies of numerous signals by using the active comb filter.

[009] Another objective of the invention directed towards developing a gain and noise modelling approach using an analog comb filter based notch filter.

[0010] According to an exemplary aspect, a system to obtain finite gain and noise of an electrocardiogram (ECG) amplifier, comprising a computing device include an electrocardiogram simulator configured to analyze the performance of at least one operational trans-conductance amplifier by simulating using cadence virtuoso analog design environment at 0.18 ??m, 0.5 µm and 0.9 µm CMOS technology nodes.

[0011] According to another exemplary aspect, the electrocardiogram simulator configured to provide an improved performance at 0.18 µm CMOS technology.

BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 is a circuit diagram depicting a schematic representation of a computing system, in accordance with one or more embodiments.

[0013] FIG. 2A is an example diagram depicting a schematic representation of a first-order filter circuit, in accordance with one or more embodiments.

[0014] FIG. 2B is an example diagram depicting a schematic representation of an active OTA realization circuit, in accordance with one or more embodiments.

[0015] FIG. 3 is a block diagram depicting a schematic representation of a voltage mode OTA comb filter, in accordance with one or more embodiments.

[0016] FIG. 4 is a block diagram depicting a schematic representation of OTA noise representation using an input-output voltage noise source, in accordance with one or more embodiments.

[0017] FIG. 5 is an example diagram depicting a schematic representation of circuit schematics for simulation, in accordance with one or more embodiments.

[0018] FIG. 6A-6C are example diagrams depicting exemplary graphs of a phase vs frequency response, in accordance with one or more exemplary embodiments.

[0019] FIG. 7A-7c are example diagrams depicting exemplary graphs of a phase vs gain factor, in accordance with one or more exemplary embodiments.

[0020] FIG. 8 is a block diagram illustrating the details of a digital processing system in which various aspects of the present disclosure are operative by execution of appropriate software instructions.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0021] It is to be understood that the present disclosure is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The present disclosure is capable of other embodiments and of being practiced or of being carried out in various ways. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting.

[0022] The use of “including”, “comprising” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. The terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item. Further, the use of terms “first”, “second”, and “third”, and the like, herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

[0023] In current nanoscale technology, the portable device performance mostly depends on interconnects material used, transistor delay and power dissipation. The performance may be improved by increasing the chip size and scaling that further enhances the leakage power dissipation in the portable devices. Scaling also has opposing effect on RLC delay in VLSI circuits that causes an increase in resistivity of the metal interconnects and hence degrading the performance of the devices.

[0024] Referring to FIG. 1, is a block diagram 100 depicting a computing system, in accordance with one or more exemplary embodiments. The computing system 102 may include an electrocardiogram simulator 104. The electrocardiogram simulator 104 may be configured to identify a low trans-conductance value in the order of nano-amperes per volt, the integrated devices (ICs) are normally operated in the subthreshold region. The electrocardiogram simulator 104 may be configured to obtain finite gain and noise of an electrocardiogram (ECG) amplifier at 0.18 µm, 0.5 µm and 0.9 µm standard CMOS technology node. The electrocardiogram simulator 104 may be configured to integrate a first-order filter in higher-order filter circuit to demonstrate the performance and to further acquire the circuit specifications according to the requirement of ECG diagnosis.

[0025] Referring to FIG. 2A is an example diagram 200a depicting a schematic representation of a first-order filter circuit, in accordance with one or more embodiments. The diagram 200a comprises a series resistor 202, voltage source 204, and a load capacitor 206. The voltage source 204 of the series resistor 202 may be transformed into current source by Norton’s equivalent circuitry. However, to realize an active filter, the real OTA’s circuits can be used to replace the passive components as illustrated in Fig. 2B. The filter circuit incorporates an equivalent grounded resistor and an input voltage-to-current transducer of OTA based on the closed-loop configuration. Its transfer function can be defined as

[0026] In an embodiment, the system presents an active Comb-C filter. The Comb-C filter may be constructed with all OTAs and capacitors. All the PMOS and NMOS transistors are designed at 0.18 µm, 0.5 µm and 0.9 µm CMOS technology nodes. The bias current of this analog circuit is primarily controlled by the controlling voltage of the OTA. The performance is analyzed for different factors of transistor channel length and width. It is observed that, the ECG performance increases in terms of gain, bandwidth and noise at advanced technology node but the effective bandwidth reduces for lesser channel length. However, the bandwidth at 0.18 µm technology node (i.e., for advanced VLSI system) may be increased for an increase in bias current of OTA. Therefore, the portable OTA based ECG system can provide an improved performance at 0.18 µm CMOS technology.

[0027] Referring to FIG. 2B is a circuit diagram 200b depicting a schematic representation of an active OTA realization circuit, in accordance with one or more embodiments. The modelling of OTA nonlinearity is an important factor to analyze the performance of the first order filter. The several non-linear effects such as nonlinear output current for different input pairs, finite output resistance of current sink/source, etc may be observed to design the active filter in the active OTA realization circuit. Therefore, it is almost impossible to estimate the system performance without considering the effect of non-linear models. The non-linear model primarily includes the modelling of intrinsic noise and finite gain of the OTA based filter circuit. The modelling of these factors are discussed in following sub-sections. The sub-sections may include OTA finite gain, OTA noise.

[0028] In general, the infinite gain of an OTA may be obtained from the transfer function. However, in practical circuit, a large integrator loss can be happened by a finite resistance that is again due to the channel length modulation. It further influences the overall response of the filter circuit. Therefore, considering the output response of OTA as 1/g0, the transfer function of Fig. 2B can be expressed as

[0029] Referring to FIG. 3 is a circuit diagram 300 depicting a schematic representation of a voltage mode OTA comb filter, in accordance with one or more embodiments. The general architecture of the voltage-mode OTA comb filter is designed to analyze the OTA finite gain. The diagram 300 comprises an active network 301a, and a passive network 301b. The active network 301a comprises internal nodes 302a-302n, input trans-conductors 304a-304n, feed forward and feedback trans-conductors 306a-306n, feed forward trans-conductors 308a-308n, output summer consisting of trans-conductors (Gmci, Gmo) 310a-310n. The passive network 301b comprises input capacitors 312a-312n, a grounded and floating capacitor Cij, where 1 = i < j = n.

[0030] Now, considering the voltage at each node xi, the trans-conductance gain (G) in matrix form can be expressed as

[0031] The modelling expression may be used to develop the basic behavioral model with a SIMULINK tool. The basic first-order filter may be designed and is integrated in higher-order filter circuit to demonstrate the performance and acquire the circuit specifications according to the requirement of ECG diagnosis.

[0032] The voltage mode OTA comb filter may be configured to obtain OTA finite gain and OTA noise. The large integrator loss can be happened by a ?nite resistance that is again due to the channel length modulation. It further influences the overall response of the ?lter circuit.

[0033] The performance of OTA may be primarily influenced by the two main sources of noise. The two main sources of noise may be a flicker and a thermal noise. The flicker noise may be defined as a noise system that primarily produces an inverse frequency with the power density curve. The flicker noise specifically impacts the trans-conductance of OTA at low frequency band. The other term of flicker noise is 1/f noise due to its inverse noise power spectral density to the frequency. On the other hand, thermal noise (also known as Johnson noise) is normally referred as the electronic noise generated by the thermal agitation of the charge carriers inside an electrical conductor at equilibrium. The agitation of the charge carriers may happen for any applied voltage. The output noise of OTA may be affected by these two types of noise factors in the ideal condition.

[0034] Referring to FIG. 4 is a block diagram 400 depicting a schematic representation of OTA noise representation using an input-output voltage noise source, in accordance with one or more embodiments. The diagram 400 comprises a noise of a spectral density Sn(f) 402, a CMOS trans-conductor (gm) 404. The noise of a CMOS trans-conductor with value gm 408 is primarily described by an equivalent input-referred noise-voltage source (vn). Therefore, the spectral density, Sn(f) can be modeled as

[0035] Where St and Sf are represented as thermal and flicker noise components. The magnitudes of these two parameters are primarily dependent on the trans-conductor topology and biasing.

[0036] According to the general noise equation in HSPICE Elements and Device Models Manual NLEV = 2 , the input 1/f noise power spectral density can be derived as

[0037] Where the coefficient and exponent constants of flicker noise are may be represented as KF and AF, respectively; Weff and Leff are may be the effective channel width and length of the transistors, respectively; the oxide capacitance per unit area may be represented by COX. Moreover, the power spectral density of input referred thermal noise may be modelled in terms of OTA trans-conductance gain (G) and can be expressed as

[0038] Where kb and T may represents the Boltzman’s constant and the absolute temperature, respectively. The value of ? may be primarily dependent on the operating region of a transistor. Most of the transistors of OTA are supposed to operate in subthreshold region in order to satisfy the low power and low frequency requirements of an OTA comb filter. Thus, the value of ? is chosen as (1/2?) for subthreshold operation. The typical value of ? is 0.7 and ? = 1/?, where ? represents the slope factor.

[0039] Referring to FIG. 5 is an example diagram 500 depicting a schematic representation of circuit schematics for simulation, in accordance with one or more embodiments. The diagram 500 comprises NMOS transistors 502a-502j, PMOS transistors 504a-504i, resistors (R1 and R2) 506a-506b, first supply voltage (??dd) 508a, second supply voltage (??ss) 508b, internal capacitors 510a-510b, and an input voltage (Vin) 512. The simulation is performed by using cadence virtuoso analog design environment at0.18 ??m, 0.5 µm and 0.9 µm CMOS Technology nodes. The supply voltages 508a-508b used for simulation are ??dd = 1.8 V and ??ss = -1.8 V. The input voltage (Vin) 512 is chosen as 1V sine wave signal for simulation purpose. The values of the internal capacitors C1 and C2 510a-510b are chosen as 5µF and 21 nF, respectively. The resistors R1 and R2 506a-506b are the mismatch between the resistors and can affect only on the gain factor. The variable resistance (R2) 506b may be adjusted to 100 kO by biasing the current of corresponding OTA circuit. Therefore, the input-output voltage relationship of the OTA can be established as,

[0040] The dimensions of MOS Transistors at different technology nodes may be represented as:

Transistor Name & type Channel width (µm) Channel Length (µm) Technology Node (µm)
NMOS: M1, M2, M3, M8, M9, M11, M12A, M12B, M16, and M17 1.8 0.18 0.18
5 0.5 0.5
9 0.9 0.9
PMOS: M4, M5, M6, M7, M10, M13, M14A, M14B, and M15 4.5 0.18 0.18
12.5 0.5 0.5
22.5 0.9 0.9

[0041] The analysis of gain and noise are described using the transistor dimensions. The physiological signal such as ECG signal primarily contains the power line frequency and its harmonics along with the input signal. The proposed comb filter is designed to eliminate undesired signals of fundamental frequency of 60 Hz in ECG signal. As it is a low-frequency operation, a low noise and low distortion OTA is suitable for low-frequency application.

[0042] Referring to FIG. 6A-6C are example diagrams 600a-600c depicting exemplary graphs of a phase vs frequency response, in accordance with one or more exemplary embodiments. The exemplary graph 600a may include frequency (Hz) 602 on X-axis and phase (deg) 604 on Y-axis. The graph 600a may depict the phase margin analysis at 0.18 µm technology node. The graph 600b may depict the phase margin analysis at 0.5 µm technology node. The graph 600c may depict the phase margin analysis at 0.9 µm technology node.

[0043] Referring to FIG. 7A-7c are example diagrams 700a-700c depicting exemplary graphs of a phase vs gain factor, in accordance with one or more exemplary embodiments. The exemplary graph 700a may include frequency (Hz) 702 on X-axis and gain 704 on Y-axis. The graph 700a may depict the frequency response of OTA at 0.18 µm technology node. The graph 700b may depict the frequency response of OTA at 0.5 µm technology node. The graph 700c may depict frequency response of OTA at 0.9 µm technology node.

[0044] The overall cut-off frequency (i.e., 3 dB bandwidth) may be reduced at 0.18 µm technology node as compared to 0.5 and 0.9 µm technology nodes. The primary reason behind is that for an increase of transistor width and channel length (i.e., at higher technology nodes), the current through the transistor channel increases. It encouragingly increases the overall gain and phase of OTA based ECG system. However, for an increase in overall gain, the bandwidth (i.e., the frequency range the op-amp can respond to) may be decreased. At lower frequencies, due to a lesser electromagnetic induction effect, a less amount of signal is interfered inside and hence there is a better match between the effective amplitude of the output and the predicted gain. Thus, the overall bandwidth for 0.18 µm technology node is reduced. The quantitative values of bandwidth of OTA based different technology nodes are summarized in the following table:

Technology Nodes (µm) Gain (dB) Bandwidth (Hz)
0.18 36.21 105.72
0.5 9.78 136.20
0.9 7.73 283.36

[0045] The correct input source configuration is required to analyze the noise in OTA. Therefore, a voltage controlled voltage source (VCVS) may be considered for reference. The voltage controlled voltage source (VCVS) values have gains of ±0.5 to provide the differential gain to the circuit. However, for a common mode gain simulation, it is required to change the values from ±0.5 to 1. The common mode input terminal of the transistor may be considered for common mode input voltage to the circuit. In this case the common mode input terminal of the transistor is non-zero, but that is not always the case so it is required to put a non-zero input common-mode voltage for the noise analysis.

[0046] Here, the flicker and thermal noise is analyzed in cadence for different technology nodes of 0.18 µm, 0.5 µm and 0.9 µm. The quantitative values of noise at different technology nodes are summarized in the following table. The ECG system may perform an improved noise factor at 60 Hz frequency at 0.18 µm technology node.

Technology Nodes (µm) Flicker Noise (nV) Thermal Noise (µV)
0.18 1.16 5.62
0.5 2.76 47.86
0.9 9.18 68.31

[0047] Referring to FIG. 8, FIG. 8 is a block diagram 800 illustrating the details of a digital processing system 800 in which various aspects of the present disclosure are operative by execution of appropriate software instructions. The digital processing system 800 may correspond to the computing device 102 (or any other system in which the various features disclosed above can be implemented).

[0048] Digital processing system 800 may contain one or more processors such as a central processing unit (CPU) 1010, random access memory (RAM) 820, secondary memory 827, graphics controller 860, display unit 870, network interface 880, and input interface 890. All the components except display unit 870 may communicate with each other over communication path 850, which may contain several buses as is well known in the relevant arts. The components of Figure 8 are described below in further detail.

[0049] CPU 810 may execute instructions stored in RAM 820 to provide several features of the present disclosure. CPU 810 may contain multiple processing units, with each processing unit potentially being designed for a specific task. Alternatively, CPU 810 may contain only a single general-purpose processing unit.

[0050] RAM 820 may receive instructions from secondary memory 830 using communication path 850. RAM 820 is shown currently containing software instructions, such as those used in threads and stacks, constituting shared environment 825 and/or user programs 826. Shared environment 825 includes operating systems, device drivers, virtual machines, etc., which provide a (common) run time environment for execution of user programs 826.

[0051] Graphics controller 860 generates display signals (e.g., in RGB format) to display unit 1070 based on data/instructions received from CPU 810. Display unit 870 contains a display screen to display the images defined by the display signals. Input interface 890 may correspond to a keyboard and a pointing device (e.g., touch-pad, mouse) and may be used to provide inputs. Network interface 880 provides connectivity to a network (e.g., using Internet Protocol), and may be used to communicate with other systems (such as those shown in Figure 1) connected to the network.

[0052] Secondary memory 830 may contain hard drive 835, flash memory 836, and removable storage drive 837. Secondary memory 830 may store the data software instructions (e.g., for performing the actions noted above with respect to the Figures), which enable digital processing system 800 to provide several features in accordance with the present disclosure.

[0053] Some or all of the data and instructions may be provided on removable storage unit 840, and the data and instructions may be read and provided by removable storage drive 837 to CPU 810. Floppy drive, magnetic tape drive, CD-ROM drive, DVD Drive, Flash memory, removable memory chip (PCMCIA Card, EEPROM) are examples of such removable storage drive 837.

[0054] Removable storage unit 840 may be implemented using medium and storage format compatible with removable storage drive 837 such that removable storage drive 837 can read the data and instructions. Thus, removable storage unit 840 includes a computer readable (storage) medium having stored therein computer software and/or data. However, the computer (or machine, in general) readable medium can be in other forms (e.g., non-removable, random access, etc.).

[0055] In this document, the term "computer program product" is used to generally refer to removable storage unit 840 or hard disk installed in hard drive 835. These computer program products are means for providing software to digital processing system 800. CPU 810 may retrieve the software instructions, and execute the instructions to provide various features of the present disclosure described above.

[0056] The term “storage media/medium” as used herein refers to any non-transitory media that store data and/or instructions that cause a machine to operate in a specific fashion. Such storage media may comprise non-volatile media and/or volatile media. Non-volatile media includes, for example, optical disks, magnetic disks, or solid-state drives, such as storage memory 830. Volatile media includes dynamic memory, such as RAM 820. Common forms of storage media include, for example, a floppy disk, a flexible disk, hard disk, solid-state drive, magnetic tape, or any other magnetic data storage medium, a CD-ROM, any other optical data storage medium, any physical medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASH-EPROM, NVRAM, any other memory chip or cartridge.

[0057] Storage media is distinct from but may be used in conjunction with transmission media. Transmission media participates in transferring information between storage media. For example, transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise bus (communication path) 850. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave and infra-red data communications.

[0058] Reference throughout this specification to “one embodiment”, “an embodiment”, or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases “in one embodiment”, “in an embodiment” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0059] Furthermore, the described features, structures, or characteristics of the disclosure may be combined in any suitable manner in one or more embodiments. In the above description, numerous specific details are provided such as examples of programming, software modules, user selections, network transactions, database queries, database structures, hardware modules, hardware circuits, hardware chips, etc., to provide a thorough understanding of embodiments of the disclosure.

[0060] Although the present disclosure has been described in terms of certain preferred embodiments and illustrations thereof, other embodiments and modifications to preferred embodiments may be possible that are within the principles and spirit of the invention. The above descriptions and figures are therefore to be regarded as illustrative and not restrictive.

[0061] Thus the scope of the present disclosure is defined by the appended claims and includes both combinations and sub-combinations of the various features described hereinabove as well as variations and modifications thereof, which would occur to persons skilled in the art upon reading the foregoing description.