Claims:1) A processor implemented method comprising:
obtaining one or more parameters and one or more corresponding values pertaining to at least one application under test (AUT);
generating a first set of arrays based on an analysis being performed on said one or more parameters and said one or more corresponding values, wherein two or more arrays in said first set of arrays comprises elements that are unique from each other;
identifying two or more arrays from said first set of arrays to obtain a second set of arrays, wherein two or more arrays from said second set of arrays comprises pairwise interacting elements that are unique from each other;
interchanging said pairwise interacting elements across said two or more arrays in said second set of arrays to obtain a third set of arrays; and
combining two or more arrays from said third set of arrays to form an optimized covering array.
2) The processor implemented method of claim 1, further comprising generating one or more optimized test designs pertaining to said at least one AUT based on said optimized covering array.
3) The processor implemented method of claim 1, wherein said pairwise interacting elements when interchanged across said second set of arrays form pairwise interacting elements in said third set of arrays that are unique from each other.
4) The processor implemented method of claim 3, wherein said pairwise interacting elements in said third set of arrays are greater in number as compared to said unique pairwise interacting elements in said second set of arrays.
5) The processor implemented method of claim 1, wherein said unique pairwise interacting elements are interchanged across said second set of arrays to eliminate from duplicating pairwise interacting elements.
6) The processor implemented method of claim 1, wherein combining two or more arrays from said third set of arrays to form an optimized covering array comprises stacking said two or more arrays from said third set of arrays in at least one of one or more sequences and one or more orientations.
7) A system, comprising:
a memory storing instructions, and one or more parameters and one or more corresponding values pertaining to at least one application under test (AUT);
one or more communication interfaces; and
a hardware processor coupled to said memory through said one or more communication interfaces, wherein said hardware processor is configured by said instructions to execute:
a first array generating module that generates a first set of arrays based on an analysis being performed on said one or more parameters and said one or more corresponding values, wherein two or more arrays in said first set of arrays comprises elements that are unique from each other;
an array grading module that identifies two or more arrays from said first set of arrays to obtain a second set of arrays, wherein two or more arrays from said second set of arrays comprises pairwise interacting elements that are unique from each other;
an Elements Interchanging module that interchanges said pairwise interacting elements across said two or more arrays in said second set of arrays to obtain a third set of arrays; and
a covering array generating module that combines two or more arrays from said third set of arrays to form an optimized covering array.
8) The computer implemented system of claim 7, further comprising a test design generating module that generates one or more optimized test designs pertaining to said at least one AUT based on said optimized covering array.
9) The computer implemented system of claim 7, wherein said pairwise interacting elements when interchanged across said second set of arrays form pairwise interacting elements in said third set of arrays that are unique from each other.
10) The computer implemented system of claim 9, wherein said pairwise interacting elements in said third set of arrays are greater in number as compared to said unique pairwise interacting elements in said second set of arrays.
11) The computer implemented system of claim 7, wherein said unique pairwise interacting elements are interchanged across said second set of arrays to eliminate from duplicating pairwise interacting elements.
12) The computer implemented system of claim 7, wherein said covering array generating module combines two or more arrays from said third set of arrays to form an optimized covering array by stacking said two or more arrays from said third set of arrays in at least one of one or more sequences and one or more orientations.
, Description:As Attached