Claims:1. A processor implemented method, comprising:
obtaining a raster floor map pertaining to a specific volume;
converting the raster floor map to a vector floor map, wherein the vector floor map comprises one or more obstacle polygons;
dividing the vector floor map into a grid of cells;
automatically identifying, based on the one or more obstacle polygons, a set of valid cells and a set of invalid cells in the grid;
identifying, for each valid cell, a connectivity across one or more adjacent valid cells to obtain adjacency information for each valid cell; and
generating, using the adjacency information, one or more optimal paths for routing in the specific volume.

2. The processor implemented method of claim 1, wherein the one or more obstacle polygons are detected using an edge detection technique.

3. The processor implemented method of claim 1, wherein the one or more optimal paths comprise one or more valid cells, and wherein center of each valid cell is a vertex, and an interconnection between centers of two or more valid cells is indicative of an edge.

4. The processor implemented method of claim 1, wherein the set of invalid cells are automatically identified by determining at least one of (i) a presence of at least a portion of a cell in any of the one or more obstacle polygons, (ii) a degree of overlap of a cell on any of the one or more obstacle polygons.

5. A system comprising:
a memory storing instructions;
one or more communication interfaces; and
one or more hardware processors communicatively coupled to the memory using the one or more communication interfaces, wherein the one or more hardware processors are configured by the instructions to:
obtain a raster floor map pertaining to a specific volume,
convert the raster floor map to a vector floor map, wherein the vector floor map comprises one or more obstacle polygons,
divide the vector floor map into a grid of cells,
automatically identify, based on the one or more obstacle polygons, a set of valid cells and a set of invalid cells in the grid,
identify, for each valid cell, a connectivity across one or more adjacent valid cells to obtain adjacency information for each valid cell, and
generate, using the adjacency information, one or more optimal paths for routing in the specific volume.

6. The system of claim 5, wherein the one or more obstacle polygons are detected using an edge detection technique.

7. The system of claim 5, wherein the one or more optimal paths comprise one or more valid cells, and wherein center of each valid cell is a vertex, and an interconnection between centers of two or more valid cells is indicative of an edge.

8. The system of claim 5, wherein the set of invalid cells are automatically identified by determining at least one of (i) a presence of a cell in any of the one or more obstacle polygons, and (ii) an overlap of a cell on any of the one or more obstacle polygons.
, Description:FORM 2

THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENT RULES, 2003

COMPLETE SPECIFICATION
(See Section 10 and Rule 13)

Title of invention:
SYSTEMS AND METHODS FOR GENERATING OPTIMAL PATHS FOR ROUTING

Applicant:
Tata Consultancy Services Limited
A company Incorporated in India under the Companies Act, 1956
Having address:
Nirmal Building, 9th floor,
Nariman point, Mumbai 400021,
Maharashtra, India

The following specification particularly describes the embodiments and the manner in which it is to be performed.

TECHNICAL FIELD
[0001] The disclosure herein generally relate to techniques for optimal paths generation for routing, and, more particularly, to systems and methods for generating optimal paths for routing.

BACKGROUND
[0002] With the advancement of technology, computing devices, for example, mobile phones run a variety of applications, including navigation and route finding applications. Typically, such navigation and route finding applications rely on Global Positioning System (GPS) technology that provide directions for navigations. However, GPS data may not be useful since there may be instances of loss in signals from GPS satellites, and/or networks from service operators. For example, GPS signals may not be available or lack in penetration inside buildings and/or indoor space. Further, conventional navigation and route finding systems and techniques require manual processing of data to a large extent, which involves more man power to manually process data causing delay and sometimes ineffective in providing accurate data.

SUMMARY
[0003] Embodiments of the present disclosure present technological improvements as solutions to one or more of the above-mentioned technical problems recognized by the inventors in conventional systems. For example, in one aspect, a processor implemented method is provided. The method comprising obtaining a raster floor map pertaining to a specific volume; converting a raster floor map to a vector floor map, wherein the vector floor map comprises one or more obstacle polygons; dividing the vector floor map into a grid of cells; automatically identifying, based on the one or more obstacle polygons, a set of valid cells and a set of invalid cells in the grid; identifying, for each valid cell, a connectivity across one or more adjacent valid cells to obtain adjacency information for each valid cell; and generating, using the adjacency information, one or more optimal paths for routing in the specific volume.
[0004] In an embodiment of the present disclosure, the one or more obstacle polygons are detected using an edge detection technique. In an embodiment, the one or more optimal paths comprise one or more valid cells, and wherein center of each valid cell is a vertex, and an interconnection between center of two or more valid cells is indicative of an edge. In an embodiment of the present disclosure, the set of invalid cells are automatically identified by determining at least one of (i) a presence of at least a portion of a cell in any of the one or more obstacle polygons, (ii) a degree of overlap of a cell on any of the one or more obstacle polygons. In other words, a cell is identified as a valid cell, when the cell or a portion of the cell does not lie (or does not have an overlap) on (or in) the one or more obstacle polygons.
[0005] In another aspect, a system is provided. The system comprising: a memory storing instructions; one or more communication interfaces; one or more hardware processors communicatively coupled to the memory using the one or more communication interfaces, wherein the one or more hardware processors are configured by the instructions to: obtain a raster floor map pertaining to a volume, convert a raster floor map to a vector floor map, wherein the vector floor map comprises one or more obstacle polygons, divide the vector floor map into a grid of cells, automatically identify based on the one or more obstacle polygons, a set of valid cells and a set of invalid cells in the grid, identify, for each valid cell, a connectivity across one or more adjacent valid cells to obtain adjacency information for each valid cell, and generate, using the adjacency information, one or more optimal paths for routing in the volume.
[0006] In an embodiment, the one or more obstacle polygons are detected using an edge detection technique. In an embodiment, the one or more optimal paths comprise one or more valid cells, and wherein center of each valid cell is a vertex, and an interconnection between center of two or more valid cells is indicative of an edge. In an embodiment, the set of invalid cells are automatically identified by determining at least one of (i) a presence of a cell in any of the one or more obstacle polygons, and (ii) an overlap of a cell on any of the one or more obstacle polygons.
[0007] In yet another aspect, one or more non-transitory machine readable information storage mediums comprising one or more instructions is provided. The one or more instructions which when executed by one or more hardware processors causes obtaining a raster floor map pertaining to a volume; converting a raster floor map to a vector floor map, wherein the vector floor map comprises one or more obstacle polygons;
[0008] dividing the vector floor map into a grid of cells; automatically identifying, based on the one or more obstacle polygons, a set of valid cells and a set of invalid cells in the grid; identifying, for each valid cell, a connectivity across one or more adjacent valid cells to obtain adjacency information for each valid cell; and generating, using the adjacency information, one or more optimal paths for routing in the volume.
[0009] In an embodiment of the present disclosure, the one or more obstacle polygons are detected using an edge detection technique. In an embodiment, the one or more optimal paths comprise one or more valid cells, and wherein center of each valid cell is a vertex, and an interconnection between centers of two or more valid cells is indicative of an edge. In an embodiment of the present disclosure, the set of invalid cells are automatically identified by determining at least one of (i) a presence of at least a portion of a cell in any of the one or more obstacle polygons, (ii) a degree of overlap of a cell on any of the one or more obstacle polygons.
[0010] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, serve to explain the disclosed principles:
[0012] FIG. 1 illustrates an exemplary block diagram of a system for generating optimal paths for routing in a volume according to an embodiment of the present disclosure.
[0013] FIG. 2 illustrates an exemplary flow diagram of a processor implemented method for generating optimal paths for routing in a volume using the system of FIG. 1 according to an embodiment of the present disclosure.
[0014] FIG. 3 is an exemplary view of the raster floor map to vector floor map conversion according to an embodiment of the present disclosure.
[0015] FIG. 4 is an exemplary view of the vector floor map that is divided into a grid of cells according to an embodiment of the present disclosure.
[0016] FIG. 5 is an exemplary view of the vector floor map with one or more valid cells and one or more invalid cells according to an embodiment of the present disclosure.
[0017] FIGS. 6A-6B are exemplary views of valid cell and connectivity of the valid cell across the one or more adjacent valid cells according to an embodiment of the present disclosure.
[0018] FIG. 7 shows a user interface of illustrating an optimal path (or shortest route) generated by the system 100 of FIG. 1 from a source to a destination according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS
[0019] Exemplary embodiments are described with reference to the accompanying drawings. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. Wherever convenient, the same reference numbers are used throughout the drawings to refer to the same or like parts. While examples and features of disclosed principles are described herein, modifications, adaptations, and other implementations are possible without departing from the spirit and scope of the disclosed embodiments. It is intended that the following detailed description be considered as exemplary only, with the true scope and spirit being indicated by the following claims.
[0020] Referring now to the drawings, and more particularly to FIG. 1 through 7, where similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments and these embodiments are described in the context of the following exemplary system and/or method.
[0021] FIG. 1 illustrates an exemplary block diagram of a system 100 for generating optimal paths for routing in a volume according to an embodiment of the present disclosure. In an embodiment, the system 100 includes one or more processors 104, communication interface device(s) or input/output (I/O) interface(s) 106, and one or more data storage devices or memory 102 operatively coupled to the one or more processors 104. The one or more processors 104 that are hardware processors can be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuitries, and/or any devices that manipulate signals based on operational instructions. Among other capabilities, the processor(s) is configured to fetch and execute computer-readable instructions stored in the memory. In an embodiment, the system 100 can be implemented in a variety of computing systems, such as laptop computers, notebooks, hand-held devices, workstations, mainframe computers, servers, a network cloud and the like.
[0022] The I/O interface device(s) 106 can include a variety of software and hardware interfaces, for example, a web interface, a graphical user interface, and the like and can facilitate multiple communications within a wide variety of networks N/W and protocol types, including wired networks, for example, LAN, cable, etc., and wireless networks, such as WLAN, cellular, or satellite. In an embodiment, the I/O interface device(s) can include one or more ports for connecting a number of devices to one another or to another server.
[0023] The memory 102 may include any computer-readable medium known in the art including, for example, volatile memory, such as static random access memory (SRAM) and dynamic random access memory (DRAM), and/or non-volatile memory, such as read only memory (ROM), erasable programmable ROM, flash memories, hard disks, optical disks, and magnetic tapes. In an embodiment, one or more modules (not shown) of the system 100 can be stored in the memory 102.
[0024] FIG. 2, with reference to FIG. 1, illustrates an exemplary flow diagram of a processor implemented method for generating optimal paths for routing in a volume according to an embodiment of the present disclosure. In an embodiment, the system 100 comprises one or more data storage devices or the memory 102 operatively coupled to the one or more hardware processors 104 and is configured to store instructions for execution of steps of the method by the one or more processors 104. The steps of the method of the present disclosure will now be explained with reference to the components of the system 100 as depicted in FIG. 1, and the flow diagram. In an embodiment of the present disclosure, at step 202, the one or more processors 104 obtain a raster floor map pertaining to a specific volume. In an embodiment, the volume may comprise, but is not limited to an indoor space (home, office, meeting rooms, and the like), an outdoor space, an auditorium, a ball room, or combinations thereof.
[0025] In an embodiment of the present disclosure, at step 204, the one or more processors 104 convert the raster floor map to a vector floor map, wherein the vector floor map comprises one or more obstacle polygons. FIG. 3, with reference to FIGS. 1-2, is an exemplary view of the raster floor map to vector floor map conversion according to an embodiment of the present disclosure. For example, available floor maps for a building are mostly in raster form: an image (*.jpg, *.png, etc.) or embedded in a Portable Document Format (PDF). This image needs to be converted to vector form, and the system 100 uses polygon representation for all the obstacles depicted in the floor map. To achieve this, the system 100 implements one or more edge detection technique, which may be based on one or more parameter(s) for example, but not limited to, brightness cutoff, etc. As shown in FIG. 3, the raster image of the floor map is converted to the multi-polygon represented vector floor map. As can be seen, the obstacle polygons represent non-walkable areas of the vector floor map.
[0026] In an embodiment of the present disclosure, at step 206, the one or more processors 204 divide the vector floor map into a grid of cells. FIG. 4, with reference to FIGS. 1 through 3, is an exemplary view of the vector floor map that is divided into a grid of cells according to an embodiment of the present disclosure. Adjacency representation of the map is derived from its vector form generated above. In order to derive that information, the vector floor map is divided into a grid of cells (e.g., small squares). The length of a side of a cell square may be denoted as CL. A sample cell structure embedded on a part of the vector floor map is shown in FIG. 4.
[0027] In an embodiment of the present disclosure, at step 208, the one or more processors 204 automatically identify, based on the one or more obstacle polygons, a set of valid cells and a set of invalid cells in the grid. FIG. 5, with reference to FIGS. 1 through 4, is an exemplary view of the vector floor map with one or more valid cells and one or more invalid cells according to an embodiment of the present disclosure. The one or more valid cells are indicated by an unshaded region 502, and the one or more invalid cells are indicated by a shaded region 504 in FIG. 5. In an embodiment of the present disclosure, at step 210, the one or more processors 204 identify, for each valid cell, a connectivity across one or more adjacent valid cells to obtain adjacency information for each valid cell. FIGS. 6A-6B are exemplary views of valid cell and connectivity of the valid cell across the one or more adjacent valid cells according to an embodiment of the present disclosure. More specifically, FIG. 6A illustrates 2 hop cell neighbors of a central cell 602, and FIG. 6B illustrates distances from the center of X to the Centers of 1-Hop cells. Two properties for a cell can be defined as follows by way of example:
1. Validity: A cell is valid if the center of the cell does not lie on or in any obstacle polygon, and vice versa.
2. Connectivity: A cell X is connected to cell Y only if the line joining the center of cell X and center of cell Y does not intersect or touch any obstacle polygon.
[0028] In other words, the set of invalid cells are automatically identified by determining at least one of (i) a presence of at least a portion of a cell in any of the one or more obstacle polygons, (ii) a degree of overlap of a cell on any of the one or more obstacle polygons. To determine the degree of overlap, the system 100 may configure a pre-defined overlap threshold which may be compared with the degree of overlap of a cell with an obstacle polygon to identify the cell as either valid or invalid cell. In an example embodiment, the overlap threshold may be pre-defined or configured in the system 100 and may be in one or more following ranges 0-50% or 50%-75%, and/or 75%-100%. The overlap threshold may be re-configured at any point of time, depending upon one or more scenarios (e.g., event type such as evacuation, and the like, map type, number of obstacle polygons detected, number of valid cells, and invalid cells automatically identified, user requests for optimal map generation and routing/navigation, etc.).
[0029] Assuming, a dimension for cells to be 50 centimeters x 50 centimeters. The adjacency representation encapsulates two important information for each cell X: 1) whether cell X is invalid/valid, and 2) a set, SC of cells containing all the cells which are connected to X within a two-hop distance (FIG. 6A). Hence the cardinality of SC is between 0 and 24.
[0030] In an embodiment of the present disclosure, the adjacency information comprises, for example, but not limited to, two fold applications: For example, this adjacency information can be used in localizing and tracking a user on a floor map by propagating his/her location estimates through valid cells using, for example, a probabilistic propagation approach or a model like particle filter. This uses the 2-hop cell information for a typical cell size of 50 centimeters, since for a single stride taken by the user, a minimum of two cells are traversed, assuming the average stride length of the user is well above 50 centimeters.
[0031] Secondly, the adjacency can be used to find optimum routes between a source and a destination, where a source can be user's current location and a destination can be a direct location input from a user or from any planner application containing the destination information about the place/location (e.g., venue) user may want to go on the floor map. For this, only 1-hop neighbor information suffices.
[0032] In an embodiment of the present disclosure, at step 212, the one or more processors 104 generate, using the adjacency information, one or more optimal paths for routing/navigation in the specific volume. In an embodiment of the present disclosure, the adjacency information of each valid cell from the set of automatically identified valid cells is used for generating one or more optimal paths for routing/navigating in the volume. The optimal path may be indicative of a route to be taken from a source to a destination. The optimal path may be generated based on one or more parameters/criteria, for example, time (e.g., less time to reach the destination from the source), distance (shortest path identified and generated for routing from the source to destination), and the like. In an embodiment of the present disclosure, the parameter ‘time’ may use the real-time information about how crowded a particular path may be or will/could be at a given point of time, which in turn can come from a tracking application running on one or more personal devices carried by one or more users (either in the volume or in close proximity of the volume (or in close proximity of the source and/or destination). In an embodiment, such information may be sourced from at least one of an Internet of Things (IoT) platform, a cloud environment, a third party application, and the like, in an example embodiment. To generate one or more optimal paths, it is assumed that center of cells to be vertexes and their interconnections to be the edges. In an embodiment of the present disclosure, the system 100 may execute one or more techniques (e.g., Dijkstra's technique) to generate optimal paths for routing. Following is an exemplary of the implementation by the system 100:
[0033] For a geometric distance metric, the distance array D is defined as D = {vCL, CL, vCL, CL, CL, vCL, CL, vCL}, which are distances of the center of the cell X from centers of neighboring cells in the order E = {XF, XG, XH, XE, XA, XD, XC, XB} as depicted in FIG. 6B.
[0034] For a time based distance metric, i.e., path of shortest time, (not shortest ground distance), the distance array D is defined as D = {TEi: Approximate time to traverse the respective edge ‘i’ in set E}. The time TEi can be estimated from the average speed of the user, and a user density metric derived from the number of users currently around the edge ‘i’ in set E. This number of users can be decided by counting the number of users within a circle of radius R and center as the center of edge ‘i’.
Center of the cell X is defined as CX.
Graph G is defined as G = (V, E); V = {CX: X is a set of all the valid cells on the floor map}
E = {Edge(CX-CY): Cells X and Y are valid and connected}.
Then the Dijkstra’s technique can be applied as on any other regular graph as:
structure Cell (fields stored for each cell during the technique)
{
- Distance (stores the distance traversed from the source till this cell)
- Is_Visited (stores whether this cell has been considered for a shortest path)
- Previous_Cell (stores the cell in the shortest path before current cell)
}
GetRoute (Cell Source, Cell Destination, G)
{
N_Cells_Visited ? 0
N_Total_Cells ? |V|
[V].Is_Visited ? false
[V].Distance ? 8
Routing_Path ?
Repeat while (N_Cells_Visited < N_Total_Cells)
{
Min_Distance_Cell ? Cell with minimum ‘Distance’ field
If (Min_Distance_Cell = Destination)
End Parent Loop
N_Cells_Visited ? N_Cells_Visited + 1
Min_Distance_Cell.Is_Visited ? true
VN ? Set of all valid connected cells within one hop of
Min_Distance_Cell
For a cell C in VN:
{
DC ? D[i]: i is a corresponding index of position of C with respect to central cell
Min_Distance_cell (refer to FIG. 6B and definition of array D)
if (Min_Distance_Cell.Distance + DC < C.Distance)
{
C.Distance ? Min_Distance_Cell.Distance + DC
C.Previous_Cell ? Min_Distance_Cell
}
}
}
if (N_Cells_Visited < N_Total_Cells)
{
Current_Cell ? Destination
Repeat while (Current_Cell != Source)
{
Add Current_Cell to Routing_Path
Current_Cell ? Current_Cell.Previous_Cell
}
Add Current_Cell to Routing_Path
Add Source to Routing_Path
}
Return Routing_Path
}
[0035] It should be noted that the above technique can directly be extended for following use cases in a simple way when the easily available raster floor maps are available for a building (define shortest path from A to B using the vector model of the present disclosure as SP(A, B)):
Multiple Floor Routing: In this case, raster floor maps of all the floors of a building are stored in the system 100 in proper vectorized sets of obstacle polygons, as described by the embodiments of the present disclosure invention. If a user wants to route from location L1 on floor F1 to location L2 on floor F2, following can be executed (Inter-Floor Traversal Medium (IFTM), IFTM which can be stairs or lift/elevator, depending on whether the scenario is for evacuation, or on personal choice of the user):
1) Get shortest path from L1 to IFTM location of floor F1 using the floor map models as described by the embodiments of the present disclosure.
2) Traverse from IFTM location of floor F1 to IFTM location of floor F2.
3) Get shortest path from IFTM location of floor F2 to L2 using the floor map models as described by the embodiments of the present disclosure.
Conditional Routing: If the user wants to reach at a destination D from source S via a set of intermediate n stops ISI, then the overall (optimal) route is SP(S, IS1) + SP(IS1, IS2) + SP(IS2, IS3) + … + SP(ISn-1, D), assuming the ISi’s are provided in the order of arrival.
[0036] FIG. 7 shows a user interface of illustrating an optimal path (or shortest route) generated by the system 100 of FIG. 1 from a source to a destination according to an embodiment of the present disclosure. More specifically, FIG. 7 depicts an optimal path 702 generated by the system 100 that indicates a path to be taken from a source to a destination (e.g., ODC 8) for navigation by one or more users.
[0037] The embodiments of the present disclosure provide systems and methods for generating one or more optimal paths for routing. Conventional systems and/or techniques rely on raster image that are color-coded beforehand. This involves applying image processing techniques on the raster image thus making the process erroneous. Unlike conventional systems and techniques, the embodiments of the present disclosure enable the system 100 to determine navigable areas without errors, and without any manual intervention. Unlike conventional systems and methods which perform determining of navigable areas in two stages: first color coding the map, then performing image processing on the map to read the color codes, the embodiments of the present disclosure performs the same task in a single automated pass, and since no image processing is involved, the task is processing power friendly for very large maps, thereby reducing processing time, memory usage, power consumption, and effectively utilization of resources of the system 100.
[0038] The written description describes the subject matter herein to enable any person skilled in the art to make and use the embodiments. The scope of the subject matter embodiments is defined by the claims and may include other modifications that occur to those skilled in the art. Such other modifications are intended to be within the scope of the claims if they have similar elements that do not differ from the literal language of the claims or if they include equivalent elements with insubstantial differences from the literal language of the claims.
[0039] It is to be understood that the scope of the protection is extended to such a program and in addition to a computer-readable means having a message therein; such computer-readable storage means contain program-code means for implementation of one or more steps of the method, when the program runs on a server or mobile device or any suitable programmable device. The hardware device can be any kind of device which can be programmed including e.g. any kind of computer like a server or a personal computer, or the like, or any combination thereof. The device may also include means which could be e.g. hardware means like e.g. an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a combination of hardware and software means, e.g. an ASIC and an FPGA, or at least one microprocessor and at least one memory with software modules located therein. Thus, the means can include both hardware means and software means. The method embodiments described herein could be implemented in hardware and software. The device may also include software means. Alternatively, the embodiments may be implemented on different hardware devices, e.g. using a plurality of CPUs.
[0040] The embodiments herein can comprise hardware and software elements. The embodiments that are implemented in software include but are not limited to, firmware, resident software, microcode, etc. The functions performed by various modules described herein may be implemented in other modules or combinations of other modules. For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can comprise, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
[0041] The illustrated steps are set out to explain the exemplary embodiments shown, and it should be anticipated that ongoing technological development will change the manner in which particular functions are performed. These examples are presented herein for purposes of illustration, and not limitation. Further, the boundaries of the functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternative boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. Alternatives (including equivalents, extensions, variations, deviations, etc., of those described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such alternatives fall within the scope and spirit of the disclosed embodiments. Also, the words “comprising,” “having,” “containing,” and “including,” and other similar forms are intended to be equivalent in meaning and be open ended in that an item or items following any one of these words is not meant to be an exhaustive listing of such item or items, or meant to be limited to only the listed item or items. It must also be noted that as used herein and in the appended claims, the singular forms “a,” “an,” and “the” include plural references unless the context clearly dictates otherwise.
[0042] Furthermore, one or more computer-readable storage media may be utilized in implementing embodiments consistent with the present disclosure. A computer-readable storage medium refers to any type of physical memory on which information or data readable by a processor may be stored. Thus, a computer-readable storage medium may store instructions for execution by one or more processors, including instructions for causing the processor(s) to perform steps or stages consistent with the embodiments described herein. The term “computer-readable medium” should be understood to include tangible items and exclude carrier waves and transient signals, i.e., be non-transitory. Examples include random access memory (RAM), read-only memory (ROM), volatile memory, nonvolatile memory, hard drives, CD ROMs, BLU-RAYs, DVDs, flash drives, disks, and any other known physical storage media.
[0043] It is intended that the disclosure and examples be considered as exemplary only, with a true scope and spirit of disclosed embodiments being indicated by the following claims.