CLIAMS:An apparatus comprising:
decode logic to decode a vector packed zero high bits starting with a specified bit position (VPBZHI) instruction, the VPBZHI instruction including a first and second source operand and a destination operand;
execution logic to execute the decoded VPBZHI instruction to cause,
for each data element position of the first source operand a determination of a starting bit position for zeroing out values of the second source beginning at a data element at that starting position,
for each corresponding data element position of the second source operand, a zeroing of bits that are in bit positions that are more significant or equal to the starting bit position of a corresponding data element position of the first source operand,
storing into the destination operand values of the second source after any zeroing into corresponding data element positions.
,TagSPECI:[0001] The field of invention relates generally to computer processor architecture, and, more specifically, to instructions which when executed cause a particular result.

Background
[0002] An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, and may include the native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term instruction generally refers herein to a macro-instruction – that is instructions that are provided to the processor for execution – as opposed to micro-instructions or micro-ops – that result from a processor’s decoder decoding macro-instructions).