FORM -2
THE PATENTS ACT, 1970 (39 of 1970) & THE PATENTS RULES, 2003
PROVISIONAL
Specification
(See Section 10 and rule 13)
SYSTEMS FOR PARALLEL COMPUTING

COMPUTATIONAL RESEARCH LABORATORIES LIMITED
an Indian Company of Survey No. 103/A, Ground Moor, Pride Portal, Bahirat Wadi, Senapati Bapat Road, Pune 411016, Maharashtra, India
THE FOLLOWING SPECIFICATION DESCRIBES THE INVENTION

Field of the Invention:
This invention relates to systems for computing.
Particularly, this invention relates to systems for parallel computing.
Background of the Invention:
Computing units include central processing units (CPU) comprising multiprocessing equipment, typically multi-core processors. With the advent of multi-core CPUs and fast interconnects, the computing power of supercomputers is increasing very fast. The computational problems in science and engineering are becoming increasingly more complex. To solve these complex problems parallel computation on large supercomputers is becoming common nowadays. Parallel computation works on the premise that large complex problems can be broken down into smaller problems. These smaller problems can be (1) distributed on processing units, (2) be worked upon independently for certain amount of time, (3) then collated later on. The steps (1) to (3) are repeated till final result of the larger problem is obtained.
However the speedup of many parallel applications on large supercomputers is often not satisfactory. One of the main reasons for poor scaling of parallel applications is the distribution of the whole job amongst available nodes in a single level. This leads to random communication across the interconnect network causing congestion and delay.
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Objectives of the Invention:
An objective of the invention is to provide a computing system for decreasing the time required for computing.
Another objective of the invention is to provide a computing system which efficiently uses the interconnect network.
Summary of the Invention:
Modern supercomputers are composed of large number of computer nodes connected by fast interconnects. Each computing system contains a plurality of 'nodes', and a set of nodes is defined to be a 'group'. This invention envisages a system for parallel computing, which can be adapted to be used for newer assemblies, as well as existing assemblies.
In accordance with an embodiment of this invention, each component (node) of the interconnect topology forming the network within a computing system is tagged, hierarchically labeled and collated into groups in accordance with pre¬defined parameters. Each group may have sub-groups at its lower level and master-groups at its higher level. Thus, each node is hierarchically tagged to its immediate upper level, and a multi-level tier of groups is formed. The exact number of levels/tiers will depend on the actual number of nodes available and other hardware considerations.
Typically, the bandwidth available at any level of group is more than its next level group and less than its previous level group.

In accordance with another embodiment of this invention, the computing system is adapted to break down any input problem into a plurality of smaller problems. Said lower level of groups of nodes are then employed in accordance with this invention to individually handle said broken down smaller problems in a parallel fashion. Said nodes within said groups are pre-selected in accordance with pre-defined parameters to service portions of said problem.
In accordance with another embodiment of this invention, the computing system is provided by an interconnecting mechanism adapted for connecting one group to another in accordance with pre-defined characteristics and functions.
Typically, the communication at any level of group is more than its next level group and less than its previous level group. This provides the computing system to take full advantage of the hierarchical bandwidth of the entire cluster which gives rise to much better scaling.
Brief Description of the Accompanying Drawings:
Figure 1 illustrates a computing system of the prior art randomly solving a problem.
The invention will now be described in relation to the accompanying drawings, in which:
Figure 2 illustrates a hierarchical parallel computing.
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Detailed Description of the Accompanying Drawings:
Figure I illustrates a typical parallel computing system of the prior art solving a problem. The nodes [as represented by the dots] form the core of the computing system. The arrows represent the communication between said nodes [as represented by the dots]. The overall communication pattern is random and not optimized in relation to distribution of nodes, and hence leads to lesser efficiency.
Figure 2 illustrates a hierarchical parallel computing in accordance with this invention.
Here each group is represented by circles that encircle the nodes. The problem is first broken amongst the group. At this level the communication between groups is represented by bold arrows. Within each group the group level problems are further subdivided into next lower level groups or within the nodes [if it is the last level]. The communication pattern within each group is shown by thin arrows.
This invention envisages a system for parallel computing, which can be adapted to be used for newer assemblies, as well as existing assemblies. In accordance with an embodiment of this invention, each component (node) [as represented by the dots] of the interconnect topology forming the network within a computing system is tagged, hierarchically labeled and collated into groups [as represented by circles enclosing the dots] in accordance with pre-defined parameters. Each group [as represented by circles enclosing the dots] may have sub-groups at its lower level and master-groups at its higher level. Thus, each
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node [as represented by the dots] is hierarchically tagged to its immediate upper level, and a multi-level tier of groups [as represented by circles enclosing the dots] is formed. The exact number of levels/tiers will depend on the actual number of nodes [as represented by the dots] available and other hardware consideration Typically, the bandwidth available at any level of group (as represented by circles enclosing the dots] is more than its next level group and less than its previous level group. In accordance with another embodiment of this invention, the computing system is adapted to break down any input problem into a plurality of smaller problems. Said lower level of groups [as represented by circles enclosing the dots] of nodes [as represented by the dots] are then employed in accordance with this invention to individually handle said broken down smaller problems in a parallel fashion. Said nodes [as represented by the dots] within said groups [as represented by circles enclosing the dots] are pre-selected in accordance with pre-defined parameters to service portions of said problem. In accordance with another embodiment of this invention, the computing system is provided by an interconnecting mechanism adapted for connecting one group [as represented by circles enclosing the dots] to another in accordance with pre-defined characteristics and functions. Typically, the communication at any level of group [as represented by circles enclosing the dots] is more than its next level group [as represented by circles enclosing the dots] and less than its previous level group [as represented by circles enclosing the dots]. Communication between nodes [as represented by the dots] and groups [as represented by circles enclosing the dots] are represented by arrows. This provides the computing system to take full advantage of the hierarchical bandwidth of the entire cluster which gives rise to much better scaling.
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In view of the wide variety of embodiments to which the principles of the present invention can be applied, it should be understood that the illustrated embodiments are exemplary only. The illustrated embodiments should not be taken as limiting the scope of the present invention. For example, the interactions between the components may be taken in sequences other than those described, and more or fewer elements may be used. While various elements of the preferred embodiments have been described as being implemented, other embodiments implementations may alternatively be used, and vice-versa.
Dated this 17th day of October 2008.
Mohan Dewan
Of R.K. Dewan & Co.
Applicants' Patent Attorney.

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