Description:This document pertains generally, but not by way of limitation, to die
interconnections, and more particularly to providing large heterogeneous-die packages using integrated die bridges.

Background
Conventional die manufacturing techniques are being pushed to their
limits for size of a monolithic die
, yet applications are yearning for capabilities
that are possible for large dimensional integrated circuits using the latest
technology such as 7nm gate lengths. As monolithic dies have become bigger,
small differences that can be overlooked for smaller dies
, cannot be compensated
for and can often significantly reduce yield. Recent solutions can involve using
smaller integrated circuits interconnected with a semiconductor interposer or
integrated with silicon bridges assembled into a silicon substrate to provide a
heterogeneous-chip package. However, conventional techniques for making the
semiconductor imposer or substrate limit the size of the heterogeneous-chip
package. , C , Claims:1. A chip package, comprising:
a base die in a molding material, the base die comprising interconnections;
a metal functional connection in the molding material, the metal functional connection laterally adjacent to the base die, wherein the metal functional connection has a height at least equal to a thickness of the molding material;
a first chip electrically coupled to the base die;
a second chip electrically coupled to the base die, the second chip electrically coupled to the first chip by the interconnections in the base die; and
a dielectric material between and in contact with the first chip and the second chip, the dielectric material having an upper surface co-planer with an upper surface of the first chip.