Claims:1. An offload device comprising:
a processing engine implemented at least partially in hardware, wherein the processing engine is to:
receive a translation fetch descriptor from a processor of a compute device to be processed by the processing engine, the translation fetch descriptor comprising an indication of a plurality of virtual memory addresses;
send, in response to receipt of the translation fetch descriptor, a request for a physical memory address corresponding to each of the plurality of virtual memory addresses; and
send, without reading from or writing to any of the physical addresses corresponding to the plurality of virtual memory addresses, an indication to the processor that the translation fetch descriptor has been processed.
, Description:CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present patent application claims the benefit of U.S. Non-Provisional Patent Application No. 17/129,496, filed December 21, 2020, and titled: “TECHNOLOGIES FOR OFFLOAD DEVICE FETCHING OF ADDRESS TRANSLATIONS”, which is incorporated herein by reference in its entirety.
BACKGROUND
[0002] Offload devices such as accelerators are a type of connected device or endpoint that can offload general purpose processing and execute certain workloads with additional capacity or more efficiently in terms of performance and power. Address virtualization capabilities allow for scalable, robust use of accelerators. An operating system can manage virtual address spaces and the assignment of real memory to virtual memory. Real memory is addressed using physical addresses while virtual memory is addressed using virtual addresses. Address translation hardware in the central processing unit, often referred to as a memory management unit or MMU, can translate virtual addresses to physical addresses.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
[0004] FIG. 1 is a simplified block diagram of at least one embodiment of a compute device with an offload device for fetching of address translations;
[0005] FIG. 2 is a simplified block diagram of at least one embodiment of an environment that may be established by the compute device of FIG. 1;
[0006] FIG. 3 is a simplified block diagram of at least one embodiment of an environment that may be established by the offload device of FIG. 1 and/or the RCiEP of FIG. 1;
[0007] FIG. 4 is a table depicting one embodiment of a translation fetch descriptor that may be used by the compute device of FIG. 1;
[0008] FIG. 5 is a table depicting one embodiment of a translation fetch completion record that may be used by the compute device of FIG. 1;
[0009] FIG. 6 is a simplified flow diagram of at least one embodiment of a method for off-loading a task that may be performed by the compute device of FIG. 1; and
[0010] FIGS. 7-10 are a simplified flow diagram of at least one embodiment of a method for fetching address translations that may be executed by the some or all components of the compute device of FIG. 1.
DETAILED DESCRIPTION OF THE DRAWINGS
[0011] While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.
[0012] References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).