Claims:1. A computing device for dynamic address assignment, the computing device comprising a data bus and a host controller, wherein the host controller is to:
receive device information from a peripheral device via the data bus, wherein the device information comprises a provisional identifier, a bus characteristic register, and a device characteristic register;
determine an instance identifier as a function of the provisional identifier;
determine whether an entry of a device address table of the host controller matches the instance identifier;
determine whether the entry is available for assignment in response to a determination that the entry matches the instance identifier; and
assign a dynamic address to the peripheral device, (i) wherein the dynamic address is assigned from the entry in response to a determination that the entry is available for assignment and (ii) wherein the dynamic address is assigned from an initial address register of the host controller in response to a determination that an entry of the device address table does not match the instance identifier or a determination that the entry is not available for assignment.
, Description:BACKGROUND
[0001] Current mobile devices such as smart phones, tablets, and other computing devices include an increasing number of sensors and other peripheral devices and integrated circuits. Typical sensors and other peripheral devices may be connected to a computing device via a variety of I/O interfaces, such as the I2C interface, the serial peripheral interface (SPI) bus, UART serial ports, or other interfaces. The MIPI® Alliance is currently developing a specification for a two-wire interface known as MIPI I3C™. The I3C specification may support communications with multiple sensors or other peripheral devices connected to the bus. Additionally, the I3C specification may support hot-joining peripheral devices to the bus after it is initially started.
BRIEF DESCRIPTION OF THE DRAWINGS
[0002] The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
[0003] FIG. 1 is a simplified block diagram of at least one embodiment of a computing device for predictable dynamic address assignment;
[0004] FIG. 2 is a simplified block diagram of at least one embodiment of an environment of the computing device of FIG. 1;
[0005] FIG. 3 is a schematic diagram of at least one embodiment of a data bus of the computing device of FIGS. 1-2;
[0006] FIG. 4 is a simplified flow diagram of at least one embodiment of a method for predictable dynamic address assignment that may be executed by the computing device of FIGS. 1 and 2; and
[0007] FIG. 5 is a simplified flow diagram of at least one embodiment of a method for assigning a dynamic address that may be executed by a host controller of the computing device of FIGS. 1 and 2.