Claims:1. A frequency multiplier (400) comprising:
an input filter (402) configured in the frequency multiplier to receive an input signal at a fundamental frequency from a radio frequency (RF) source, the input filter allows to pass fundamental frequency and rejects undesired frequency;
a bias circuit (404) connected in shunt between the input filter (402) and a matching circuit (406), the bias circuit, on receipt of the input signal, bias a step recovery diode (SRD) (420), the SRD and transient tuning circuit (416) are coupled in shunt of an impulse generator (408), the impulse generator generates a voltage impulse with fast rise time and short pulse width;
a temperature compensation circuit (412) is connected in series between the resonator circuit (410) and an output filter (414), the output pulse received from the impulse generator is converted to a sinusoidal output voltage to obtain a desired frequency,
wherein, the temperature compensation circuit (412) configured to stabilise the output power level variation across operating temperature range, and wherein the output filter configured to pass a desired nth output harmonic of fundamental frequency.
2. The frequency multiplier as claimed in claim 1, wherein the input filter (402) is a narrowband SAW band pass filter.
3. The frequency multiplier as claimed in claim 2, wherein the narrowband SAW bandpass filter connected between bias circuit and RF input source, the narrowband SAW bandpass filter passes fundamental frequency and reject out of band harmonics to prevent SRD oscillations.
4. The frequency multiplier as claimed in claim 1, wherein the bias circuit (404) comprises a thermal resistor RB connected with bias voltage VB, wherein thermal resistor RB limits the bias voltage VB variation across operating temperature range to achieve stable output level.
5. The frequency multiplier as claimed in claim 4, wherein the bias circuit (404) controls maximum output power level at desired harmonic by controlling input drive of the SRD.
6. The frequency multiplier as claimed in claim 1, wherein an impulse inductor (418) of impulse generator (408) is connected in series between SRD (420) and transient tuning circuit (416).
7. The frequency multiplier as claimed in claim 1, wherein the output filter (414) is a narrowband output SAW bandpass filter.
8. The frequency multiplier as claimed in claim 7, wherein the narrowband output SAW bandpass filter is coupled at the output of the temperature compensation circuit (412) for passing the nth output harmonic of fundamental frequency and rejecting out of band harmonics.
9. The frequency multiplier as claimed in claim 1, wherein the temperature compensation circuit (412) limit the output power level variation with at least four different selectable attenuation versus temperature slopes.
10. The frequency multiplier as claimed in claim 9, wherein the temperature compensation circuit (412) comprises at least two logic controls for achieving attenuation slope versus temperature.
, Description:TECHNICAL FIELD
[0001] The present disclosure relates, in general, to frequency multipliers, and more specifically, relates to a temperature compensated high-frequency multiplier with selectable attenuation versus temperature slopes.

BACKGROUND
[0002] Frequency multipliers are used to derive from an input signal having an input frequency an output signal having an output frequency greater than the input frequency of the input signal. Typically, the output frequency is an exact integral multiplier of the input frequency. Few existing frequency multipliers include an input circuit, an output circuit, and a resonating circuit. The input circuit is coupled to an input node and a middle node. The middle node provides a middle signal that has a signal component having the same frequency as an input signal that is provided to the input node. The middle signal further has an even number “n” multiples of the input signal frequency. The output circuit has a pre-determined input impedance for the middle node. The resonance circuit includes an inductor that is coupled in series with a capacitor, where the capacitor is in a parallel connection to the middle node. The resonance circuit has a resonance frequency that is equal to the frequency of the input signal, and such a resonance circuit also has an output impedance that matches with the predetermined input impedance of the output circuit.
[0003] Another existing frequency multiplier includes a frequency multiplier circuit for producing isolated odd and even harmonics, and a self-biasing diode microwave frequency multiplier. In the self-biasing diode microwave frequency multiplier, the microwave frequency multiplier employs a first diode and a second diode each coupled in an anti-parallel relationship across a signal input of a finline structure, each of the diodes being associated with signal-induced biasing elements for self-biasing the diodes. A bias is caused to occur at internal nodes which increase with increased input power for a broad range of input power clipping at higher signal levels. Relative to prior arts, the conversion loss will remain optimum up to high input power over an entire high power input range. Additional external bias may be employed in the existing frequency multipliers.
[0004] However, the existing approaches require additional expensive fixed attenuation slope co-fired ceramics with temperature-sensitive materials or current hungry PIN diodes with elaborate area consuming control circuits. Therefore, there is a need in the art to provide a means that improves temperature stability and gain of a frequency multiplier.

OBJECTS OF THE PRESENT DISCLOSURE
[0005] An object of the present disclosure relates, in general, to frequency multipliers, and more specifically, relates to a temperature compensated high-frequency multiplier with selectable attenuation versus temperature slopes.
[0006] Another object of the present disclosure improves temperature stability of frequency multiplier using unique temperature compensation circuit.
[0007] Another object of the present disclosure controls attenuation slope versus temperature for fine optimisation of temperature variations across temperature with two logic controls.
[0008] Another object of the present disclosure a system that supply to bias step recovery diode (SRD) diode to achieve better gain efficiency.
[0009] Another object of the present disclosure provides a gain efficient SRD
[0010] Yet another object of the present disclosure provides narrowband filters at input and output to achieve better noise performance.

SUMMARY
[0011] The present disclosure relates, in general, to frequency multipliers, and more specifically, relates to a temperature compensated high-frequency multiplier with selectable attenuation versus temperature slopes.
[0012] The present disclosure relates to a unique method for temperature compensated and gain efficient step recovery diode (SRD) high-frequency multiplier with selectable attenuation versus temperature slopes. This deals with the method of improving temperature stability of frequency multiplier using unique temperature compensation circuit more particularly with two logic controls for controlling attenuation slope versus temperature for fine optimisation of temperature variations across temperature. This system consists of a circuit with a supply to bias SRD diode to achieve better gain efficiency. Narrowband filters at input and output are used to achieve better noise performance. The high-frequency multiplier using SRD can be used as a harmonic generator in the transmitter or receiver subsystem of any electronic warfare system devoted to generating signals at specific frequencies.
[0013] In an aspect, the present disclosure provides a frequency multiplier including an input filter configured in the frequency multiplier to receive an input signal at a fundamental frequency from a radio frequency (RF) source, the input filter allows to pass fundamental frequency and rejects undesired frequency, a bias circuit connected in shunt between the input filter and a matching circuit, the bias circuit, on receipt of the input signal, bias a step recovery diode (SRD), the SRD and transient tuning circuit are coupled in shunt of an impulse generator, the impulse generator generates a voltage impulse with fast rise time and short pulse width, a temperature compensation circuit is connected in series between the resonator circuit and an output filter, the output pulse received from the impulse generator is converted to a sinusoidal output voltage to obtain a desired frequency, wherein, the temperature compensation circuit configured to stabilise the output power level variation across operating temperature range, and wherein the output filter configured to pass a desired nth output harmonic of fundamental frequency.
[0014] In an embodiment, the input filter is a narrowband SAW band pass filter.
[0015] In another embodiment, the narrowband SAW bandpass filter connected between bias circuit and RF input source, the narrowband SAW bandpass filter passes fundamental frequency and reject out of band harmonics to prevent SRD oscillations.
[0016] In another embodiment, the bias circuit comprises a thermal resistor RB connected with VB, wherein thermal resistor RB limits the bias voltage variation across operating temperature range to achieve stable output level.
[0017] In another embodiment, the bias circuit controls maximum output power level at desired harmonic by controlling input drive of the SRD.
[0018] In another embodiment, the impulse inductor of impulse generator is connected in series between SRD and transient tuning circuit.
[0019] In another embodiment, the output filter is a narrowband output SAW bandpass filter.
[0020] In another embodiment, the narrowband output SAW bandpass filter is coupled at the output of the temperature compensation circuit for passing the nth output harmonic of fundamental frequency and rejecting out of band harmonics.
[0021] In another embodiment, the temperature compensation circuit limit the output power level variation with at least four different selectable attenuation versus temperature slopes.
[0022] In another embodiment, the temperature compensation circuit comprises at least two logic controls for achieving attenuation slope versus temperature.
[0023] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The following drawings form part of the present specification and are included to further illustrate aspects of the present disclosure. The disclosure may be better understood by reference to the drawings in combination with the detailed description of the specific embodiments presented herein.
[0025] FIG. 1 illustrates a block diagram of the conventional frequency multiplier.
[0026] FIG. 2 illustrates block diagram of conventional frequency multiplier circuit for producing isolated odd and even harmonics.
[0027] FIG. 3 illustrates block diagram of the self-biasing diode microwave frequency multiplier.
[0028] FIG. 4A illustrates an exemplary block diagram of temperature compensated frequency multiplier with selectable attenuation versus temperature slopes, in accordance with an embodiment of the present disclosure.
[0029] FIG. 4B illustrates an exemplary circuit diagram of impulse generator and transient tuning circuit, in accordance with an embodiment of the present disclosure.
[0030] FIG. 4C illustrates an exemplary circuit diagram of temperature compensation circuit, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0031] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0032] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0033] FIG. 1 illustrates a block diagram of the conventional frequency multiplier.
[0034] Referring to FIG. 1, conventional frequency multiplier 100 that can include an input node 102, an output node 104, an input impedance matching circuit 106, an field-effect transistor (FET) 108, a resonance circuit 110, a direct current (DC) cut capacitor 112, an FET 114, and an output impedance matching circuit 116.
[0035] FIG. 2 illustrates block diagram of conventional frequency multiplier circuit for producing isolated odd and even harmonics. Referring to FIG.2, the frequency multiplier circuit 200 for producing isolated odd and even harmonics include a 180° hybrid receptive of a fundamental frequency signal which may be adjusted over a range of frequencies produces the fundamental frequency signal at two output ports (204, 206) phased 180° apart. The 180° and 0° hybrid is coupled to receive at respective input ports 202 the signal from the active devices and to produce at one output port all the odd harmonics and to produce at the other output port (204, 206) all of the even harmonics of the fundamental frequency.
[0036] FIG. 3 illustrates block diagram of the self-biasing diode microwave frequency multiplier. Referring to FIG. 3, the microwave frequency multiplier 300 employs a first diode D1 and a second diode D2 each coupled in an anti-parallel relationship across a signal input of a finline structure, each of the diodes being associated with signal-induced biasing elements for self-biasing the diodes. A bias is caused to occur at internal nodes which increase with increased input power for a broad range of input power levels. Relative to prior arts, the conversion loss will remain optimum up to high input power over an entire high power input range. Additional external bias may be employed in alternative embodiments.
[0037] The conventional approaches described above require additional expensive fixed attenuation slope co-fired ceramics with temperature sensitive materials or current hungry PIN diodes with elaborate area consuming control circuits.
[0038] The present disclosure relates, in general, to frequency multipliers, and more specifically, relates to a temperature compensated high-frequency multiplier with selectable attenuation versus temperature slopes.
[0039] The present disclosure relates to a unique method for temperature compensated and gain efficient step recovery diode (SRD) high-frequency multiplier with selectable attenuation versus temperature slopes. This deals with the method of improving temperature stability of frequency multiplier using unique temperature compensation circuit more particularly with two logic controls for controlling attenuation slope versus temperature for fine optimisation of temperature variations across temperature. This system consists of a circuit with a supply to bias SRD diode to achieve better gain efficiency. Narrowband filters at input and output are used to achieve better noise performance. The high-frequency multiplier using SRD can be used as a harmonic generator in the transmitter or receiver subsystem of any electronic warfare system devoted to generating signals at specific frequencies. The present disclosure can be described in enabling detail in the following examples, which may represent more than one embodiment of the present disclosure.
[0040] FIG. 4A illustrates an exemplary block diagram of temperature compensated frequency multiplier with selectable attenuation versus temperature slopes, in accordance with an embodiment of the present disclosure.
[0041] Referring to FIG.4A, temperature compensated frequency multiplier 400 that can include input filter 402, bias circuit 404, a matching circuit 406, an impulse generator 408, resonator circuit 410, temperature compensation circuit 412, and an output filter 414. In an exemplary embodiment, the frequency multiplier 400 may include input filter 402, bias circuit 404, matching circuit 406, the impulse generator 408 and transient tuning circuit 416 at the input of a step recovery diode (SRD) 420 and the output section can include the resonator circuit 410, temperature compensation circuit 412 and output filter 414. In an exemplary embodiment, it is assumed that the SRD 420 and transient tuning circuit 416 to be used in shunt mode.
[0042] In an exemplary embodiment, the input filter 402 of the frequency multiplier 400 can include a narrowband surface acoustic wave (SAW) band-pass filter. The narrowband SAW bandpass filter can be coupled between the bias circuit 404 and a radio frequency (RF) input source 422. The input fundamental frequency can be received by the narrowband SAW bandpass filter from the RF input source 422 to allow fundamental frequency and to reject unwanted signals. The input filter 402 connected in series to reject low and high-frequency resonance in the source that drives the SRD diode 420 to oscillations and can provide better phase noise performance.
[0043] The bias circuit 404 can be connected in shunt between the input filter 402 and matching circuit 406 to allow a rectified current to flow and to generate the negative bias voltage when RF is applied. A thermal resistor RB is connected with bias voltage VB in the bias circuit 404, where the thermal register limits the bias voltage variation across the operating temperature range to achieve a stable output level. In another embodiment, the bias circuit 404 can be coupled with the matching circuit 406 connected to bias SRD diode 420 to achieve nth output harmonics level. The value of bias resistor RB is calculated by applying below given equation (1):
[0044] (1)
where,
RB: SRD Biasing Resistor,
T: SRD carrier life time,
n: Multiplying factor,
Cvr: Reverse Bias Diode Capacitance.
[0045] The bias circuit 404 is provided to control maximum output power level at desired harmonic by controlling input drive of SRD diode 420. For impulse generator and transient tuning circuit 408 in loaded condition, time impulse width tp is to get the maximum power of desired harmonics, the following condition should be satisfied i.e.,
where, : maximum output frequency of nth harmonics.
[0046] In another embodiment, the impulse generator 408 coupled to matching circuit 406, the impulse generator 408 can generate a voltage impulse with a fast rise time and short pulse width. An impulse inductor Li 418 can be connected in series between SRD diode 420, transient tuning circuit 416 having capacitor Ct and inductor Lt. The output of the impulse generator 408 can be coupled to the resonator circuit 410.
[0047] In another embodiment, the temperature compensation circuit 412 can be connected in series between the output filter 414 and the resonator circuit 410. The output pulse received from the impulse generator 408 is converted to a sinusoidal output voltage to obtain the desired frequency, where the output filter 414 can pass the desired nth output harmonics of the fundamental input frequency. In an exemplary embodiment, the output filter 414 can be a narrowband SAW bandpass filter. The narrowband SAW bandpass filter can be coupled at the output of temperature compensation circuit 412 for passing primarily nth harmonic of fundamental input frequency and rejecting out of band harmonics.
[0048] In another embodiment, the temperature compensation circuit 412 connected in series between resonator circuit 410 and output filter 414 to limit output power level variation across operating temperature range of -40 to +85°C. The temperature compensation circuit 412 connected at the output of frequency multiplier 400 to limit output power level variation with at least four different selectable attenuation versus temperature slopes. The temperature compensating architecture of the present disclosure requires only a single supply voltage and two logic bits to set control attenuation slope versus temperature, thereby the requirement of the elaborate area can be reduced.
[0049] FIG. 4B illustrates an exemplary circuit diagram of impulse generator and transient tuning circuit, in accordance with an embodiment of the present disclosure. The selection of SRD diode 412 in FIG. 4B selected for required input frequency, output frequency, bandwidth and output power of multiplier based on the following rules: Transition time : tt = 1/ ,
Carrier Lifetime: t >>1/2pfin,
Junction Capacitance: ,
Output Power: Break Down Voltage (Vbr) >> Peak RF Voltage + Bias Voltage.
[0050] The key concept of frequency multiplier 400 is based on generating multiples of input frequency using very strong capacitive non-linearity of SRD 420, which is realized almost by charge-storage effects. RF power level 422 at the input of the SRD diode 420 biases it to forward state and it behaves as low impedance. When the RF input 422 reverse biases the diode 420, it does not stop conducting until all the charge carriers have time to flow out of the diode's inert region. Once the diode is finally depleted of charge carriers, it changes its state from a short circuit to an open circuit very abruptly. At this point, the collapsing magnetic field in inductor 418 of impulse generator circuit 408 generates a voltage impulse with a very fast rise time and short pulse width. This pulse is rich in harmonic content that is equivalent to a number of frequencies, which are the multiples of the input frequency.
[0051] The pulse is then applied to the resonator circuit 410, temperature compensation circuit 412 and output filter 414 that converts it to a sinusoidal output voltage and filter out the desired frequency component. The impulse inductor Li 418 is connected in series between SRD diode 420 and transient tuning circuit 416 with capacitor Ct and inductor Lt as shown in FIG. 4B. it is calculated as given below in equation (2).
(2)
where,
tp: loaded time impulse width,
Cvr: Reverse bias diode capacitance,
RL: RL is load applied 424 on output side of SRD diode 420 as shown in FIG. 4B.
[0052] FIG. 4C illustrates an exemplary circuit diagram of temperature compensation circuit, in accordance with an embodiment of the present disclosure.
[0053] Referring to FIG. 4C, the temperature compensation/stabilisation circuit 412 is connected in series between resonator circuit 410 and output filter 414 to stabilise output power level variation across operating temperature range of -40 to 85°C without the use of a closed feedback loop. The temperature compensation/stabilisation circuit 412 can incorporate a circuit to control output level variation of frequency multiplier 400 across operating temperature with two logic controls for controlling attenuation slope versus temperature.
[0054] In an embodiment, the temperature compensation circuit 412 can include variable attenuator with control block device 426, at least two coupling capacitors (428-1, 428-2) connected in series at RFin and RFout nodes shown in FIG. 4C. At least two control signal voltages (430-1, 430-2) configured for controlling attenuation slope versus temperature is given at nodes ctrl1 and ctrl2 and power supply is given at node Vdd of the control block device 426.
[0055] The embodiments of the present disclosure described above provide several advantages. The one or more of the embodiments provides the frequency multiplier 400 that improves temperature stability of frequency multiplier 400 using unique temperature compensation circuit. The present disclosure controls attenuation slope versus temperature for fine optimisation of temperature variations across temperature with two logic controls. The present disclosure includes a circuit with supply to bias SRD diode to achieve better gain efficiency, and the frequency multiplier 400 provides narrowband filters at input and output to achieve better noise performance. Further, the frequency multiplier 400 using the SRD 420 can be used as a harmonic generator in transmitter or receiver subsystem of any electronic warfare system devoted to generating signals at specific frequencies.
[0056] It will be apparent to those skilled in the art that the temperature compensated frequency multiplier 400 of the disclosure may be provided using some or all of the mentioned features and components without departing from the scope of the present disclosure. While various embodiments of the present disclosure have been illustrated and described herein, it will be clear that the disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the scope of the disclosure, as described in the claims.

ADVANTAGES OF THE PRESENT DISCLOSURE
[0057] The present disclosure improves temperature stability of frequency multiplier using unique temperature compensation circuit.
[0058] The present disclosure controls attenuation slope versus temperature for fine optimisation of temperature variations across temperature with two logic controls.
[0059] The present disclosure provides a system with a supply to bias SRD diode to achieve better gain efficiency.
[0060] The present disclosure provides a gain efficient step recovery diode.
[0061] The present disclosure provides narrowband filters at input and output to achieve better noise performance.