Abstract: The present invention relates to a temperature control module which comprises plurality of potential networks wherein first network includes means (T1) for sensing temperature, other networks being operatively interconnected to each other communicating through plurality of isolator means and control logic block/circuit communicating with said potential network adapted to operate in a dual hysteresis band condition, wherein said control logic block comprises control logic upper band block (28) and control logic lower band block (27). The control logic blocks (27, 28) comprises plurality of amplifier blocks/circuits (29) adapted to receive signals from said potential network and compare the received signals with predetermined set values of the dual hysteresis band and/or variable hysteresis band.
FORM2
THE PATENTS ACT, 1970
(39 of 1970)
&
The Patents Rules, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)
Title of the invention - TEMPERATURE CONTROL MODULE WITH
DUAL VARIABLE HYSTERESIS BAND
2. Applicant
(a) NAME : LARSEN & TOUBRO LIMITED
(b) NATIONALITY : An Indian Company
(c) ADDRESS : L&T House, Ballard Estate, Mumbai 400 001,
State of Maharashtra, India
3. PREAMBLE TO THE DESCRIPTION
The following specification particularly describes the invention and the manner in which it is to be performed :
FIELD OF INVENTION
The present invention relates to a temperature control module for operating devices to monitor and limit temperatures. More particularly, the invention relates to a temperature control module comprising dual variable hysteresis band and having a control logic module adapted to actuate devices to sense and limit the ambient or surface temperature within a variable range of temperatures providing flexibility of the sensing and limiting operation. The temperature control module of the invention finds its applications in control of temperatures of enclosures, furnaces, stand alone control of ambient temperature and any application which employs ON-OFF control method for controlling temperature and the like.
BACKGROUND AND PRIOR ART
Hysteresis is a phenomenon in which the response of a physical system to an external influence depends not only on the present magnitude of that influence but also on the previous history of the system. Expressed mathematically, the response to the external influence is a doubled-valued function; one value applies when the influence is increasing, the other applies when the influence is decreasing.
Magnetic hysteresis occurs when a permeable material like soft iron is magnetized by being subjected to an external magnetic field. The induced magnetization tends to lag behind the magnetizing force. If a field is applied to an initially unmagnetized sample and is then removed, the sample retains a residual magnetization (it has become a permanent magnet). The graph of the magnetic induction B versus the magnetic field H
2
is called a hysteresis loop. The area of the loop is proportional to the energy dissipated as heat when the system goes through a cycle; this represents a considerable energy loss in alternating-current machinery.
Thermal hysteresis occurs when the value of a given property of a body depends not only on the body's temperature but also on whether the temperature is rising or falling. An example is the dielectric constant versus temperature for certain crystals. Another kind of hysteresis is a common feature of "control or cybernetic systems. A familiar example is a thermostat controlling a source of heat and set at some temperature To. When the room temperature falls through To to some lower temperature Ti, the heating power is switched on.
GB 1199612 discloses a hysteresis band which is fixed and has a value of 5 degrees F. It follows set point and the system comprises of plurality of thermistors. In the present invention the module comprises of single thermistor and has a variable hysteresis band.
GB 1206808 describes control circuit comprising two thermistors for controlling a heater and a cooler for controlling temperature of oil.
JP2000030719 makes use of a microprocessor for setting the reference levels.
In none of the prior art dual hysteresis band and use of only one thermistor have been found.
3
Thus there is need to provide for a temperature control module comprising dual variable hysteresis adapted to actuate devices to sense and limit the ambient or surface temperature within a variable range of temperatures.
The present inventors have surprisingly found that a temperature control module with dual hysteresis band comprising a control logic designed in a manner and can control and monitor the ambient or surface temperature of the monitoring and/or controlling devices in a variable hysteresis band thereby providing flexibility in the sensing and controlling operation.
OBJECTS OF INVENTION
Thus one object of the present invention is to provide a temperature control module to sense and limit the ambient or surface temperature within a variable range of temperatures.
Another object of the present invention is to provide a control logic module for transistor turn-on and/or turn-off.
Yet another object of the present invention is to provide dual hysteresis band operation.
SUMMARY OF INVENTION
Thus according to one aspect of the present invention there is provided a temperature control module comprising :,
plurality of potential networks wherein first network includes means for sensing temperature, other networks being
4
operatively interconnected to each other communicating through plurality of isolator means; and
control logic block/circuit communicating with said potential network adapted to operate in a dual hysteresis band condition, wherein said control logic block comprises control 'logic upper band block and control logic lower band block, wherein
said control logic block/circuits comprising plurality of amplifier blocks/circuits adapted to receive signals from said potential network and compare the received signals with predetermined set values of the dual hysteresis band and/or variable hysteresis band.
DETAILED DESCRIPTION OF INVENTION
The temperature control module of the present invention comprises a potential network which includes means for sensing temperature. The said network is a potential divider network (hereinafter referred to as first potential divider network) wherein is placed the means for sensing temperature which comprises a thermistor.
In another embodiment of the present invention the first potential divider circuit comprises of resistors Rl and R2 operatively connected to the thermistor.
In another embodiment of the present invention the control logic block/circuit comprises of two parts - one for upper band and other for lower band of temperatures. Two blocks are connected to the first potential divider network by means of conductors.
5
First stage of the control logic block for upper band of temperatures comprises non-inverting amplifier whose gain is decided by a set of resistors R3 and R4 by transfer function:
H(s) -._!.,.+ (R3/R4)*[l/(l + sR4C3) ] •
The conductor connecting the first potential divider network comprises capacitor means which are decoupling capacitors CI and C2 adapted to suppress noise and/or any harmonics / transients / surges in the circuit. The non-inverting amplifier is connected to a second amplifier, which is an operational amplifier by means of another conductor. The operational amplifier acts as comparator whose reference depends on its own output and reference toggles between two levels of hysteresis curve whose set-points are set by the user through switch means SI and S2.
Yet in another embodiment of the present invention, the output of the operational amplifier is connected to plurality of transistors Ql and Q2 by means of conductors through resistors Rll and R14 and logical gate means. The logic gate is a NOT gate. The transistors Ql and Q2 used here are switching transistors adapted to switch ON and OFF two voltage/potential divider networks (hereinafter referred to as second and third potential divider networks) comprising plurality of resistors R9, RIO and R12, R13 respectively. Isolator means are provided so as to isolate the second and third potential dividers. The isolator means comprises plurality of diodes Dl and D2.
When output of the operational amplifier is low, transistor Ql does not get sufficient forward bias and hence is OFF .At the same time, the output of NOT gate connected to the operational amplifier is pulled high by pull-up resistor R7 which biases
6
the transistor Q2 into conduction. Hence the third voltage divider consisting of R12 and R13 is turned ON and set point PI of hysteresis curve is defined. The reference point PI can be changed by user through switch S2 by selecting either of the resistors R13, R25 or R26 providing flexibility in operation.
When output of the operational amplifier is high, transistor Q2 turns OFF as it does not get sufficient forward bias. At the same time, transistor Ql is biased into conduction and it turns on second voltage/potential divider consisting of resistors R9 and RIO. Hence setpoint P2 of hysteresis curve of is defined.
In another embodiment of the present invention reference point P2 can be changed by user through switch SI by selecting either of the resistors RIO, R23 or R24 providing flexibility in operation.
Output of the operational amplifier drives the final output through NOT gate which energizes coil of Relay 1 connected to the NOT gate by pull-up action. When output of is low the output of Not gate is high and hence both terminals of coil of relay 1 are at same potential. Therefore no current flows and coil of relay 1 is OFF and relay remains in same state. When output is high , NOT gate output is low. Therefore the other terminal of coil of relay 1 is grounded which in turn provides current to the coil of associated electromechanical output relay 1 causing the relay to change state.
Similarly, set points P3 and P4 of the hysteresis curve are defined by another operational amplifier and switching
7
transistors Q4 and Q3 along with switches S4 and S3. Final output Relay 2 is driven by similar action as is the case for the upper band circuit.
Temperature control logic for upper band is achieved by connecting the output of amplifier to non inverting terminal 'of the first non-inverting amplifier as described herein before and connecting output of reference logic circuit to inverting input of the said amplifier.
Temperature control logic for lower band is achieved by connecting the output of non-inverting amplifier to inverting terminal of the second amplifier and connecting output of reference logic circuit to non inverting input of it.
Thus in this circuit the two setpoints of each band i.e upper and lower band can be changed effectively giving a variable hysteresis band. For the upper temperature band the corresponding output (relay 1) turns ON when the sensed temperature increases above the setpoint PI and the output (relay 1) turns OFF when the sensed temperature decreases below the setpoint P2.
Similarly, for lower temperature band when the sensed temperature decreases below the setpoint P3, corresponding output (relay 2) turns ON and when the sensed temperature increases above the setpoint P4 then the output (relay 2) turns OFF.
The temperature control module can be used in applications related to controlling temperatures of Enclosures, applications related to temperatures of furnaces (with the use
8
of a suitable sensor), applications related to stand alone control of ambient temperature. Thus it can be used for any application, which employs On-Off Control method for controlling the Temperature. In the present embodiment it is used in switchboards for limiting the temperature of the ambient inside the panel which does not limit the scope of the 'invention.
BRIEF DESCRIPTION OF ACCOMPANYING FIGURES
'Figure 1 illustrates the circuit of the temperature control module of the present invention.
Figure 2 illustrates the dual hysteresis band curve.
Figure 3 illustrates the block representation of the temperature module of the present invention.
DETAILED DESCRIPTION OF ACCOMPANYING FIGURES
In figure 1 the circuit of the temperature module of the present invention is illustrated. The given circuit comprises thermistor Tl placed in a voltage divider network consisting resistors Rl and R2. Conductor 2 is adapted to feed voltage across R2 to the logic circuit for the upper band and conductor 3 is used for lower band. First stage of the upper band consists of a non inverting amplifier 18 whose gain is decided by resistors R3 and R4. Decoupling capacitors CI and C2 are used to suppress noise. Output of amplifier 18 is given to next stage through conductor 4. Operational amplifier (opamp) 19 acts as a comparator whose reference depends on its own output. Reference toggles between two levels of hysteresis
9
curve whose set-points are set by the user through switch SI and S2.
Output of opamp 19 is connected to transistors Ql through resistor Rll and to transistor Q2 through resistor R14 via a NOT gate 23. Ql and Q2 are switching transistors used to switch ON or OFF the second and the third voltage divider networks consisting of resistors R9, RIO and R12, R13 respectively. Both voltage dividers are isolated using diodes Dl and D2. When output of opamp 19 is low, Ql does not get sufficient forward bias and hence is OFF .At the same time, the output of NOT gate 23 is pulled high by pull-up resistor R7, which biases the transistor Q2 into conduction. Hence the voltage divider consisting of R12 and R13 is turned ON and set point PI of hysteresis curve of fig.2 is defined.
Output of opamp 19 drives the final output through NOT gate 22.Coil of Relay 1 is energized by pull-up action. When output of opamp 19 is 1OWN the output of Not gate is high and hence both terminals of coil of relay 1 are at same potential. Therefore no current flows and coil of relay 1 is OFF and relay remains in same state. When output of opamp 19 is high , Not gate output is low. Therefore the other terminal of coil of relay 1 is grounded which in turn provides current to the coil of associated electromechanical output relay 1 causing the relay to change state.
Block representation of the temperature module is illustrated in figure 3. Lower band block (27) and upper band block (28) comprises amplifier block (29), comparator block (30), device actuator block (31) and control logic (32). Signals are sent from thermistor (Tl) to the amplifiers blocks (29) .
10
The invention has been described in a preferred form only and many variations may be made in the invention which will still be comprised within its spirit. The invention is not limited to the details cited above. The number of capacitors, resistors and transistors may vary but this does not restricts 'scope of the invention. The logic gates used in the present invention are NOT gates. Other combinations of logic gates giving same operation equivalence as NOT gate can be used to obtain flexibility of operation within the upper and the lower 'band of temperatures and still the invention can be performed. The temperature control module thus conceived is susceptible of numerous modifications and variations, all the details may furthermore be replaced with elements having technical equivalence which will still be comprised within its true spirit.
11
WE CLAIM
1. A temperature control module comprising :
plurality of potential networks wherein first network includes means for sensing temperature, other networks being operatively interconnected to each other communicating through plurality of isolator means; and
control logic block/circuit communicating with said potential network adapted to operate in a dual hysteresis band condition, wherein said control logic block comprises control logic upper band block and control logic lower band block, wherein
said control logic block/circuits comprising plurality of amplifier blocks/circuits adapted to receive signals from said potential network and compare the received signals with predetermined set values of the dual hysteresis band and/or variable hysteresis band.
2. A temperature control module as claimed in claim 1, wherein the first potential network is potential divider network comprising plurality of resistors operatively connected to the temperature sensing means;
3. A temperature control module as claimed in claims 1 and 2, wherein the temperature sensing means comprises thermistor.
12
4. A temperature control module as claimed in claim 1, wherein the amplifier block/circuit comprises non-inverting amplifier communicating with set of resistors so as to decide amplifier gain.
5. A temperature control module as claimed in claim 1, wherein the control logic upper block comprises capacitor means adapted to suppress noise and/or any harmonics / transients / surges in the circuit.
'6. A temperature control module as claimed in claim 1, wherein the amplifier block further comprises of operational amplifier means, preferably comparator is adapted to provide toggling in its reference between two levels of predetermined set points of hysteresis curve.
7. A temperature control module as claimed in claim 1, wherein the plurality of potential networks comprises second and third potential divider networks.
8. A temperature control module as claimed in claim 1, wherein the isolator means comprises diode means adapted to isolate reference potential dividers network..
9. A temperature control module as claimed in claim 1, wherein the control logic upper band block comprises logic gate means adapted to provide output signals for energizing and de-energizing relay coil means.
10. A temperature control module as claimed in claim 1, the control logic lower block comprises capacitor means
13
adapted to suppress noise and/or any harmonics / transients / surges in the circuit.
11. A temperature control module as claimed in claim 1, wherein the control logic lower band block comprises logic gate means adapted to provide output signals for energizing and de-energizing relay coil means.
12. A temperature control module as claimed in claims 12 to
14, wherein the logic gate means comprises plurality of
NOT gates.
13. A temperature control module as claimed in claims 1 to
15, wherein the control logic upper band block/circuit
and the control logic lower band block/circuit are
adapted to actuate relay means depending the sense
temperatures corresponding to predetermined set points.
Dated this 17th day of July 2006.
14
Abhishek Sen
of S. Majumdar & Co. Applicant's agent
ABSTRACT
Title : TEMPERATURE CONTROL MODULE WITH DUAL VARIABLE HYSTERESIS BAND
The present invention relates to a temperature control module which comprises plurality of potential networks wherein first network includes means (Tl) for sensing temperature, other networks being operatively interconnected to each other communicating through plurality of isolator means and control logic block/circuit communicating with said potential network adapted to operate in a dual hysteresis band condition, wherein said control logic block comprises control logic upper band block (28) and control logic lower band block (27). The control logic blocks (27, 28) comprises plurality of amplifier blocks/circuits (29) adapted to receive signals from said potential network and compare the received signals with predetermined set values of the dual hysteresis band and/or variable hysteresis band.
Figure 3
| Section | Controller | Decision Date |
|---|---|---|
| # | Name | Date |
|---|---|---|
| 1 | 1149-MUM-2006-CORRESPONDENCE(05-05-2010).pdf | 2010-05-05 |
| 1 | 1149-MUM-2006-RELEVANT DOCUMENTS [26-09-2023(online)].pdf | 2023-09-26 |
| 2 | 1149-MUM-2006-CORRESPONDENCE(IPO)-(FER)-(17-01-2014).pdf | 2014-01-17 |
| 2 | 1149-MUM-2006-RELEVANT DOCUMENTS [30-09-2022(online)].pdf | 2022-09-30 |
| 3 | 1149-MUM-2006-RELEVANT DOCUMENTS [24-09-2021(online)].pdf | 2021-09-24 |
| 3 | 1149-MUM-2006-CORRESPONDENCE(IPO)-(HEARING NOTICE)-(30-10-2015).pdf | 2015-10-30 |
| 4 | 1149-MUM-2006-FORM 2(TITLE PAGE)-(GRANTED)-(11-01-2016).pdf | 2016-01-11 |
| 4 | 1149-MUM-2006-ASSIGNMENT WITH VERIFIED COPY [09-03-2021(online)].pdf | 2021-03-09 |
| 5 | 1149-MUM-2006-FORM-16 [09-03-2021(online)].pdf | 2021-03-09 |
| 5 | 1149-MUM-2006-FORM 2(GRANTED)-(11-01-2016).pdf | 2016-01-11 |
| 6 | 1149-MUM-2006-POWER OF AUTHORITY [09-03-2021(online)].pdf | 2021-03-09 |
| 6 | 1149-MUM-2006-DRAWING(GRANTED)-(11-01-2016).pdf | 2016-01-11 |
| 7 | 1149-MUM-2006-RELEVANT DOCUMENTS [29-03-2020(online)].pdf | 2020-03-29 |
| 7 | 1149-MUM-2006-DESCRIPTION(GRANTED)-(11-01-2016).pdf | 2016-01-11 |
| 8 | 1149-MUM-2006-RELEVANT DOCUMENTS [23-03-2019(online)].pdf | 2019-03-23 |
| 8 | 1149-MUM-2006-CORRESPONDENCE(IPO)-(11-01-2016).pdf | 2016-01-11 |
| 9 | 1149-MUM-2006-Abstract-160115.pdf | 2018-08-09 |
| 9 | 1149-MUM-2006-CLAIMS(GRANTED)-(11-01-2016).pdf | 2016-01-11 |
| 10 | 1149-MUM-2006-ABSTRACT(GRANTED)-(11-01-2016).pdf | 2016-01-11 |
| 11 | 1149-mum-2006-abstract.pdf | 2018-08-09 |
| 11 | Form 27 [30-03-2017(online)].pdf | 2017-03-30 |
| 12 | 1149-MUM-2006-Amended Pages Of Specification-160115.pdf | 2018-08-09 |
| 12 | 1149-MUM-2006-RELEVANT DOCUMENTS [30-03-2018(online)].pdf | 2018-03-30 |
| 13 | 1149-MUM-2006-Amended Pages Of Specification-281215.pdf | 2018-08-09 |
| 13 | abstract1.jpg | 2018-08-09 |
| 14 | 1149-MUM-2006-Claims-160115.pdf | 2018-08-09 |
| 14 | 1149-MUM-2006_EXAMREPORT.pdf | 2018-08-09 |
| 15 | 1149-MUM-2006-Claims-281215.pdf | 2018-08-09 |
| 15 | 1149-MUM-2006-REPLY TO HEARING-281215.pdf | 2018-08-09 |
| 16 | 1149-MUM-2006-POWER OF ATTORNEY(25-8-2006).pdf | 2018-08-09 |
| 17 | 1149-MUM-2006-OTHERS-160115.pdf | 2018-08-09 |
| 17 | 1149-mum-2006-claims.pdf | 2018-08-09 |
| 18 | 1149-MUM-2006-MARKED COPY-281215.pdf | 2018-08-09 |
| 18 | 1149-MUM-2006-CORRESPONDENCE(1-1-2010).pdf | 2018-08-09 |
| 19 | 1149-MUM-2006-CORRESPONDENCE(10-9-2013).pdf | 2018-08-09 |
| 19 | 1149-mum-2006-form-3.pdf | 2018-08-09 |
| 20 | 1149-MUM-2006-CORRESPONDENCE(16-3-2009).pdf | 2018-08-09 |
| 20 | 1149-mum-2006-form-2.pdf | 2018-08-09 |
| 21 | 1149-MUM-2006-CORRESPONDENCE(25-8-2006).pdf | 2018-08-09 |
| 22 | 1149-MUM-2006-CORRESPONDENCE(26-9-2011).pdf | 2018-08-09 |
| 22 | 1149-mum-2006-form-1.pdf | 2018-08-09 |
| 23 | 1149-MUM-2006-CORRESPONDENCE(IPO)-(19-7-2006).pdf | 2018-08-09 |
| 23 | 1149-MUM-2006-Form 2(Title Page)-160115.pdf | 2018-08-09 |
| 24 | 1149-MUM-2006-Correspondence-291015.pdf | 2018-08-09 |
| 24 | 1149-MUM-2006-FORM 2(TITLE PAGE)-(19-7-2006).pdf | 2018-08-09 |
| 25 | 1149-mum-2006-correspondence-received.pdf | 2018-08-09 |
| 25 | 1149-MUM-2006-FORM 18(16-3-2009).pdf | 2018-08-09 |
| 26 | 1149-mum-2006-description (complete).pdf | 2018-08-09 |
| 26 | 1149-MUM-2006-Form 1-160115.pdf | 2018-08-09 |
| 27 | 1149-MUM-2006-Drawing-160115.pdf | 2018-08-09 |
| 27 | 1149-MUM-2006-FORM 1(25-8-2006).pdf | 2018-08-09 |
| 28 | 1149-mum-2006-drawings.pdf | 2018-08-09 |
| 28 | 1149-MUM-2006-Examination Report Reply Recieved-160115.pdf | 2018-08-09 |
| 29 | 1149-mum-2006-drawings.pdf | 2018-08-09 |
| 29 | 1149-MUM-2006-Examination Report Reply Recieved-160115.pdf | 2018-08-09 |
| 30 | 1149-MUM-2006-Drawing-160115.pdf | 2018-08-09 |
| 30 | 1149-MUM-2006-FORM 1(25-8-2006).pdf | 2018-08-09 |
| 31 | 1149-mum-2006-description (complete).pdf | 2018-08-09 |
| 31 | 1149-MUM-2006-Form 1-160115.pdf | 2018-08-09 |
| 32 | 1149-mum-2006-correspondence-received.pdf | 2018-08-09 |
| 32 | 1149-MUM-2006-FORM 18(16-3-2009).pdf | 2018-08-09 |
| 33 | 1149-MUM-2006-Correspondence-291015.pdf | 2018-08-09 |
| 33 | 1149-MUM-2006-FORM 2(TITLE PAGE)-(19-7-2006).pdf | 2018-08-09 |
| 34 | 1149-MUM-2006-CORRESPONDENCE(IPO)-(19-7-2006).pdf | 2018-08-09 |
| 34 | 1149-MUM-2006-Form 2(Title Page)-160115.pdf | 2018-08-09 |
| 35 | 1149-mum-2006-form-1.pdf | 2018-08-09 |
| 35 | 1149-MUM-2006-CORRESPONDENCE(26-9-2011).pdf | 2018-08-09 |
| 36 | 1149-MUM-2006-CORRESPONDENCE(25-8-2006).pdf | 2018-08-09 |
| 37 | 1149-MUM-2006-CORRESPONDENCE(16-3-2009).pdf | 2018-08-09 |
| 37 | 1149-mum-2006-form-2.pdf | 2018-08-09 |
| 38 | 1149-MUM-2006-CORRESPONDENCE(10-9-2013).pdf | 2018-08-09 |
| 38 | 1149-mum-2006-form-3.pdf | 2018-08-09 |
| 39 | 1149-MUM-2006-CORRESPONDENCE(1-1-2010).pdf | 2018-08-09 |
| 39 | 1149-MUM-2006-MARKED COPY-281215.pdf | 2018-08-09 |
| 40 | 1149-mum-2006-claims.pdf | 2018-08-09 |
| 40 | 1149-MUM-2006-OTHERS-160115.pdf | 2018-08-09 |
| 41 | 1149-MUM-2006-POWER OF ATTORNEY(25-8-2006).pdf | 2018-08-09 |
| 42 | 1149-MUM-2006-Claims-281215.pdf | 2018-08-09 |
| 42 | 1149-MUM-2006-REPLY TO HEARING-281215.pdf | 2018-08-09 |
| 43 | 1149-MUM-2006-Claims-160115.pdf | 2018-08-09 |
| 43 | 1149-MUM-2006_EXAMREPORT.pdf | 2018-08-09 |
| 44 | 1149-MUM-2006-Amended Pages Of Specification-281215.pdf | 2018-08-09 |
| 44 | abstract1.jpg | 2018-08-09 |
| 45 | 1149-MUM-2006-Amended Pages Of Specification-160115.pdf | 2018-08-09 |
| 45 | 1149-MUM-2006-RELEVANT DOCUMENTS [30-03-2018(online)].pdf | 2018-03-30 |
| 46 | Form 27 [30-03-2017(online)].pdf | 2017-03-30 |
| 46 | 1149-mum-2006-abstract.pdf | 2018-08-09 |
| 47 | 1149-MUM-2006-ABSTRACT(GRANTED)-(11-01-2016).pdf | 2016-01-11 |
| 48 | 1149-MUM-2006-Abstract-160115.pdf | 2018-08-09 |
| 48 | 1149-MUM-2006-CLAIMS(GRANTED)-(11-01-2016).pdf | 2016-01-11 |
| 49 | 1149-MUM-2006-CORRESPONDENCE(IPO)-(11-01-2016).pdf | 2016-01-11 |
| 49 | 1149-MUM-2006-RELEVANT DOCUMENTS [23-03-2019(online)].pdf | 2019-03-23 |
| 50 | 1149-MUM-2006-DESCRIPTION(GRANTED)-(11-01-2016).pdf | 2016-01-11 |
| 50 | 1149-MUM-2006-RELEVANT DOCUMENTS [29-03-2020(online)].pdf | 2020-03-29 |
| 51 | 1149-MUM-2006-DRAWING(GRANTED)-(11-01-2016).pdf | 2016-01-11 |
| 51 | 1149-MUM-2006-POWER OF AUTHORITY [09-03-2021(online)].pdf | 2021-03-09 |
| 52 | 1149-MUM-2006-FORM-16 [09-03-2021(online)].pdf | 2021-03-09 |
| 52 | 1149-MUM-2006-FORM 2(GRANTED)-(11-01-2016).pdf | 2016-01-11 |
| 53 | 1149-MUM-2006-FORM 2(TITLE PAGE)-(GRANTED)-(11-01-2016).pdf | 2016-01-11 |
| 53 | 1149-MUM-2006-ASSIGNMENT WITH VERIFIED COPY [09-03-2021(online)].pdf | 2021-03-09 |
| 54 | 1149-MUM-2006-RELEVANT DOCUMENTS [24-09-2021(online)].pdf | 2021-09-24 |
| 54 | 1149-MUM-2006-CORRESPONDENCE(IPO)-(HEARING NOTICE)-(30-10-2015).pdf | 2015-10-30 |
| 55 | 1149-MUM-2006-RELEVANT DOCUMENTS [30-09-2022(online)].pdf | 2022-09-30 |
| 55 | 1149-MUM-2006-CORRESPONDENCE(IPO)-(FER)-(17-01-2014).pdf | 2014-01-17 |
| 56 | 1149-MUM-2006-CORRESPONDENCE(05-05-2010).pdf | 2010-05-05 |
| 56 | 1149-MUM-2006-RELEVANT DOCUMENTS [26-09-2023(online)].pdf | 2023-09-26 |