FIELD OF THE INVENTION
This invention relates to test setup module for the complete diagnostic & functional testing of
Micro Controller based Audio board.
BACKGROUND OF THE INVENTION
The embedded systems are based on highly-integrated 32-bit microcontrollers, combining highperformance
data manipulation capabilities with powerful peripheral subsystems. The function
of the Audio Module is to digitize 4 audio input signals coming from aircraft cockpit. The digitized
audio signal is compressed by DSP processor and sent to main CPU through shared memory.
In this application two channels are used and the remaining two channels are spare. Voice
module consists of audio input channels to acquire the audio signal from the aircraft and audio
output channel to retrieve the audio signal, which has saved in memory & for playback purpose.
The test facility for diagnostic testing of Audio Module utilizes the microcontroller for self testing
& testing of all internal resources as per the user provided commands from interfacing device.
The interfacing devices indicates the resource to be tested & the ADSP micro processor
performs the internal testing & sends back the test result on RS-232 interface attached to the
module with interfacing device. The test connector is provided separately to test individual
components in the board. By providing suitable parameters to the board, each component can
be tested.
Further the test setup ensures that the functional testing can be carried out to ensure the
serviceability of the audio module & so that all components that have been individually tested
are working satisfactorily in integrated mode. The test setup simulates the required signals that
are received from the aircraft & the voice data is fed as per the specified limits of voltage &
signal strength.
SUMMARY OF PRESENT INVENTION
At start-up (Power ‘ON’) time, diagnostic software is programmed inside the memory & the
module is then connected to an interfacing device. The diagnostic software interacts with the
host PC or interfacing device & prompts the user for the test that has to be carried out. The
testing of resources is exhaustive & covers maximum resources by way of reading & writing of
memory devices, looping back of transmitter & receivers on the board. This invention provides
the user with every aid to simulate & read back the data & declaring the serviceability of Audio
module.
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the present invention become more apparent and
descriptive in the description when considered together with figures/flow charts presented:
Figure 1: is a Block Diagram of Audio Module
Figure 2: is a Block Diagram of Test Set up of Audio Module Testing
DETAILED DESCRIPTION
The function of this card is to digitize 4 audio input signals coming from aircraft cockpit.
The digitized audio signal is compressed by DSP processor and sent to main CPU through
shared memory. In this application two channels are used and the remaining two channels are
spare. It also has one audio channel output for audio replay purpose.
Voice module consists of audio input channels to acquire the audio signal from the
aircraft and audio output channel to retrieve the audio signal, which has saved in memory & for
playback purpose.
ADSP:
The ADSP SHARC series is a 32-bit ADSP based processor used in this module. The
salient feature of this processor is as listed below:
• 32-bit floating point computational unit.
• 4 Mbit on chip dual-port SRAM.
• It operates at a speed of 40 MIPS, 25nS instruction rate.
• Four Independent Buses for Dual Data Fetch, Instruction Fetch, and No intrusive I/O.
• 120 MFLOPS Peak, 80 MFLOPS Sustained Performances.
• Parallel computations are performed in this processor.
The processor receives the serial digital data from CODEC, and then compresses the digital
data based on compression algorithm stored in it. This compressed data is finally stored in the
shared Memory DPRAM. Then the main processor board can access this data from DPRAM.
CODEC and Filters:
AUDIO Signals entering from the Aircraft cockpit is fed to the multi-channel CODEC IC
through a low pass filter, which eliminates any high frequency or noise components present in
the audio signals. A passive Filter is used for a cut-off frequency of 3400 Hz. It has two
independent stereo ADCs & three independent stereo DAC’s using multibit sigma-delta
architecture. The Codec totally has 4 ADC and 6 DAC channels. These devices are basically
operated in differential mode and also can be operated in single ended mode.
Codec can be configured to operate at a sampling rate of 48 OR 96 kHz. The ADCs
include an on-board digital decimation filter with 120dB stop band attenuation & linear phase
response.
Resolution of all ADC’s is 24 bits. The codec has an SPI control port to permit programming the
internal control registers for the ADCs & DAC’s and also to read peak level information for each
ADC.
The ADC serial data output format defaults to popular I2S format is given to ADSP
through a shared memory.
Memory Block:
The Voice module consists of mainly three memories namely:
I. Dual port RAM (DPRAM):
The DPRAM has a high speed 5.0 V, 8K X 16 memory configuration, with a 20ns access
time. The DP-SRAM stores the data from CODEC through ADSP and at the same time this data
can access by processor module.
II. S-RAM:
The SRAM has a high-speed 5.0V 256K X 16 memory configuration, with a 15ns access
time.
III. BOOT FLASH:
The BOOT Flash has a high-speed 5.0V 16M-bit memory configuration, with a 70ns
access time. It is used to store the compressed program code for the ADSP processor to load it
in program memory when power on.
CPLD:
This is a programmable logic device. It is programmed for address decoding, Mux
selection and chip select logic.
Test Connector:
The test connector is provided separately to test individual components in the board. By
providing suitable parameters to the board, each component can be tested.
FUNCTIONAL TEST:
Following are the Functional test requirements i.e. the tests conducted on the board:
• S/W Version ID and Checksum test
• DSP Test
• SRAM Test
• DPRAM Test
• Flash Test
• CPLD Test
• CODEC Test
• Audio IO Test
1. S/W Version Number and Checksum test:
Upon receipt of the user command through serial port the AUDIO module perform the
following steps:
• Reads the stored checksum and software version
• Arranges the checksum and version in the required predefined format.
• Sends the result to the ATE/Test PC via serial port.
Checksum and version is displayed on the ATE/Hyper terminal of Test PC.
2. DSP Test:
Upon receipt of the user command through serial port the AUDIO module perform the
following steps:
• The DSP Performs predefined register test.
• Upon successful operation, DSP Sets the Result as PASS else FAIL.
• Sends the result to the ATE/Test PC via serial port.
•
Test result is displayed on the ATE/Hyper terminal of Test PC.
3. SRAM Test:
Upon receipt of the user command through serial port the AUDIO module perform the
following steps:
• Performs the below mentioned tests in the sequence as listed to test the SRAM:
1. Constant data write and read Test
a. In this test known data is written and validated by reading again. (for
example: 0x55555555 and 0xAAAAAAAA)
2. Address Check Test
a. In this test the data is same as that of the address.
b. In this test the address is varied in sequence from min to max value.
c. Read operation is performed from min to max.
d. The data is same as that of address value from which it has been read.
3. Marching one’s Test
a. In this test out of 32-bit one bit is set to Logic 1 and rest to logic 0. This
type of pattern is written to every address by shifting the position of logic
1 bit (i.e. 0x00000001, 0x00000002, 0x00000004…..0x80000000).
b. Read back the value for validation.
c. tested for 32-bit data length.
4. Marching zero’s Test
a. In this test out of 32-bit one bit is set to Logic 0 and rest to logic 1. This
type of pattern is written to every address by shifting the position of logic
0 bit (i.e. 0xFFFFFFFE, 0xFFFFFFFD, 0xFFFFFFFB …..0x7FFFFFFF).
b. Read back the value for validation.
c. tested for 32-bit data length.
• The next test in the above sequence is conducted only when the current test
performed is OK.
• If any of the tests fails the test result is declared as FAIL otherwise PASS.
• Sends the result to the ATE/Test PC via serial port.
Test result is displayed on the ATE/Hyper terminal of Test PC.
4. DPRAM Test:
Upon receipt of the user command through serial port the AUDIO module perform the
following steps:
• Performs the below mentioned tests in the sequence as listed to test the DPRAM:
1. Constant data write and read Test (for example: writing 0x5555 and 0xAAAA)
2. Address Check Test.
3. Marching one’s Test.
4. Marching zero’s Test.
• The next test in the above sequence is conducted only when the current test performed
is OK.
• If any of the tests fails the test result is declared as FAIL otherwise PASS.
• Sends the result to the ATE/Test PC via serial port.
Test result is displayed on the ATE/Hyper terminal of Test PC.
5. Flash Test:
Upon receipt of the user command through serial port the AUDIO module perform the
following steps:
• Computes the checksum by XORing the data.
• Sends the result to the ATE/Test PC via serial port.
Test result is displayed on the ATE/Hyper terminal of Test PC.
6. CPLD Test:
Upon receipt of the user command through serial port the AUDIO module perform the
following steps:
• Reads the data from CPLD Info Register (8 bit Register).
• Sends the result to the ATE/Test PC via serial port.
Test result displayed on the ATE/Hyper terminal of Test PC.
7. CODEC Test:
Upon receipt of the user command through serial port the AUDIO module perform the
following steps:
• Configure the CODEC
• Enable the DAC output to generate the standard 1KHz frequency.
• Set the Mux selection register to select the Audio input channel.
• Read back the data.
• Perform the FFT.
• Compare the value fort the correctness within the allowable tolerance.
• If OK set the result as PASS else FAIL.
• Repeat the above steps for 4 CODEC input channels.
• Sends the result and frequency to the ATE/Test PC via serial port.
Test result is displayed on the ATE/Hyper terminal of Test PC.
8. Audio IO Test
Upon receipt of the user command through serial port the AUDIO module perform the
following steps:
• Configure the CODEC
• Generate the 1 KHz on the Audio output channel.
• Set the Mux selection register to select the Audio input channel.
• Read back the data.
• Perform the FFT.
• Compare the value fort the correctness within the allowable tolerance.
• If OK set the result as PASS else FAIL.
• Sends the result and frequency to the ATE/Test PC via serial port.
• Perform the above steps for the other Audio input channels.
Test result is displayed on the ATE/Hyper terminal of Test PC.

WE CLAIMS:-
Accordingly, the description of the present invention is to be considered as illustrative only and is for the purpose of teaching those skilled in the art of the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and exclusive use of all modifications which are within the scope of the appended claims is reserved. The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Test Setup for testing of microcontroller based Audio Module Comprising;
a. Four channels of audio inputs, which are sampled and compressed on-board using CODECS &
b. The data is stored in the DUAL port RAM and the stored data is transferred to the PMM by the processor board, using the dual port RAM access.
c. RS422 used for receiving the data on HyperTerminal for performs the audio module test.

2. Test Setup for testing of microcontroller based Audio Module of claim 1 wherein the diagnostic software interacts with the host PC or interfacing device & prompts the user for the test that has to be carried out.

3. Test Setup for testing of microcontroller based Audio Module as claimed in any of the preceding claims wherein the testing of resources is exhaustive & covers maximum resources by way of reading & writing of memory devices, looping back of transmitter & receivers on the board. ,TagSPECI:As per Annexure-II