Description:TECHNICAL FIELD
The present disclosure relates to a field of power magnetics. Moreover, the present disclosure relates to a testing apparatus for power magnetics and a method of using the testing apparatus for power magnetics.
BACKGROUND
In the field of electrical engineering and energy conversion, there exists a wide range of power convertors that exchange power through various modes, including, but not limited to DC-AC, AC-DC, AC-AC, and DC-DC conversions. A significant portion, approximately 50–60%, of the weight and volume of such power converters includes power magnetics that is critical for energy conversion and power transfer. Further, due to involvement of wideband-gap semiconductors, the power converters can operate at higher switching frequencies, offering numerous benefits. However, operation of the power convertors at the higher switching frequencies may increase core and copper losses in magnetic components of the power convertors, ultimately diminishing overall efficiency. The increased core and copper losses in the magnetic component can be estimated for optimization of power magnetics. However, the core and copper losses in the magnetic component may be difficult to measure due to the constraints of compact packaging and limited access to terminals for connecting measurement equipment. Furthermore, the presence of winding losses may introduce inaccuracies in core loss estimation, further complicating in-situ characterization process.
Conventionally, various excitation circuits have been proposed to facilitate loss characterization. For example, a series resonant circuit may be employed to measure core loss, but this approach is only suitable for sinusoidal excitations at a single frequency. Further, while replacing the resonant capacitor with a transformer may help in minimizing phase errors, this approach still lacks the flexibility to perform measurements under arbitrary excitation conditions. Traditional testing apparatus can only simulate a limited number of electrical scenarios. However, in real world, there is a variety of complex electrical scenarios that may affect the power magnetics. Thus, there exists a technical problem of how to test practical and real-world operating conditions of power magnetics.
Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with the conventional method of testing power magnetics in various electrical scenarios and measuring core and copper losses.
SUMMARY
The present disclosure provides a testing apparatus for power magnetics. The present disclosure provides a solution to the technical problem of how to evaluate the performance of magnetic components in various electrical excitation scenarios. An aim of the present disclosure is to provide a solution that overcomes at least partially the problems encountered in the prior art and provide an improved testing apparatus that can evaluate the performance of the magnetic components on a plurality of generated voltage waveforms and enhances the versatility and accuracy of measurements to thoroughly understand the characteristics of power magnetics.
One or more objectives of the present disclosure is achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the present disclosure are further defined in the dependent claims.
In one aspect, the present disclosure provides a testing apparatus for power magnetics. The testing apparatus includes a magnetics excitation circuit that includes at least two H-bridge circuits connected in series. Each of the two H-bridge circuits includes a plurality of switches and a Direct Current (DC) voltage source. The magnetics excitation circuit is configured to generate a plurality of voltage waveforms based on a plurality of switching patterns of the two H-bridge circuits and a plurality of voltage levels. The plurality of voltage levels is provided by a combination of the DC voltage source of each H-bridge circuit and by an independent or a concurrent operation of the two H-bridge circuits. The magnetics excitation circuit is further configured to apply each of the plurality of generated voltage waveforms across two ends of a test magnetic component. Performance and core losses of the test magnetic component is estimated based on the application of each of the plurality of generated voltage waveforms across the two ends of a test magnetic component.
In a first example, the testing apparatus can generate a wide range of voltage waveforms, including different voltage levels and polarity, by manipulating the switching patterns of the H-bridge circuits and the voltage level of the DC voltage sources. This flexibility allows for comprehensive testing of power magnetics under various operating conditions, providing a more accurate assessment of their performance.
In a second example, the testing apparatus can estimate core losses of the test magnetic component based on the measured performance parameters. This capability is crucial for designing and optimizing power magnetics, ensuring their efficiency and reliability in real-world applications. Further, in addition to core losses, the testing apparatus can estimate copper losses and other magnetic parameters of the test magnetic component. This comprehensive characterization enables engineers to fine-tune the design and performance of power magnetics.
In a third example, the testing apparatus includes a processor that can adapt the testing parameters based on input data, allowing for customized testing tailored to specific requirements. This adaptability ensures that the testing is relevant to the intended application of the power magnetics. Moreover, the testing apparatus includes an environmental control chamber that can simulate real-world operating conditions by adjusting at least one of a temperature, pressure, and humidity levels. This feature enables engineers to evaluate how power magnetics perform in different environmental scenarios.
In another aspect, the present disclosure provides a method for using a testing apparatus for power magnetics. The method includes generating, by a magnetics excitation circuit, a plurality of voltage waveforms based on a plurality of switching patterns and a plurality of voltage levels. The plurality of voltage levels is provided by a combination of a DC voltage source of each H-bridge circuit of the magnetics excitation circuit and by an independent or concurrent operation of two H-bridge circuits of the magnetics excitation circuit. The method further includes applying, by the magnetics excitation circuit, each of the plurality of generated voltage waveforms across two ends of a test magnetic component. Performance and core losses of the test magnetic component is estimated based on the application of each of the plurality of generated voltage waveforms on the test magnetic component.
The method achieves all the advantages and technical effects of the testing apparatus of the present disclosure.
It is to be appreciated that all the aforementioned implementation forms can be combined. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. It will be appreciated that features of the present disclosure are susceptible to being combined in various combinations without departing from the scope of the present disclosure as defined by the appended claims.
Additional aspects, advantages, features, and objects of the present disclosure would be made apparent from the drawings and the detailed description of the illustrative implementations construed in conjunction with the appended claims that follow.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic block diagram of a testing apparatus for power magnetics, in accordance with an embodiment of the present disclosure;
FIG. 2 is an exemplary circuit diagram of a magnetics excitation circuit of the testing apparatus for power magnetics, in accordance with an embodiment of the present disclosure;
FIG. 3 is an exemplary circuit diagram of another magnetics excitation circuit of the testing apparatus for power magnetics, in accordance with another embodiment of the present disclosure;
FIG. 4 is an exemplary circuit diagram of yet another magnetics excitation circuit of the testing apparatus for power magnetics, in accordance with yet another embodiment of the present disclosure;
FIG. 5 is an exemplary graphical representation depicting a quasi-square wave type voltage excitation across the test magnetic component, in accordance with an embodiment of the present disclosure;
FIG. 6 is yet another exemplary graphical representation depicting a rectangular wave type voltage excitation across the test magnetic component, in accordance with an embodiment of the present disclosure;
FIG. 7 is yet another exemplary graphical representation depicting a multi-level voltage excitation across the test magnetic component, in accordance with an embodiment of the present disclosure;
FIG. 8 is yet another exemplary graphical representation depicting another multi-level voltage excitation across the test magnetic component, in accordance with an embodiment of the present disclosure; and
FIG. 9 is a flowchart depicting a method of using the testing apparatus for power magnetics, in accordance with an embodiment of the present disclosure.
The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the present disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those skilled in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers.
Embodiments of the present disclosure will now be described, by way of example only, with reference to the following diagrams wherein:
In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the non-underlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing.
DETAILED DESCRIPTION OF EMBODIMENTS
The following detailed description illustrates embodiments of the present disclosure and ways in which they can be implemented. Although some modes of carrying out the present disclosure have been disclosed, those skilled in the art would recognize that other embodiments for carrying out or practicing the present disclosure are also possible.
FIG. 1 is a schematic block diagram of a testing apparatus for power magnetics, in accordance with an embodiment of the present disclosure. With reference to FIG. 1, there is shown a block diagram of a testing apparatus 100. In some implementations, the testing apparatus 100 is used for testing a test magnetic component 102 in multiple electrical scenarios. The testing apparatus 100 includes a magnetics excitation circuit 104 connected to a primary end of the test magnetic component 102. In some implementations, the test magnetic component 102 is placed in an environment control chamber 106, as shown in FIG. 1. Both ends i.e., the primary and secondary ends of the test magnetic component 102 are connected to a measurement instrumentation 108. The measurement instrumentation 108 is further connected to a data acquisition system 110. The testing apparatus 100 further includes a processor 112 communicatively or electrically connected to the magnetics excitation circuit 104 and a host computing device 114. The host computing device 114 is further connected to the data acquisition system 110, via a communication channel 122. The processor 112 is further connected to a current sensor 116 that is further connected to the measurement instrumentation 108. In some examples, the current sensor 116 is configured to sense the current at the primary end of the test magnetic component 102. The processor 112 is further connected to a pair of voltage sensors i.e., a first voltage sensor 118 and a second voltage sensor 120. The first voltage sensor 118 is connected across the primary ends of the test magnetic component 102 and the measurement instrumentation 108. Further, the second voltage sensor 120 is connected across the secondary ends of the test magnetic component 102 and the measurement instrumentation 108.
The present disclosure provides the testing apparatus 100 for power magnetics, where the testing apparatus 100 generates versatile voltage waveforms, applies the generated voltage waveforms to the test magnetic component 102 while measuring its performance under controlled conditions, and estimates core and copper losses. The testing apparatus 100 adapts testing parameters and simulates real-world environments for comprehensive power magnetics evaluation. Voltage waveforms refer to the patterns or shapes of the electrical voltage signals generated by the testing apparatus, which are applied to the test magnetic component for evaluation. These waveforms can vary in terms of amplitude, frequency, and shape, allowing for a wide range of testing scenarios and conditions. Core and copper losses refer to power losses that occur in electrical components, particularly in power magnetics like transformers and inductors. In some examples, the core losses may occur in the magnetic core material due to hysteresis and eddy current effects when it is subjected to time-varying magnetic fields. In some examples, the core losses may occur due to other effects such as magnetic relaxation, presence of DC bias in the flux, etc. The core losses are typically associated with the magnetic properties of the material and can impact the overall efficiency and performance of the test magnetic component 102. The copper losses occur in the windings of the test magnetic component 102 due to the resistance of the wire. The copper losses may result in the temperature rise and lower the efficiency of the test magnetic component 102. Estimation of the core and copper losses using the testing apparatus 100 is essential for designing and optimizing power magnetics for various applications, ensuring they meet efficiency, performance, and reliability requirements.
The test magnetic component 102 refers to a specific magnetic component that is being evaluated or tested. Examples of the test magnetic component 102 may include various types of power magnetics, such as inductors, transformers, coupled inductors, or any other magnetic component used in electrical systems. The purpose of the testing apparatus 100 is to subject the test magnetic component 102 to various voltage waveforms and environmental conditions that are similar to the real-world electrical scenarios, measure its performance parameters (such as voltage, current, and temperature), and estimate core and copper losses to assess how well it functions under different real-world operating conditions.
The magnetics excitation circuit 104 refers to a specific circuitry responsible for generating and applying the voltage waveforms to the test magnetic component 102. The magnetics excitation circuit 104 is a crucial component of the testing apparatus 100 as it allows for the controlled excitation of the test magnetic component 102 with various voltage waveforms, facilitating the evaluation of its performance and estimation of core and copper losses under different electrical scenarios. The magnetics excitation circuit 104 includes at least two H-bridge circuits 104A, 104B connected in series. Each of the at least two H-bridge circuits 104A, 104B includes a plurality of switches and a Direct Current (DC) voltage source. The at least two H-bridge circuits 104A, 104B include a first H-bridge circuit 104A and a second H-bridge circuit 104B. The first H-bridge circuit 104A includes a first plurality of switches S1 and a first DC voltage source 124. The second H-bridge circuit 104B includes a second plurality of switches S2 and a second DC voltage source 126. In some implementations, each of the at least two H-bridge circuits 104A, 104B is made of same type of semiconductor devices. However, in some other implementations, each of the at least two H-bridge circuits 104A, 104B is made of different type of semiconductor devices.
Alternatively, the testing apparatus 100 further includes the environment control chamber 106. The environment control chamber 106 is configured to accommodate the test magnetic component 102 and control one or more environmental conditions including temperature, pressure, and humidity levels within the enclosed structure to simulate real-world operating environments. In some instances, the environment control chamber 106 may be a temperature control chamber.
The measurement instrumentation 108 refers to a device that measure a set of performance parameters of the test magnetic component upon the application of each of the plurality of generated voltage waveforms. In some implementations, the set of performance parameters may include, but not limited to a voltage across the two ends of the test magnetic component 102, a current through one of the two ends of the test magnetic component 102, temperature measurements on the test magnetic component 102, and a magnetic hysteresis behaviour. In some implementations, the set of performance parameters includes one or more electrical parameters and one or more thermal parameters associated with the performance of the test magnetic component 102 upon the application of each generated excitation waveform to the test magnetic component 102. The one or more electrical parameters includes a voltage measured across the two ends of the test magnetic component, and a current through one of the two ends of the test magnetic component, and the one or more thermal parameters includes temperature measurements on the test magnetic component 102. In some examples, the measurement instrumentation 108 may be a power analyser or an oscilloscope. In some other examples, the measurement instrumentation 108 includes the current sensor 116, the first voltage sensor 118, the second voltage sensor 120; an oscilloscope or the power analyser. In some other cases, the measurement instrumentation 108 may include voltage and current probes.
The data acquisition system 110 refers to a device used to record and store data over time. The data acquisition system 110 is used to continuously capture and store measurements of various performance parameters associated with the test magnetic component 102 as it undergoes testing under different voltage waveforms and controlled environmental conditions. This data is valuable for analysis, evaluation, and further understanding of the magnetic component's behaviour and performance characteristics.
The processor 112 refers to a computational element that is operable to determine switching patterns and voltage levels, and potentially controlling the switching of switches of the magnetic excitation circuit 104. The processor 112 may refer to one or more individual processors, processing devices, and various elements associated with a processing device that may be shared by other processing devices. In some implementations, the processor 112 may be an independent unit and may be located outside a server. Examples of the processor 112 may include but are not limited to, a hardware processor, a digital signal processor (DSP), a microprocessor, a microcontroller, a state machine, a data processing unit, a graphics processing unit (GPU), and other processors or control circuitry.
The host computing device 114 refers to any electronic device or machine that may perform computational tasks and process data stored in the data acquisition system 110. The host computing device 114 includes a wide range of devices, from traditional personal computers and servers to smartphones, tablets, and embedded systems.
The current sensor 116 refers to a component or device within the testing apparatus 100 that is responsible for measuring electric current. The current sensor 116 is used to measure the current flowing through a circuit or the test magnetic component 102 to obtain data on its electrical performance. The current sensor 116 is useful in collecting data that is used to assess the performance and characteristics of the test magnetic component 102 during testing.
The first voltage sensor 118 and the second voltage sensor 120 refer to a device or component that is used to measure or detect the voltage level of an electrical circuit. The first voltage sensor 118 and the second voltage sensor 120 may provide information about the electrical potential difference across the primary ends and the secondary ends of the test magnetic component 102.
The communication channel 122 includes a means of transmitting or receiving data, information, or signals between different components of the system or between the system and external devices. The communication channel 122 may be physical, such as electrical wires or optical fibers, or it may be wireless, like radio waves or electromagnetic signals. Examples of the communication channel 122 may include, but are not limited to, wired communication channels, such as Ethernet and USB, wireless communication channels, including Wi-Fi and Bluetooth, cellular networks, like 4G and 5G, satellite communication, infrared data transmission, Near Field Communication (NFC), power line communication, underwater acoustic communication, free space optical communication, and Internet.
In operation, the magnetics excitation circuit 104 is configured to generate a plurality of voltage waveforms based on a plurality of switching patterns of the at least two H-bridge circuits 104A and 104B and a plurality of voltage levels. The voltage level may be defined as the preset voltage levels to be applied to the test magnetic component 102 during testing, which can vary based on the intended use or operating conditions of the test magnetic component 102. The plurality of voltage levels is provided by a combination of the DC voltage source 124 and 126 of each H-bridge circuit and by an independent or concurrent operation of the at least two H-bridge circuits 104A and 104B. A voltage level V1 is provided by the first DC voltage source 124 and a voltage level V2 is provided by the second DC voltage source 126. In some examples, by controlling the switching patterns of each of the at least two H-bridge circuits 104A and 104B and utilizing their DC voltage sources 124 and 126, various voltage waveforms with different magnitudes and polarities for testing the test magnetic component 102 may be generated.
The magnetics excitation circuit 104 is further configured to apply each of the plurality of generated voltage waveforms across two ends of the test magnetic component 102. The measurement instrumentation 108 is further configured to measure a set of performance parameters associated with the test magnetic component 102 upon the application of each of the plurality of generated voltage waveforms to the test magnetic component 102 under controlled environmental conditions. In an example, the measurement instrumentation 108 measures the potential difference across the primary ends and secondary ends of the test magnetic component 102 when each voltage waveform is applied. Further, the measurement instrumentation 108 measures the current flowing through the test magnetic component 102 during excitation. By measuring the voltages across the primary and secondary ends and the current flowing through the test magnetic component 102 during excitation, the measurement instrumentation 108 evaluates the magnetic characteristics such as hysteresis behaviour.
The processor 112 is further configured to estimate core losses of the test magnetic component 102 based on the measured set of performance parameters upon application of each of the plurality of generated voltage waveforms to the test magnetic component 102 under the controlled environmental conditions. In an example, the measurement instrumentation 108 measures the voltage waveform across the primary and secondary ends of the test magnetic component for each excitation waveform applied. Simultaneously, the measurement instrumentation 108 measures the current flowing through the test magnetic component 102. By multiplying the measured voltages and current values at each time instant, the processor 112 calculates the instantaneous power across the test magnetic component 102. In some implementations, the processor 112 is further configured to estimate copper losses and other magnetic parameters of the test magnetic component based on the measured set of performance parameters upon application of each of the plurality of generated voltage waveforms to the test magnetic component 102 under the controlled environmental conditions.
In some implementations, the processor 112 is further configured to receive an input dataset related to the test magnetic component 102 under test. The processor 112 is further configured to select a set of testing parameters based on the received input data. The processor 112 is further configured to determine the plurality of switching patterns and the plurality of voltage levels. The processor 112 is further configured to control a manipulation of the plurality of switching patterns within each H-bridge circuit to vary the plurality of voltage levels based on the set of testing parameters. In some implementations, the set of testing parameters includes a voltage level to be applied to the test magnetic component 102, one or more frequencies of operation of the plurality of switches, a duty cycle, a level of direct current (DC) bias, a type of excitation waveform, and the controlled environmental conditions under which testing is performed. Each frequency of operation is defined as a frequency at which the switches in the at least two H-bridge circuits 104A, 104B are operated to create the excitation waveforms, which can affect the component's performance. The duty cycle is defined as a proportion of time during each excitation cycle when the voltage is applied, influencing the response of the test magnetic component 102. The DC bias as a test parameter corresponds to a level of direct current bias, if any, applied to the test magnetic component 102, to understand the effect of DC bias on core loss. The type of excitation waveform corresponds to the voltage waveform shape (e.g., sinusoidal, square wave, rectangular wave, quasi square wave, multilevel) used for excitation, affecting how the test magnetic component 102 behaves. The controlled environmental conditions may include parameters like temperature, pressure, and humidity within the environment control chamber, simulating the real-world operating environment of the test magnetic component 102. In some implementations, the control of the manipulation of the plurality of switching patterns within each H-bridge circuit to vary the plurality of voltage levels is performed by dynamically adjusting an opened state and a closed state as well as the frequency of operation of the plurality of switches.
FIG. 2 is a circuit diagram of a magnetics excitation circuit of the testing apparatus for power magnetics, in accordance with an embodiment of the present disclosure. With reference to FIG. 2, there is shown a circuit diagram 200 of the magnetics excitation circuit 104. In the illustrated example of FIG. 2, the magnetics excitation circuit 104 includes the two H-bridge circuits connected in series. The two H-bridge circuits include the first H-bridge circuit 104A and the second H-bridge circuit 104B. As discussed above, the first H-bridge circuit 104A includes the first DC voltage source 124 and the first plurality of switches S1. The first plurality of switches S1 includes a first switch S11, a second switch S21, a third switch S31, and a fourth switch S41. As discussed above, the second H-bridge circuit 104B includes the second DC voltage source 126 and the second plurality of switches S2. The second plurality of switches S2 includes a first switch S12, a second switch S22, a third switch S32, and a fourth switch S42. The magnetics excitation circuit 104 further includes a first mechanical switch MS1 for engaging and disengaging of the first H-bridge circuit 104A, and a second mechanical switch MS2 for engaging and disengaging of the second H-bridge circuit 104B. In the illustrated example of FIG. 2, the magnetics excitation circuit 104 is connected at the primary end of the test magnetic component 102. Further, block 202, is an abstraction for 108, 110, 112, 114 and 122. At block 202, various loss such as core loss, copper loss, and other magnetic properties may be estimated.
In some implementations, an input DC voltage level of the first H-bridge circuit 104A of the two H-bridge circuits is equal to the input DC voltage level of the second H-bridge circuit 104B of the two H-bridge circuits. In some other implementations, the input DC voltage level of the first H-bridge circuit 104A of the two H-bridge circuits is lower than the input DC voltage level of the second H-bridge circuit 104B of the two H-bridge circuits. In some other implementations, the input DC voltage level of the first H-bridge circuit 104A of the two H-bridge circuits is higher than the input DC voltage level of the second H-bridge circuit 104B of the two H-bridge circuits.
In some implementations, when a positive DC voltage level is applied by the plurality of switching pattern , a first switching pattern of the plurality of switching patterns includes the first switch S11 and the fourth switch S41 of the first H-bridge circuit 104A of the two H-bridge circuits to be in a closed state, the second switch S21 and the third switch S31 of the first H-bridge circuit 104A to be in an opened state, and the first mechanical switch MS1 of the magnetics excitation circuit 104 to be in the opened state and the second mechanical switch MS2 of the magnetics excitation circuit 104 to be in the closed state to provide a first voltage level of positive polarity (i.e., +V1). In such cases, the second H-bridge circuit 104B is disengaged using the second mechanical switch MS2. Alternatively, in some implementations, when a positive DC voltage level is applied by the plurality of switching pattern, the first switching pattern of the plurality of switching patterns includes the first switch S12 and the fourth switch S42 of the second H-bridge circuit 104B of the two H-bridge circuits to be in the closed state, the second switch S22 and the third switch S32 of the second H-bridge circuit 104B to be in the opened state, and the first mechanical switch MS1 to be in the closed state and the second mechanical switch MS2 to be in the opened state to provide a second voltage level of positive polarity (i.e., +V2). In such cases, the first H-bridge circuit 104A is disengaged using the first mechanical switch MS1.
In some implementations, a second switching pattern of the plurality of switching patterns includes the first switch S11, S12 and the fourth switch S41, S42 of the first H-bridge circuit 104A and the second H-bridge circuit 104B to be in the closed state, and the second switch S21, S22 and the third switch S31, S32 of the first H-bridge circuit 104A and the second H-bridge circuit 104B to be in the opened state and the first mechanical switch MS1 and the second mechanical switch MS2 to be in the opened state to provide a sum of the first voltage level and the second voltage level (i.e., V1+V2).
In some implementations, a third switching pattern of the plurality of switching patterns comprises the first switch S11 and the fourth switch S41 of the first H-bridge circuit 104A to be in the opened state, the second switch S21 and the third switch S31 of the first H-bridge circuit 104A to be in the closed state, the second switch S22 and the third switch S32 of the second H-bridge circuit 104B to be in the opened state, and the first switch S12 and the fourth switch S42 of the second H-bridge circuit 104B to be in the closed state and the first mechanical switch MS1 and the second mechanical switch MS2 to be in the opened state to provide a voltage difference of the first voltage level from the second voltage level (i.e., V2-V1).
In some implementations, when a negative DC voltage level is applied by the plurality of switching pattern, a fourth switching pattern of the plurality of switching patterns includes the second switch S21 and the third switch S31 of the first H-bridge circuit 104A to be in the closed state and the first switch S11 and the fourth switch S41 of the first H-bridge circuit 104A to be in the opened state and the first mechanical switch MS1 to be in the opened state and the second mechanical switch MS2 to be in the closed state to provide the first voltage level of negative polarity (i.e., -V1). In such cases, the second H-bridge circuit 104B is disengaged using the second mechanical switch MS2. Alternatively, in some implementations, when the negative DC voltage level is applied by the plurality of switching patterns, the fourth switching pattern of the plurality of switching patterns further includes the second switch S22 and the third switch S32 of the second H-bridge circuit 104B to be in the closed state and the first switch S12 and the fourth switch S42 of the second H-bridge circuit 104B be in the opened state and the second mechanical switch MS2 to be in the opened state and the first mechanical switch MS1 to be in the closed state to provide the second voltage level of negative polarity (i.e., -V2). In such cases, the first H-bridge circuit 104A is disengaged using the first mechanical switch MS1.
In some implementations, a fifth switching pattern of the plurality of switching patterns includes the second switch S21, S22 and the third switch S31, S32 of the first H-bridge circuit 104A and the second H-bridge circuit 104B to be in the closed state and the first switch S11, S12 and the fourth switch S41, S42 of the first H-bridge circuit 104A and the second H-bridge circuit 104B to be in the opened state and the first mechanical switch MS1 and the second mechanical switch MS2 to be in the opened state to provide a negative of sum of the first voltage level and the second voltage level (i.e., -(V1+V2)).
In some implementations, a sixth switching pattern of the plurality of switching patterns comprises the second switch S21 and the third switch S31 of the first H-bridge circuit 104A to be in the opened state, the first switch S11 and the fourth switch S41 of the first H-bridge circuit 104A to be in the closed state, the first switch S12 and the fourth switch S42 of the second H-bridge circuit 104B to be in the opened state, the second switch S22 and the third switch S32 of the second H-bridge circuit 104B to be in the closed state, and the first mechanical switch MS1 and the second mechanical switch MS2 to be in the opened state to provide a voltage difference of the second voltage level from the first voltage level (i.e., V1-V2).
In some implementations, a seventh switching pattern of the plurality of switching patterns includes the first switch S11 and the second switch S21 of the first H-bridge circuit 104A or the first switch S12 and the second switch S22 of the second H-bridge circuit 104B to be in the closed state, or the third switch S31 and the fourth switch S41 of the first H-bridge circuit 104A or the third switch S32 and the fourth switch S42 of the second H-bridge circuit 104B to be in the closed state and the first mechanical switch MS1 and the second mechanical switch MS2 to be in the opened state to provide a zero voltage level (i.e., V=0).
In some implementations, a predetermined DC bias is established by application of the plurality of voltage levels of the positive polarity or the negative polarity. In some implementations, an eighth switching pattern of the plurality of switching patterns includes the first switch S11, S12 and the fourth switch S41, S42 of the first H-bridge circuit 104A or the second H-bridge circuit 104B to be in the closed state and the second switch S21, S22 and the third switch S31, S32 of the first H-bridge circuit 104A or the second H-bridge circuit 104B to be in the opened state for a first predetermined duration as per the predetermined DC bias to establish a positive DC bias. Alternatively, in some implementations, the eighth switching pattern of the plurality of switching patterns further includes the second switch S21, S22 and the third switch S31, S32 of the first H-bridge circuit 104A or the second H-bridge circuit 104B to be in the closed state and the first switch S11, S12 and the fourth switch S41, S42 of the first H-bridge circuit 104A or the second H-bridge circuit 104B to be in the opened state for a second predetermined duration as per the predetermined DC bias to establish a negative DC bias. In some implementations, subsequent to the establishment of the predetermined DC bias, the plurality of switching patterns is configured as per the application of the plurality of voltage levels of the positive polarity or the negative polarity.
The mechanical switches MS1 and MS2 are used to engage or disengage the first H-bridge circuit 104A and the second H-bridge circuit 104B before applying a plurality of switching patterns to generate a defined excitation waveform. The mechanical switches MS1 and MS2 are not switched while the plurality of the switching patterns is being applied to the test magnetic component.
FIG. 3 is an exemplary circuit diagram of another magnetics excitation circuit of the testing apparatus for power magnetics, in accordance with another embodiment of the present disclosure. The exemplary circuit diagram showcases an extended version of the proposed magnetics excitation circuit with N-number of H-bridges in series. With reference to FIG. 3, there is shown a circuit diagram 300 of the magnetics excitation circuit 104.. In the illustrated example of FIG. 3, the magnetics excitation circuit 104 includes a plurality of H-bridge circuits connected in series. The plurality of H-bridge circuits includes a first H-bridge circuit 302A, a second H-bridge circuit 302B, a third H-bridge circuit 302C, and so on up to a Nth H-bridge circuit 302N. Each of the plurality of H-bridge circuits, i.e., the first H-bridge circuit 302A, the second H-bridge circuit 302B, the third H-bridge circuit 302C, and so on up to the Nth H-bridge circuit 302N are substantially similar to the first H-bridge circuit 104A, in terms of functionality and architecture. Specifically, the first H-bridge circuit 302A includes a first plurality of switches including a first switch S11, a second switch S21, a third switch S31, and a fourth switch S41. Similarly, the second H-bridge circuit 302B includes a second plurality of switches including a first switch S12, a second switch S22, a third switch S32, and a fourth switch S42. Further, the third H-bridge circuit 302C includes a third plurality of switches including a first switch S13, a second switch S23, a third switch S33, and a fourth switch S43. Moreover, the Nth H-bridge circuit 302N includes a Nth plurality of switches including a first switch S1n, a second switch S2n, a third switch S3n, and a fourth switch S4n.
FIG. 4 is an exemplary circuit diagram of yet another magnetics excitation circuit of the testing apparatus for power magnetics, in accordance with yet another embodiment of the present disclosure. The exemplary circuit diagram showcases the capability of testing the test magnetic component using different types of semiconductor devices. With reference to FIG. 4, there is shown a circuit diagram 400 of the magnetics excitation circuit 104. The magnetics excitation circuit 104 includes a plurality of H-bridge circuits connected in series. The magnetics excitation circuit 104 includes the two H-bridge circuits connected in series. The two H-bridge circuits include the first H-bridge circuit 402A and the second H-bridge circuit 402B. As discussed above, the first H-bridge circuit 402A includes the first plurality of switches. The first plurality of switches includes the first switch S11, the second switch S21, the third switch S31, and the fourth switch S41. In the illustrated example of FIG. 4, each of the first switch S11, the second switch S21, the third switch S31, and the fourth switch S41 is a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) based H-bridge circuit. The second H-bridge circuit 402B includes the second plurality of switches including the first switch S12, the second switch S22, the third switch S32, and the fourth switch S42. In the illustrated example of FIG. 4, the first switch S12, the second switch S22, the third switch S32, and the fourth switch S42 is a gallium nitride (GaN) high electron mobility transistor (HEMT) based H-bridge circuit.
FIG. 5 is an exemplary graphical representation depicting a quasi-square wave voltage across a test magnetic component, in accordance with an embodiment of the present disclosure. FIG. 5 is explained in conjunction with the elements of FIG. 1 and 2. With reference to FIG. 5, there is shown a graph 500 that depicts voltage waveforms across the primary terminals and the secondary terminals of the test magnetic component 102, voltage waveform across a set of control terminals of the semiconductor device (across gate and source terminals for a SiC MOSFET or GaN HEMT), and current waveform through the primary winding of the test magnetic component 102.Voltage and current scales for ordinate axes are indicated in the graph 500. Time is expressed in microseconds (µs) ranging from 0 µs to 160 µs in an abscissa axis.
The graph 500 includes a first waveform 502 depicting a voltage difference between the gate and the source terminals or a gate-source voltage (v_gs) of the semiconductor device (similar to the first switch S11 of the first H-bridge circuit 104A (from FIG. 2)) of the magnetic excitation circuit 104. The gate-source voltage (v_gs) is switching between a low voltage level and a high voltage level. This is causing the semiconductor device to turn on and turn off. When the gate-source voltage (v_gs) is high, the semiconductor device is turned on and current flows through it. When the gate-source voltage (v_gs) is low, the semiconductor device is turned off and no current flows through it. A duty cycle of the first waveform 502 is defined as a ratio of an on-time period 504 compared to a total time 506 of a single cycle. The term “on time" refers to the duration or percentage of time during which a signal or a switch is in the active or "on" state (usually "on" or high) within a given cycle. In this example, the duty cycle is 0.5.
The graph 500 further includes a second waveform 510 depicting the voltage excitation (v_p) across the primary terminal of the test magnetic component 102. The second waveform 510 is a quasi-square voltage waveform corresponding to the switching events of the semiconductor devices of the magnetic excitation circuit 104. The graph 500 further includes a third waveform 508 depicting an induced voltage (v_s) across the secondary terminals of the test magnetic component 102. The third waveform 508 is a quasi-square waveform with different peak values compared to the voltage (v_p) due to non-unity turns ratio of the test magnetic component 102.
The graph 500 further includes a fourth waveform 512 depicting a current (i_p) through the primary winding of the test magnetic component 102. The fourth waveform 512 has a trapezoidal shape that correlates with the variations in the excitation voltage across the primary terminal (v_p), suggesting a relationship between the primary current and the excitation voltage.
FIG. 6 is another exemplary graphical representation depicting a rectangular voltage excitation across the test magnetic component, in accordance with an embodiment of the present disclosure. FIG. 6 is explained in conjunction with the elements of FIG. 1 and 2. With reference to FIG. 6, there is shown a graph 600 that depicts voltage waveforms across the primary terminals and the secondary terminals of the test magnetic component 102, voltage waveform across a set of control terminals of the semiconductor device (across gate and source terminals for a SiC MOSFET or GaN HEMT), and current waveform through the primary winding of the test magnetic component 102. Voltage and current scales for ordinate axes are indicated in the graph 600. Time is expressed in microseconds (µs) ranging from 0 µs to 160 µs in an abscissa axis.
The graphical representation 600 includes a first waveform 602 depicting a voltage difference between the gate and the source terminals or a gate-source voltage (v_gs) of the semiconductor device (similar to the first switch S11 of the first H-bridge circuit 104A (from FIG. 2)) of the magnetic excitation circuit 104. The gate-source voltage (v_gs) is switching between a low voltage level and a high voltage level. This is causing the semiconductor device to turn on and turn off. When the gate-source voltage (v_gs) is high, the semiconductor device is turned on and current flows through it. When the gate-source voltage (v_gs) is low, the semiconductor device is turned off and no current flows through it. A duty cycle of the first waveform 602 is defined as a ratio of an on-time period 604 compared to a total time 606 of a single cycle. In this example, the duty cycle is 0.3.
The graph 600 further includes a second waveform 610 depicting the voltage (v_p) across the primary terminal of the test magnetic component 102. The second waveform 610 is a rectangular voltage waveform corresponding to the switching events of the semiconductor devices of the magnetic excitation circuit 104. The graph 600 further includes a third waveform 608 depicting an induced voltage (v_s) across the secondary terminals of the test magnetic component 102. The third waveform 608 is also a rectangular waveform with different peak values compared to the voltage (v_p) due to non-unity turns ratio of the test magnetic component 102.
The graph 600 further includes a fourth waveform 612 depicting a current (i_p) flowing across the primary terminal of the test magnetic component 102. The fourth waveform 612 has a triangular shape that correlates with the variations in the excitation voltage across the primary terminal (v_p), suggesting a relationship between the primary current and the excitation voltage.
FIG. 7 is yet another exemplary graphical representation depicting a multi-level voltage excitation across the test magnetic component, in accordance with an embodiment of the present disclosure. FIG. 7 is explained in conjunction with the elements of FIG. 1 and 2. With reference to FIG. 7, there is shown a graph 700 that depicts voltage waveforms across the primary terminals and the secondary terminals of the test magnetic component 102, voltage waveform across a set of control terminals of two semiconductor devices (across gate and source terminals for a SiC MOSFET or GaN HEMT), and current waveform through the primary winding of the test magnetic component 102. Voltage and current scales for ordinate axes are indicated in the graph 700. Time is expressed in microseconds (µs) ranging from 0 µs to 200 µs in an abscissa axis.
The graph 700 includes a first waveform 702 and a second waveform 704, each depicting a voltage difference between the gate and the source terminals or a gate-source voltage (?v1?_gs, ?v2?_gs) across the first semiconductor device (similar to the first switch S11 of the first H-bridge circuit 104A (from FIG. 2)) and across the second semiconductor device (similar to the first switch S12 of the second H-bridge circuit 104B that is shown in FIG. 2) of the magnetic excitation circuit 104, respectively. When the gate-source voltage (?v1?_gs ?or v2?_gs) is high, the corresponding semiconductor device is turned on and current flows through it. When the gate-source voltage (?v1?_gs ?or v2?_gs) is low, the corresponding semiconductor device is turned off and no current flows through it. Further, the second waveform 704 has a phase shift 706 of 30 degrees with respect to the first waveform 702.
The graph 700 further includes a third waveform 710 depicting the voltage (v_p) across the primary terminal of the test magnetic component 102. The third waveform 710 is a multi-level voltage waveform with multiple positive and negative voltage levels corresponding to the switching events of the semiconductor devices of the magnetic excitation circuit 104. The graph 700 further includes a fourth waveform 708 depicting an induced voltage (v_s) across the secondary terminals of the test magnetic component 102. The fourth waveform 708 is also a multi-level waveform with different peak values compared to the voltage (v_p) due to non-unity turns ratio of the test magnetic component 102.
The graph 700 further includes a fifth waveform 712 depicting a current flowing (i_p) through the primary winding of the test magnetic component 102. The fifth waveform 712 has a shape that correlates with the variations in the excitation voltage across the primary terminal (v_p), suggesting a relationship between the primary current and the excitation voltage.
FIG. 8 is yet another exemplary graphical representation depicting another multi-level voltage excitation across the test magnetic component, in accordance with an embodiment of the present disclosure. FIG. 8 is explained in conjunction with the elements of FIG. 1 and 2. With reference to FIG. 8, there is shown a graph 800 that depicts voltage waveforms across the primary terminals and the secondary terminals of the test magnetic component 102, voltage waveform across a set of control terminals of two semiconductor devices (across gate and source terminals for a SiC MOSFET or GaN HEMT), and current waveform through the primary winding of the test magnetic component 102. Voltage and current scales for ordinate axes are indicated in the graph 800. Time is expressed in microseconds (µs) ranging from 0 µs to 200 µs in an abscissa axis.
The graph 800 includes a first waveform 802 and a second waveform 804, each depicting a voltage difference between the gate and the source terminals or the gate-source voltage (?v2?_gs, ?v3?_gs) across the second semiconductor device (similar to the first switch S12 of the second H-bridge circuit 104B (from FIG. 2)) and across a third semiconductor device (similar to the second switch S21 of the first H-bridge circuit 104A that is shown in FIG. 2 ) of the magnetic excitation circuit 104, respectively. When the gate-source voltage (?v2?_gs ?or v3?_gs) is high, the corresponding semiconductor device is turned on and current flows through it. When the gate-source voltage (?v2?_gs ?or v3?_gs) is low, the corresponding semiconductor device is turned off and no current flows through it. The frequency of the first waveform 802 is lower than the frequency of the second waveform 804, an example of multi-frequency operation of the semiconductor devices to produce multi-level voltage excitation across the primary terminals of the test magnetic component 108.
The graph 800 further includes a third waveform 810 depicting the voltage (v_p) across the primary terminal of the test magnetic component 102. The third waveform 810 is a multi-level voltage waveform with multiple positive and negative voltage levels corresponding to the switching events of the semiconductor devices of the magnetic excitation circuit 104. The graph 800 further includes a fourth waveform 808 depicting an induced voltage (v_s) across the secondary terminals of the test magnetic component 102. The fourth waveform 808 is also a multi-level waveform with different peak values compared to the voltage (v_p) due to non-unity turns ratio of the test magnetic component 102.
The graph 800 further includes a fifth waveform 812 depicting a current flowing (i_p) across the primary terminal of the test magnetic component 102. The fifth waveform 812 has a shape that correlates with the variations in the excitation voltage across the primary terminal (v_p), suggesting a relationship between the primary current and the excitation voltage.
FIG. 9 is a flowchart depicting a method of using the testing apparatus for power magnetics, in accordance with an embodiment of the present disclosure. FIG. 9 is described in conjunction with elements from FIGs. 1 and 2. With reference to FIG. 9, there is shown a flowchart of a method 900 for using the testing apparatus 100 (shown in FIG. 1) for power magnetics. The method 900 may include steps 902 to 908.
At step 902, the method 900 includes generating, by the magnetics excitation circuit 104, the plurality of voltage waveforms based on the plurality of switching patterns and the plurality of voltage levels. The plurality of voltage levels is provided by a combination of a DC voltage source of each H-bridge circuit of the magnetics excitation circuit 104 and by an independent or concurrent operation of two H-bridge circuits of the magnetics excitation circuit 104. By generating the plurality of voltage waveforms based on the plurality of switching pattern, the method 900 allows to deliver precise, adaptable, and voltage waveforms, enabling comprehensive testing and evaluation of the test magnetic component 102 across various real world operating conditions.
At step 904, the method 900 further includes applying, by the magnetics excitation circuit 104, each of the plurality of generated voltage waveforms across two ends of the test magnetic component 102. By subjecting the test magnetic component 102 to a variety of voltage waveforms, the method 900 enables the comprehensive evaluation of performance, and realistic simulation of operational conditions. Performance and core losses of the test magnetic component 102 is estimated based on the application of each of the plurality of generated voltage waveforms on the test magnetic component 102. Specifically, the performance and core losses of the test magnetic component 102 is estimated based on the application of each of the plurality of generated voltage waveforms across the two ends of the test magnetic component 102 or through any of the windings of the test magnetic component 102.
At step 906, the method 900 further includes measuring, by the measurement instrumentation 108, the set of performance parameters associated with the test magnetic component 102 upon the application of each of the plurality of generated voltage waveforms to test the test magnetic component 102 under controlled environmental conditions. This step allows for measurement of various performance parameters, including electrical and thermal characteristics, under controlled environmental conditions. The data collected provides invaluable insights into how the test magnetic component 102 behaves across different voltage waveforms and environmental scenarios, aiding in the optimization of its design and performance.
At step 908, the method 900 further includes estimating, by the processor 112, the core losses of the test magnetic component 102 based on the measured set of performance parameters from the test magnetic component 102 upon application of each of the plurality of generated voltage waveforms to the test magnetic component 102 under the controlled environmental conditions. In some examples, the method 900 includes estimating, by the processor 112, the core losses of the test magnetic component 102 based on the measured set of performance parameters across the two ends of the test magnetic component 102 or through any of the windings of the test magnetic component 102. Estimating the core losses based on the measured performance parameters offers a comprehensive understanding of how the test magnetic component 102 responds to different voltage waveforms and environmental conditions. This information is critical for optimizing the design, efficiency, and overall performance of power magnetic components, ensuring they meet defined specifications and standards.
In some implementations, the estimation further includes estimating copper losses and other magnetic parameters of the test magnetic component 102 based on the measured set of performance parameters upon application of each of the plurality of generated voltage waveforms to the test magnetic component 102 under the controlled environmental conditions.
Modifications to embodiments of the present disclosure described in the foregoing are possible without departing from the scope of the present disclosure as defined by the accompanying claims. Expressions such as "including", "comprising", "incorporating", "have", "is" used to describe and claim the present disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural. The word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and/or to exclude the incorporation of features from other embodiments. The word "optionally" is used herein to mean "is provided in some embodiments and not provided in other embodiments". It is appreciated that certain features of the present disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the present disclosure, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as suitable in any other described embodiment of the disclosure. , C , Claims:1. A testing apparatus (100) for power magnetics, comprising:
a magnetics excitation circuit (104) that comprises at least two H-bridge circuits (104A, 104B, 302A, 302B, 302C…302N, 402A, 402B) connected in series, each of the at least two H-bridge circuits (104A, 104B) comprises a plurality of switches (S1, S2) and a Direct Current (DC) voltage source (124, 126), wherein the magnetics excitation circuit (104) is configured to:
generate a plurality of voltage waveforms based on a plurality of switching patterns of the at least two H-bridge circuits (104A, 104B, 302A, 302B, 302C…302N, 402A, 402B) and a plurality of voltage levels, wherein the plurality of voltage levels is provided by a combination of the DC voltage source (124, 126) of each H-bridge circuit and by an independent or concurrent operation of the at least two H-bridge circuits (104A, 104B, 302A, 302B, 302C…302N, 402A, 402B); and
apply each of the plurality of generated voltage waveforms across two ends of a test magnetic component (102),
wherein performance and core losses of the test magnetic component (102) is estimated based on the application of each of the plurality of generated voltage waveforms on the test magnetic component (102).
2. The testing apparatus (100) as claimed in claim 1, wherein the testing apparatus further comprises a measurement instrumentation configured to measure a set of performance parameters associated with the test magnetic component (102) upon the application of each of the plurality of generated voltage waveforms to the test magnetic component (102) under controlled environmental conditions.
3. The testing apparatus (100) as claimed in claim 1, wherein the testing apparatus (100) further comprises a processor (112) communicatively coupled with the magnetics excitation circuit (104), the processor (112) is configured to estimate core losses of the test magnetic component (102) based on the measured set of performance parameters upon application of each of the plurality of generated voltage waveforms to the test magnetic component (102) under the controlled environmental conditions.
4. The testing apparatus (100) as claimed in claim 3, wherein the processor (104) is further configured to estimate copper losses and other magnetic parameters of the test magnetic component (102) based on the measured set of performance parameters upon application of each of the plurality of generated voltage waveforms to the test magnetic component (102) under the controlled environmental conditions.
5. The testing apparatus (100) as claimed in claim 3, wherein the processor (112) is configured to:
receive an input dataset related to the test magnetic component (102) under test;
select a set of testing parameters based on the received input data; and
determine the plurality of switching patterns and the plurality of voltage levels.
6. The testing apparatus (100) as claimed in claim 3, wherein the processor (112) is further configured to control a manipulation of the plurality of switching patterns within each H-bridge circuit to vary the plurality of voltage levels based on the set of testing parameters, wherein the set of testing parameters comprises a voltage level to be applied to the test magnetic component (102), a frequency of operation of the plurality of switches, a duty cycle, a level of direct current (DC) bias, a type of excitation waveform, and the controlled environmental conditions under which testing is performed.
7. The testing apparatus (100) as claimed in claim 4, wherein the control of the manipulation of the plurality of switching patterns within each H-bridge circuit to vary the plurality of voltage levels is performed by dynamically adjusting an opened state and a closed state as well as the frequency of operation of the plurality of switches.
8. The testing apparatus (100) as claimed in claim 1, wherein the set of performance parameters comprises one or more electrical parameters and one or more thermal parameters associated with the performance of the test magnetic component (102) upon the application of each generated excitation waveform to the test magnetic component (102); and
wherein the one or more electrical parameters comprises a voltage measured across the two ends of the test magnetic component (102), and a current at one of the two ends of the test magnetic component (102), and the one or more thermal parameters comprises temperature measurements on the test magnetic component (102).
9. The testing apparatus (100) as claimed in claim 1, wherein each of the at least two H-bridge circuits (104A, 104B) is made of same type of semiconductor devices.
10. The testing apparatus (100) as claimed in claim 1, wherein each of the at least two H-bridge circuits (104A, 104B) is made of different type of semiconductor devices.
11. The testing apparatus (100) as claimed in claim 1, wherein the testing apparatus (100) further comprises a measurement instrumentation to measure the set of performance parameters of the test magnetic component (102) upon the application of each of the plurality of generated voltage waveforms.
12. The testing apparatus (100) as claimed in claim 1, wherein the testing apparatus (100) further comprises an environment control chamber (106) configured to accommodate the test magnetic component (102) and control one or more environmental conditions, and wherein the one or more environmental conditions comprises temperature, pressure, and humidity levels within the enclosed structure to simulate real-world operating environments.
13. A method (900) for using a testing apparatus (100) for power magnetics, the method (900) comprising:
generating (902), by a magnetics excitation circuit (104), a plurality of voltage waveforms based on a plurality of switching patterns and a plurality of voltage levels, wherein the plurality of voltage levels is provided by a combination of a DC voltage source (124, 126) of each of at least two H-bridge circuits (104A, 104B) of the magnetics excitation circuit (104) and by an independent or concurrent operation of the at least two H-bridge circuits (104A, 104B) of the magnetics excitation circuit (104); and
applying (904), by the magnetics excitation circuit (104), each of the plurality of generated voltage waveforms across two ends of a test magnetic component (102),
wherein performance and core losses of the test magnetic component (102) is estimated based on the application of each of the plurality of generated voltage waveforms on the test magnetic component (102).
14. The method (900) of claim 13, further comprising measuring (906), by a measurement instrumentation (108), a set of performance parameters associated with the test magnetic component (102) upon the application of each of the plurality of generated voltage waveforms to test the test magnetic component (102) under controlled environmental conditions.
15. The method (900) of claim 13, further comprising estimating (908), by a processor (112), core losses of the test magnetic component (102) based on the measured set of performance parameters from the test magnetic component (102) upon application of each of the plurality of generated voltage waveforms to the test magnetic component (102) under the controlled environmental conditions, wherein the estimation further comprises estimating copper losses and other magnetic parameters of the test magnetic component (102) based on the measured set of performance parameters upon application of each of the plurality of generated voltage waveforms to the test magnetic component (102) under the controlled environmental conditions.
16. The method (900) as claimed in claim 13, wherein a set of conditions applied to the input DC voltage levels of the first H-bridge circuit (104A) and the second H-bridge circuit (104B) of the at least two H-bridge circuits (104A, 104B) comprise any one of: an input DC voltage level of a first H-bridge circuit (104A) of the at least two H-bridge circuits (104A, 104B) is equal to the input DC voltage level of a second H-bridge circuit (104B) of the at least two H-bridge circuits (104A, 104A); the input DC voltage level of the first H-bridge circuit (104A) of the at least two H-bridge circuits (104A, 104B) is lower than the input DC voltage level of the second H-bridge circuit (104B) of the at least two H-bridge circuits (104A, 104A), and the input DC voltage level of the first H-bridge circuit (104A) of the at least two H-bridge circuits (104A, 104B) is higher than the input DC voltage level of the second H-bridge circuit (104B) of the at least two H-bridge circuits (104A, 104B).
17. The method (900) as claimed in claim 13, wherein the plurality of voltage levels are applied by the plurality of switching patterns of the plurality of switches (S1, S2) of the at least two H-bridge circuits (104A, 104B), depending on the voltage levels of the DC voltage sources (124, 126).
18. The method (900) as claimed in claim 13, wherein a predetermined DC bias is established by application of the plurality of voltage levels of the positive polarity or the negative polarity.
19. The method (900) as claimed in claim 13, wherein subsequent to the establishment of the predetermined DC bias, the plurality of switching patterns is configured as per the application of the plurality of voltage levels of the positive polarity or the negative polarity.