Background of the Invention
Field of the invention
This invention relates to managing the data in the system using solid-state storage CAM instead of using Cache or CAM with Cache for non-volatile storage devices.
Description of the Related Art
In general, cache is used by the central processing unit of a computer or system to reduce the average time to access memory. The cache is a smaller, faster memory, which stores copies of the data that is accessed often, or data that is loaded as a part of an application from the most frequently used main memory locations. As long as most memory accesses are to cache memory locations, the average latency of memory accesses will be closer to the cache latency than to the latency of main memory.
Normally two levels of cache memory are used in the system to increase the speed. But these two levels of cache memory have a limitation like it is not used for fast searching application. Cache is just a volatile memory used to speed up the process and instruction fetching.
In every memory system. Cache coherency is the important thing need to be considerd. Normally cache must be 'write-through' cache whenever the processor performs a write to main memory. When the write is performed, the relevant cache entry is updated, and a write to main memory is issued. We can say that cache coherency has been maintained here by the cache reflects the accurately contents of main memory. The problem is, writes to main memory are usually even slower than reads. The solution to this is to minimize the number of writes actually made to main memory by only doing the write once the processor has definitely finished with that location. This is what a write-back cache does - it writes out the location to main memory sometime after the actual write took place. So the need of cache is to fast read from the main memory only. There is no need of write in the cache for minimizing cache coherency.

In the patent 'Apparatus, System and Method for Solid State Storage as Cache for High Capacity Non Volatile Storage' [WO 070173 Al, 2008] explained the concept of using solid-state cache back-end and cache front-end module for one or more HCNV storage devices. But this patent explained only about the usage of solid-state cache in the HCNV storage. As we previously said, this cache is not suitable for fast searching application. Normally people prefer the solid-state devices for their high latency speed (No hard disk seek) only. But using that solid-state storage as a cache makes the system more costly only.
In the Patent 'Fully Associated Texture Cache having Content Addressable Memory and method for use thereof [US 6784892, 2004] explained the cache memory includes first and second memories coupled together and here one is CAM and another one is FIFO. Here the first memory used to store address storage locations and second memory used to data storage locations and each address storage location coupled to a respective data storage locations with a plurality of activation lines. This patent is not describing anything about solid-state storage and fast searching. The patent is using two memories in the same cache; it's not level cache.
In the patent 'Multilevel Content Addressable Memory' [US 0260814 Al, 2007] explained the procedure of using multilevel content addressable memory. This invention explains about the architecture of that Multilevel CAM but not the method of real time using in the system.
Summary of the Invention
This invention is an apparatus and method of using solid state Content Addressable Memory for Non-Volatile storage. A CAM is a memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry using for fast searching. This invention uses CAM in Solid-state disk/drives instead of cache or additionally with that for efficient searching applications.

The idea of the invention is using content addressable memory as a cache or using that content addressable memory with cache in solid-state disks to increase the speed of the system and for fast searching application. This invention describes about the method of using level cache in the solid-state disks instead of single RAM. This level cache consists CAM in one level and Cache in another level or both in the same level. The idea of this invention is to use, one level of cache is for reading the data from the main memory and another level of CAM is used for searching application in the main memory.
When the processor needs to execute an instruction, it searches first in its own data registers. If the needed data isn't there, it goes to the L1 cache and then to the L2 CAM. If the data isn't in any cache, the system has to retrieve it from the Main disk.
The CAM and Cache memory of this invention are implemented from the Solid State memories. It may be a volatile or Non-volatile or Volatile with battery backup depends upon the whole system environment. The cache using here manages both data transfers associated with the processors request and also non-volatile storage devices (Main Memory).
We can use any type of storage here irrespective of solid-state drives in the main memory. The main memory can be a Hard Disk Drive (HDD), Tape drive, Optical and RAID level storages.
Brief Description of Accompanying Drawings
In the drawings,
Figure-1 represents the System arrangements of solid-state disk with Content Addressable Memory as a in between memory.
Figure-2 represents the solid-state disk memory with the memory levels. Here in the diagram cache is showing as a level I memory and CAM is showing as a level II memory.

Figure-3 represents the memory arrangements with the main and intermediate memories. Two intermediate memories are showing in the diagram like level I / Cache and Level II / CAM.
Detailed Description of the Invention with Reference to Accompanying Drawings
The Figure-1 represents the complete solid-state disk arrangement with the intermediate memory CAM 111. The system has an arrangement of Non-Volatile main memory 101 connected with the processor 105 through the Memory Controller 102 and Memory Controller Register 104. A separate Content Addressable Memory 111 is located in the intermediate with in Processor 105 and Main memory 101. This CAM is connected with the Processor through the CAM controller 103. This CAM controller 103 is independent one having direct access with Processor 105 to access that request with CAM.
The Figure-2 represents the system with level memories. This invention system having Main and Intermediate level memories. The diagram is showing the connection arrangements of Level I/Cache 201 and Level II/CAM 202 with the CAM/Cache Controller 203.
The Figure-3 represents the memory and memory controller arrangements without the complete system view. The figure shows the connections with the level memories with the Main memory and Controller.
Here the total workflow of the Figure-1 and 2-block diagram is discussed. Memory is one of the most crucial components of system along with the processor 105, the controller 102 and the host 110. From the moment that it is switched on until it is shut down, the processor is continuously utilizing memory. It accesses memory in a particular order beginning with Intermediate Memories like Cache and CAM. That means that most data goes into Cache first, whether originating from Main Memory or Input.

When a system is turned on, the processor loads data from Main Memory through Memory control register 104 and conducts a power-on self-test to ensure that all main components are functioning. The memory controller 102 checks the memory chips for errors. Then from the main memory, the system loads the basic input/output operation that gives basic information about storage devices, boot sequence, security and configuration. The system then loads the operating system (OS) to the RAM (Cache/CAM).
Opening an application will cause it to be loaded into Intermediate level memory from the main flash memory. Any files that open in the current application will be placed into Cache as well. In fact, every time we open or load something, it goes into Cache. The processor gets the data it needs from Cache, processes it, and then sends new data back to Cache in a constant cycle.
This constant movement of data between main Memory and Level memories occurs millions of times per second. When we save a file, it is written to the main memory. Then when we close the file or application, they are both removed from Cache or Intermediate memories. If we neglect to save modified files to a permanent storage device before closing them and thus purging them from Cache, the information will be lost. Interfaces 109 like ATA and Ultra DMA are used between host 110 and the memory 101 and Processor 105. So all user inputs are accessed with these interfaces and it reaches the Cache/CAM through control dispatch 108, which is operated by the processor 105.
In Figure-2 the intermediate cache is separated into two levels of memories like level I / Cache and Level II / CAM. So whenever the processor try to fetch some instruction or try to read data from the main memory it is all happening through this intermediate level memories only. Whenever the processor needs to search operation, at the time the CAM comes into picture for fast searching.

This invention brings out the embodiment of CAM as a cache of the system in Figure I. Because CAM itself a memory it can operate as a intermediate memory in any systems, specifically the main advantage of using CAM as a Intermediate memory is for fast searching and fast accessing of main memory.
The Figure II gives the additional view of the same system with two level intermediate memories to speed up the process. Here the CAM is used for only the searching application and the cache is used as an intermediate memory for reading and writing the data.
Terminology
CAM - Content Addressable Memory.
RAM - Random Access Memory.
HCNV - High Capacity Non Volatile.
Volatile Memory - Memory that lasts only while the power is on.
Non-Volatile Memory - Memory that can retain the stored information even when not
powered.
ATA - Advanced Technology Attachment.
DMA - Direct Memory Access
Industrial Applicability
1. Storage Companies
2. Semiconductor Industries
3. Solid State Disk/Drives
4. Computer Memories

Claims
This invention claims,
1. It is an apparatus and method of CAM in system, which is using Solid state Disk
as a main memory or any other volatile and non-volatile memory as a main
memory.
2. The System Claims,
a) A design method of using CAM as cache in the system and CAM as a one
of the intermediate level memory with the system.
b) The method of connecting intermediate memories with the main memory
through the Memory controllers.
c) Method of connecting multilevel intermediate memories with the addition
of CAM.
3. The method and system of using level cache and CAM or only CAM in the solid-
state disks/drives instead of single RAM.
4. The method and system of using one level of cache is for reading the data from
the main memory and another level of memory CAM is used to search in the main
memory.
a) The CAM and Cache using this invention may be Single level or
Multilevel.
b) The system and method of memory used in this invention may be Volatile,
Non-volatile or volatile with battery backup memories.
c) The cache using here manages both data transfers associated with the processors request and also non-volatile storage devices (Main Memory).
d) The main memory can be a Hard Disk Drive (HDD), Tape drive. Optical and RAID level storages.