BACKGROUND
1. Field of the invention
[0001] One or more embodiments of the present invention relate to a solar cell.
2. Description of Related Art
[0002] Solar cells, which are photoelectric devices for converting light (such as solar
light) to electric energy, have become more important due to being a renewable energy
source and their effectively limitless and eco-friendly characteristics, as compared to
other energy sources. The most fundamental structure of a solar cell is a p-n junction
type diode and the solar cells may be classified according to the material of an
absorber layer.
[0003] A general solar cell may have a structure in which electrodes are provided
on a front surface that is an absorber layer, and on a rear surface facing the front
surface. When an electrode is provided on the front surface, a light receiving area is
reduced by an amount as much as the area of the electrode. To address this issue, a
back contact structure, in which an electrode is provided on only a rear surface, is .
used.
SUMMARY
[0004] One or more embodiments of the present invention include a solar cell
having a back contact structure in which efficiency is improved by controlling a gap
between conductive type doped portions, and a method of fabricating the solar cell.
[0005] Additional aspects will be set forth in part in the description which follows
and, in part, will be apparent from the description, or may be learned by practice of the
presented embodiments.
-2-
[0006] According to one or more embodiments of the present invention, a method of
fabricating a solar cell includes forming a doped portion having a first conductive type
on a semiconductor substrate, growing an oxide layer on the semiconductor substrate,
forming a plurality of recess portions in the oxide layer, further growing the oxide layer
on the semiconductor substrate, forming a doped portion having a second conductive
I
type on areas of the semiconductor substrate corresponding to the recess portions,
-
forming a first conductive electrode electrically coupled to the doped portion having the
first conductive type, and forming a second conductive electrode on the semiconductor
•
substrate and electrically coupled to the doped portion having the second conductive
type, wherein a gap between the doped portions having the first and second
conductive types corresponds to a width of the oxide layer formed by further growing
the oxide layer.
[0007] The method may further include doping first conductive type impurities at a
rear surface of the semiconductor substrate at a higher concentration than a front
1
surface of the semiconductor substrate to form a back surface field (BSF), and the
front surface may be configured to receive light. - . ,..
[0008] The plurality of recess portions may be formed by forming paste on firstk
portions of the oxide layer, etching exposed second portions of the oxide layer
including areas other than the first portions, removing the paste, and forming the
plurality of recess portions in areas other than the oxide layer on the doped portion
having the first conductive type.
[0009] The plurality of recess portions may be between where the doped portion
having the first conductive type and the oxide layer are stacked, and where the
semiconductor substrate is exposed due to the etching of the exposed second portions
to remove parts.of the doped portion having the first conductive type.
[0010] The oxide layer may be further grown both on the areas where the doped
portion having the first conductive type and the oxide layer are stacked, and on the
-3-
portions where the semiconductor substrate is exposed, thereby causing the oxide
layer at the areas where the doped portion having the first conductive type and the
oxide layer are stacked to have a thickness, in a width direction that is different than a
thickness in a height direction.
[0011] The thickness of the oxide layer in the width direction at the areas where the
doped portion having the first conductive type and the oxide layer are stacked may be
greater than a thickness of the oxide laye'r in the height direction on the portions where
the semiconductor substrate was exposed. ~~m~~
[0012] The method may further include removing the oxide layer from the portions
where the semiconductor substrate was exposed to expose the semiconductor
substrate.
[0013] The method may further include forming a doped portion having a second
conductive type by injecting a dopant into the portions where the semiconductor
substrate is exposed to diffuse second conductive impurities in the semiconductor
substrate.
[0014] The doped portion having the second conductive type and the doped portion
having the first conductive type may be formed on a first surface of the semiconductor
-
substrate.
[0015] The method may further include forming a capping layer on the
semiconductor substrate where the doped portion having the second conductive type
is formed, and performing a texturing process to remove the doped portion having the
second conductive type from a surface of the semiconductor substrate configured to
receive light.
[0016] The doped portion having the first conductive type may be covered by the
oxide layer, and the areas of the semiconductor substrate corresponding to the recess
portions may be between areas of the doped portion having the first conductive type
_4-
covered by the oxide;layer, and a gap corresponding to a thickness of the oxide layer
is maintained.
[0017] The doped portions having the first and second conductive types may be
isolated from each other by the oxide layer.
[0018] The doped portion having the first conductive type may be covered by the
oxide layer and is electrically coupled to the first conductive electrode via a contact
hole in the oxide layer to form a first resistance contact point, and the doped portion
having the second conductive type may be diffusely formeoHn the semiconductor
substrate and is electrically coupled to the second conductive electrode, to form a
second resistance contact point.
[0019] The method may further include sequentially forming a passivation layer and
an antireflection layer on a front surface of the semiconductor substrate, the front
surface being configured to receive light.
[0020] According to one or more embodiments of the present invention, a solar cell
includes a doped portion having a first conductive type and a doped portion having a
second conductive type on a first surface of a semiconductor substrate, an oxide layer
covering the doped portion having the first conductive type, and a first conductive i
electrode and a second conductive electrode electrically coupled to the doped portion
having the first conductive type and the doped portion having the second conductive
type, respectively, to form resistance contact points, wherein the doped portion having
thefirst conductive type and the doped portion having the second conductive type are
separated from each other by the oxide layer forming a gap therebetween.
[0021] The doped portion having the second conductive type may be located in the
semiconductor substrate between neighboring areas where the doped portion having
the first conductive type and the oxide layer are stacked.
[0022] The gap may have a size corresponding to a thickness of the oxide layer
covering the doped portion having the first conductive type.
-5-
[0023] The solar pell may further include a passivation layer and an antireflection
layer on a second surface of the semiconductor substrate configured to receive light.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] These and/or other aspects will become apparent and more readily
appreciated from the following description of the embodiments, taken in conjunction
with the accompanying drawings in which*:
[0025] FIGS. 1A to 1K sequentially illustrate a method oTfabricating a thin film type
solar cell according to an embodiment of the present invention, in which:
[0026] FIG. 1A is a cross-sectional view illustrating a state after a semiconductor
substrate according to an embodiment of the present invention is prepared;
[0027] FIG. 1B is a cross-sectional view illustrating a state after an n+ conductive
type doped portion is formed in the semiconductor substrate of the embodiment shown
in FIG. 1A;
[0028] FIG. 1C is a cross-sectional view illustrating a state after an oxide layer (e.g.,
a silicon dioxide (Si02) layer) is formed on the semiconductor substrate of the ,-•
embodiment shown in FIG. 1B; l
[0029] FIG. 1D is a cross-sectional view illustrating a state after paste is patterned
on the semiconductor substrate of the embodiment shown in FIG. 1C;
[0030] FIG.. 1E is a cross-sectional view illustrating a state after the oxide layer is
etched on the semiconductor substrate of the embodiment shown in FIG. 1D;
[0031] FIG. 1F is a cross-sectional view illustrating a state after the paste is
removed from the semiconductor substrate of the embodiment shown in FIG. 1E;
[0032] FIG. 1G is a cross-sectional view illustrating a state after a recess is formed
in the semiconductor substrate of the embodiment shown in FIG. 1F;
[0033] FIG. 1H is a cross-sectional view illustrating a state after an oxide layer is
formed on the semiconductor substrate of the embodiment shown in FIG. 1G;
-6-
[0034] FIG. 11 is across-sectional view illustrating a state after the oxide layer is
etched on the semiconductor substrate of the embodiment shown in FIG. 1H;
[0035] FIG. 1J is a cross-sectional view illustrating a state after a p+ conductive
type doped portion is formed on the semiconductor substrate of the embodiment
shown in FIG. 11;
[0036] FIG. 1K is a cross-sectional view illustrating a state after a passivation layer,
an antireflection layer, a first conductive electrode, and a second conductive electrode
are formed on the semiconductor substrate of the embodimenTshown in FIG. 1 J;
[0037] FIG. 2 is an enlarged cross-sectional view of a portion A of FIG. 1H;
[0038] FIG. 3 is an enlarged cross-sectional view of a portion B of FIG. 1 J;
[0039] FIG. 4A is a cross-sectional view illustrating a state after an oxide layer is
formed on a substrate according to another embodiment of the present invention; and
[0040] FIG. 4B is a cross-sectional view illustrating a state after a p+ conductive
type doped portion is formed on the substrate of the embodiment shown in FIG. 4A.
t
DETAILED DESCRIPTION
[0041] Reference will now be made in detail to embodiments of the present >•
invention, examples of which are illustrated in the accompanying drawings, wherein,
like reference numerals refer to like elements throughout. In this regard, the
embodiments of the present invention may have different forms, and should not be
construed as being limited to the descriptions set forth herein. Accordingly, the
embodiments are merely described below, by referring to the figures, to explain
aspects of embodiments of the present invention.
[0042] The terms such as "first" and "second" are used herein merely to describe a
variety of constituent elements, but the constituent elements are not limited by the
terms. The terms are used only for the purpose of distinguishing one constituent
element from another constituent element.
•
-7-
I
[0043] The terms used in the present specification are used for explaining a specific
exemplary embodiment(s), not for limiting the present invention. Thus, the expression
of singularity in the present specification includes the expression of plurality, unless the
context clearly specifies otherwise. Also, the terms such as "include" or "comprise"
may be construed to denote a certain characteristic, number, step, operation,
constituent element, or a combination thereof, but may not be construed to exclude the
existence of, or a possibility of addition of, one or more other characteristics, numbers,
steps, operations, constituent elements, or combinations thereof.
[0044] FIG. 1K illustrates a solar cell 100 with a back contact structure according to
an embodiment of the present invention. Referring to FIG. 1K, the solar cell 100
includes a semiconductor substrate 101. The semiconductor substrate 101 of the
-
present embodiment is an absorber layer. The semiconductor substrate 101 is a
single-crystalline silicon substrate, or may include a polysilicon substrate. An n-type
impurity may include a group V element such as phosphorus (P) or arsenic (As).
[0045] In the present embodiment, a silicon substrate including n-type impurities is
-
used as the semiconductor substrate 101, although the present invention is not Jimited
thereto. For example, a single-crystalline silicon substrate or a polycrystalline silicon
substrate doped with p-type impurities may be used as the semiconductor substrate
101. The p-type impurities may include a group III element such as boron (B),
aluminum (Al),. or gallium (Ga).
[0046] The semiconductor substrate 101 includes a texture structure (e.g., a rough
or textured surface). The solar cell 100 has a cross-section of a pyramid shape, or a
triangular shape, on a front surface 120 of the semiconductor substrate 101 for
receiving light, as indicated by an arrow at the bottom of FIG. 1K. The texture structure
*
of the solar cell 100 may reduce reflection of incident light, increase the length of a light
passage in the semiconductor substrate 101, and increase the quantity of absorbed
-8-
1 light using internal reflection. Thus, a short-circuit current of the solar cell 100 may be
improved.
[0047] A passivation layer 117 is formed on the front surface 120 of the
semiconductor substrate 101. The passivation layer 117 may include amorphous
silicon (a-Si) doped with impurities, or silicon nitride (SiNx). When the passivation layer
117 includes the a-Si doped with impurities, the passivation layer 117 is in a state of
being doped with the same conductive impurities as the semiconductor substrate 101,
although at a higher concentration than the semiconductofsub'strate 101.
[0048] The passivation layer 117 may improve a carrier collection efficiency by
preventing surface recombination of carriers generated in the semiconductor substrate
101. For example, since the passivation layer 117 prevents carriers from moving
toward the front surface 120 of the semiconductor substrate 101, the passivation layer
117 may prevent carriers from disappearing as electrons and holes are recombined
with each other in the vicinity of the front surface 120 of the semiconductor substrate
101.
[0049] An antireflection layer 118 is formed on the passivation layer 117. The
antireflection layer 118 reduces or prevents a loss in light absorption by the solar cell
100 due to the reflection of light when solar light is incident. Thus, an efficiency of the
solar cell 100 may be improved.
[0050] The antireflection layer 118 includes a transparent material, for example,
SiOx, SiNx, SiOxNy, TiOx, ZnO, orZnS. Although the antireflection layer 118 of the '
present embodiment is a single layer, the antireflection layer 118 may also be formed
by stacking a plurality of layers having different refractive indexes.
[0051] Although the passivation layer 117 and the antireflection layer 118 of the
present embodiment are separate layers, the present invention is not limited thereto.
For example, by forming silicon nitride (SiNx), a function of the passivation layer 117
and a function of the antireflection layer 118 may be simultaneously performed.
-9-
[0052] An emitter layer 112 is formed on a rear surface 130 of the semiconductor
substrate 101. The emitter layer 112 forms a p-n junction with the semiconductor
substrate 101, and is doped with p-type or n-type impurities. When the semiconductor
substrate 101 is of an n-type, the emitter layer 112 includes p-type impurities. When
the semiconductor substrate 101 is of a p-type, the emitter layer 112 includes n-type
impurities. A diffusion area is of a stripe-type, or is of a dot-type, the dots having a
shape such as, for example, a circle or ah oval. In the present embodiment, the
emitter layer 112 corresponds to a p+ conductive type dop^stTportion (e.g., a doped
portion having a p+ conductive type).
[0053] A base layer 102 is formed on the rear surface 130 of the semiconductor
substrate 101. The base layer 102 includes impurities that are the same type as that
of the semiconductor substrate 101. The base layer 102 is doped with impurities at a
higher concentration than that of the semiconductor substrate 101, forming a back
surface field (BSF).
i
[0054] The base layer 102 is doped with n-type or p-type impurities. An impurity
9
diffusion area may be of a stripe-type, or may be of a dot-type, such as a circle pr an
oval. The emitter layer 112 and the base layer 102 are interdigitated with each other
on the rear surface 130 of the semiconductor substrate 101. In the present
embodiment, the base layer 102 corresponds to an n+ conductive type doped portion
(e.g., a doped portion having an n+ conductive type)..
[0055] A first conductive electrode 113 is formed above the base layer 102. An
insulation layer 103 is formed between the base layer 102 and the first conductive
electrode 113. The first conductive electrode 113 includes silver (Ag), gold (Au),
copper (Cu), aluminum (Al), and an alloy thereof. The first conductive electrode 113
forms an ohmic.contact with the base layer 102 via a contact hole 115.
[0056] A second conductive electrode 114 is formed on an upper surface of the
emitter layer 112, and may include silver (Ag), gold (Au), copper (Cu), aluminum (Al),
-10-
J
and/or an alloy thereof. The second conductive electrode 114 forms an ohmic contact
with the emitter layer 112.
[0057] The insulation layer 103 includes a silicon oxide layer that is an oxide layer
grown on the semiconductor substrate 101 formed of silicon. A method of fabricating
the solar cell 100 with a back contact structure having the above-described layer is
described below.
[0058] Referring to FIG. 1A, the semiconductor substrate 101 is prepared. The
semiconductor substrate 101 may include a single-crystalline silicon substrate or a
polycrystalline silicon substrate. The semiconductor substrate 101 may be a singlecrystalline
or polycrystalline silicon substrate doped with n-type or p-type impurities. In
the present embodiment, the semiconductor substrate 101 includes n-type impurities.
The semiconductor substrate 101 may undergo a cleaning process using an acid or
alkali liquid to remove physical or chemical impurities adhering to a surface thereof.
[0059] Next, as illustrated in FIG. 1B, an n+ conductive type doped portion 102 is
formed on a surface of the semiconductor substrate 101. To form a BSF on one
surface of the semiconductor substrate 101, the semiconductor substrate 101 is
inserted in a diffusion chamber (not shown) and then thermally treated at a high l
temperature after a gas containing an n-type dopant, for example, POCI3, is injected in
the diffusion chamber, thereby forming the n+ conductive type doped portion 102.
[0060] Next, as illustrated in FIG. 1C, a silicon dioxide (Si02) layer 103, which is an
oxide layer, is formed on a surface of the semiconductor substrate 101 by growing
silicon by a wet oxidation process. The thickness of the Si02 layer 103 may be about
1000A or more. The atmosphere in the diffusion chamber for growing silicon may be
an atmosphere of a mixed gas including oxygen (O2) and nitrogen (N2).
[0061] After the Si02 layer 103 is formed, as illustrated in FIG. 1D, paste 104
formed of an organic material is patterned on a rear surface of the semiconductor
-11-
substrate 101. The paste 104 may be formed, or patterned, by a screen print method,
and may be patterned in a stripe shape or a dot shape.
[0062] As illustrated in FIG. 1E, the Si02 layer 103 is etched using a buffered oxide
etchant (BOE) solution or a hydrogen fluoride (HF) solution. Accordingly, the Si02
layer 103 that is exposed after the paste 104 has been patterned is removed from the
semiconductor substrate 101.
[0063] Next, as illustrated in FIG. 1F, the paste 104 is removed. The paste 104
may be removed by being dipped into a dipping bath (not sTiown) OF potassium
hydroxide (KOH) of a low concentration. Accordingly, the Si02 layer 103 that is
patterned is formed on the semiconductor substrate 101.
[0064] After the Si02 layer 103 is patterned, as illustrated in FIG. 1G, the Si02 layer
103 is etched by being dipped into a dipping bath of KOH of a high concentration. The
n+ conductive type doped portion 102 that is exposed where the Si02 layer 103 is not
patterned is removed from the semiconductor substrate 101.
[0065] Accordingly, the n+ conductive type doped portion 102 existing outside an
area where the n+ conductive type doped portion 102 and the Si02 layer 103 are
stacked is removed from the semiconductor substrate 101, and thus, a recess
portion(s) 119 (where the n+ conductive type doped portion 102 is removed) is formed.
The recess portion 119 corresponds to an area formed by a difference in the thickness
between a portion where the n+ conductive type doped portion 102 and the Sid2 layer
103>are stacked, and a portion where the surface of the semiconductor substrate 101
is exposed due to the removal of the n+ conductive type doped portion 102 (e.g., the
recess portion 119 is the areas where the surface of the semiconductor substrate 101
is exposed between the areas of the oxide layer 103).
[0066] The surface of the semiconductor substrate 101 becomes smooth by mixing
isopropyl-alcohol (IPA) as an additive in the KOH solution.
-12-
i
[0067] Next, as illustrated in FIG. 1H, a second growth of the Si02 layer 103 is
performed on the semiconductor substrate 101 by a wet oxidation process, thereby
further increasing the thickness of the Si02 layer 103. In the growth by the wet
oxidation process, a doping concentration, an orientation of a silicon lattice, and a
surface roughness of the semiconductor substrate 101 are important. A vertical {010}
plane and a smooth surface may be embodied when the recess portion 119 is formed
by using a mixed solution (KOH+IPA) of fcOH and IPA in the step corresponding to
FIG. 1G. "*~"
[0068] Accordingly, the thickness of the SiC>2 layer 103 is increased by the second
growth. As illustrated in FIG. 2, a first thickness d1 of a SiC>2 layer 103a covering the
n+ conductive type doped portion 102 (e.g., a thickness in a width direction) is thicker
than a second thickness d2 of a Si02 layer 103b that is grown at an area where the n+
conductive type doped portion 102 is removed (e.g., a thickness in a height direction),
that is, an area of a surface of the semiconductor substrate 101 where the recess
l
portion 119 is formed. A growth speed of an oxide layer of the first thickness d1 is
about 2.5 to 3 times faster than that of the second thickness d2. .,.
[0069] When a dopant (e.g., impurities) is injected in the silicon, vacancies are ^
generated in the silicon, and the impurities and vacancies weaken a combination ,
structure of silicon. As such, oxygen may easily combine with silicon. Thus, the more
dopant is injected, the faster the growth speed of an oxide layer will be.
[0070] Also, the atmosphere in the diffusion chamber for growing silicon may be'a 1
mixed gas atmosphere of oxygen (O2) and nitrogen (N2).
[0071] Next, as illustrated in FIG. 11, the Si02 layer 103 is etched by using a BOE
solution or a HF solution. Accordingly, while removing the Si02 layer 103b of FIG. 2 in
the area where the n+ conductive type doped portion 102 is not formed, the Si02 layer
103a of FIG. 2 covering the portion where the n+ conductive type doped portion 102 is
formed remains.
-13-
_
[0072] In other words, since the Si02 layer 103a covering the portion where the n+
conductive type doped portion 102 is formed grows to be about 2.5 to 3 times thicker
than the Si02 layer 103b in the area where the n+ conductive type doped portion 102 is
not formed, an etching process is performed only for a time during which the SiC>2 layer
103b in the area where the n+ conductive type doped portion 102 is not formed is
removed.
[0073] As illustrated in FIG. 1 J, a p+ conductive type doped portion 112 is formed
on the rear surface of the semiconductor substrate 101. fothis end, the
semiconductor substrate 101 is inserted in the diffusion chamber and undergoes a
thermal treatment at a high temperature after a gas containing a p-type dopant, for
example, boron tribromide (BB^), is injected in the diffusion chamber.
[0074] Accordingly, the p-type dopant is diffused in the semiconductor substrate
101, and thus, the p+ conductive type doped portion 112 is formed in the recess
portion 119. A boron-rich (Br) layer is formed on a surface of the p+ conductive type
doped portion 112. The Br layer may be removed by using HF.
[0075] The p+ conductive type doped portion 112 may be formed not only on the
rear surface 130 of the semiconductor substrate 101, but also on the front surface 120
and side surfaces of the semiconductor substrate 101, simultaneously. To remove the
p+ conductive type doped portion 112, an undoped silicon glass (USG) layer that is a
capping layer is deposited on the rear surface 130 of the semiconductor substrate 101.
•
The p+ conductive type doped portion 112 formed on the front surface 120 and side
surfaces of the semiconductor substrate 101 is removed by a texturing process using a
mixed solution (KOH+IPA) of KOH and IPA.
[0076] Accordingly, as illustrated in FIG. 3, a gap of about several hundreds of
angstroms (A) between the n+ conductive type doped portion 102 and the p+
conductive type doped portion 112 is maintained because of the SiC>2 layer 103 that
covers the n+ conductive type doped portion 102. Since a portion corresponding to the
-14-
gap g is an area irrelevant to (e.g., that does not contribute to) an efficiency of the solar
cell 100 during an operation of the solar cell 100, if the area corresponding to the gap g
increases, the efficiency of the solar cell 100 is degraded. Thus, the portion where the
gap g is formed may be reduced as much as feasibly possible.
[0077] According to the present embodiment, while the gap g between the n+
conductive type doped portion 102 and the p+ conductive type doped portion 112 is
reduced to approximately 1/1000 of a conventional gap, isolation of each of the n+
conductive type doped portion 102 and the p+ conductive iype"doped portion 112 is
guaranteed.
[0078] Furthermore, a pattern process of forming a separate gap to maintain a gap
between the n+ conductive type doped portion 102 and the p+ conductive type doped
portion 112 is not needed. As such, since the n+ conductive type doped portion 102
and the p+ conductive type doped portion 112 are formed in a self-alignment method,
the n+ conductive type doped portion 102 and the p+ conductive type doped portion
i > ,
112 each may be formed to have a fine width.
[0079] In addition to the method of using BBr3, the method of forming the p+ ,..
conductive type doped portion 112 is not limited to any one of the methods of forming
the p+ conductive type doped portion 112 on the semiconductor substrate 101. In ,
other words, boron silicate glass (BSG) may be deposited on the semiconductor
substrate 101 by an atmospheric pressure chemical vapor deposition (APCVD)
method, and the semiconductor substrate 101 may undergo a thermal treatment at a
high temperature. Accordingly, the p+ conductive type doped portion 112 is formed in
the recess portion 119 as the p-type dopant is diffused in the semiconductor substrate
101. The BSG is deposited on one surface of the semiconductor substrate 101 by
using a mask, etc. After the p+ conductive type doped portion 112 is formed, the BSG
at the other portion is removed by using HF. Also, the p+ conductive type doped
portion 112 may be formed by a laser method.
-15-
[0080] As illustrated in FIG. 4A, an n+ conductive type doped portion 402, which
may be patterned on a semiconductor substrate 401 in the above method, and a Si02
layer 403 covering the n+ conductive type doped portion 402 are patterned. Then, as
illustrated in FIG. 4B, a boron material is coated on the semiconductor substrate 401,
and a laser may be irradiated onto the boron material so that a p-type dopant is
diffused in the semiconductor substrate 401 through a recess portion 419 to form the
p+ conductive type doped portion 412. .'
[0081] As described above, the n+ conductive type dop^Tportion 402 and the p+
conductive type doped portion 412 maintaining a narrow gap due to the oxide layer
may be formed to be interdigitated with each other on a rear surface of the
semiconductor substrate 401 through the above processes.
[0082] Referring back to FIG. 1K, a pyramid, or saw tooth, surface is formed on the
front surface 120 of the semiconductor substrate 101 through the texturing process.
To this end, the semiconductor substrate 101 uses the mixed solution (KOH+IPA) of
i
KOH and IPA.
[0083] Next, the passivation layer 117 and the antireflection layer 118 are ,
sequentially formed on the front surface 120 of the semiconductor substrate 101 to
have the pyramid/saw tooth surface formed by the texturing process. The cleaning ,of
the semiconductor substrate 101 may be performed before the passivation layer 117 is
formed.
[0084] The passivation layer 117 may include amorphous silicon doped with
impurities. For example, the passivation layer 117 may be formed as an n+ layer of a
high concentration on the front surface 120 of the n-type semiconductor substrate 101.
The passivation layer 117 formed as described above may form a front surface field
(FSF) to reduce.loss due to recombination of holes and electrons.
_
-16-
[0085] Alternatively, the passivation layer 117 may include silicon nitride (SiNx).
The passivation layer 117 may be formed by a plasma-enhanced chemical vapor
deposition (PECVD) method.
[0086] Since the passivation layer 117 is formed at the front surface 120 of the
semiconductor substrate 101, which is a light-receiving surface, the passivation layer
117 may adjust a band gap to reduce light absorption. For example, by adding an
additive, the band gap is increased so that light absorption is reduced and incident light
may be absorbed into the semiconductor substrate 101. ~"--*
[0087] The antireflection layer 118 is formed on the passivation layer 117, and may
include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), etc., and
may be formed by a CVD method, a sputtering method, a spin coating method, etc.
For example, the antireflection layer 118 may be formed as a single layer of SiOx, SiNx,
or SiOxNy, or a combination layer thereof.
[0088] Although the passivation layer 117 and the antireflection layer 118 are
l
described as independently formed in the present embodiment, the present invention is
not limited thereto. For example, the passivation layer 117 and the antireflection layer
118 may be formed as a single layer, such as by forming a layer containing SiNx, v
wherein a passivation effect and an antireflection effect may be obtained.
[0089] The first conductive electrode 113 and the second conductive electrode 114
are formed on the n+ conductive type doped portion 102 and the p+ conductive type
doped portion 112, respectively. To this end, the contact hole 115 is formed in the'
Si02 layer 103. The contact hole 115 is formed in an area corresponding to the n+
conductive type doped portion 102. The contact hole 115 may be formed by using
laser or screen printing using an etching paste.
[0090] Next, conductive paste such as, for example, silver (Ag), gold (Au), copper
(Cu), aluminum (Al), or nickel (Ni) is pattern-printed on the rear surface 130 of the
semiconductor substrate 101 by screen printing or plating, and is thermally treated.
-17-
Accordingly, the first conductive electrode 113 forming a resistance contact point with
respect to the n+ conductive type doped portion 102 is coupled to the n+ conductive
Ytype
doped portion 102. The second conductive electrode 114 forming a resistance
contact point with respect to the p+ conductive type doped portion 112 is coupled to
the p+ conductive type doped portion 112. Thus, the solar cell 100 having a back
contact structure in which the gap between the n+ conductive type doped portion 102
and the p+ conductive type doped portion' 112 is reduced may be fabricated through
the above processes. ••^—~
[0091] The gap in the solar cell 100 according to an experiment by the present 8
applicant is shown below in Table 1. 1
Table 1 ^____
Comparative example (urn) Present embodiment (urn)
Emitter area 1550 1750 j
Gap 100 i 0.1 l
* i!*
[0092] In the comparative example, a gap between a conventional n+ conductive ;
type doped portion and a conventional p+ conductive type doped portion is formed by j
performing an additional and separate gap pattern process after a screen printing
method and a wet chemical process. In the present embodiment, the gap between the n+ conductive type doped portion 102 and the p+ conductive type doped portion 112 is j
maintained by the Si02 layer 103.
[0093] Referring to Table 1, in the comparative example, the width of an emitter
area corresponding to the p+conductive type doped portion is about 1550 urn. In the
present embodiment, the width of an emitter area is about 1750 urn, which is about
200 urn wider than the width of the emitter area in the comparative example. Also, in
the comparative example, the gap between the n+ conductive type doped portion and
-18-
the p+ conductive type doped portion is about 100 um. In the present embodiment, the I
gap between the n+ conductive type doped portion 102 and the p+ conductive type
doped portion 112 is about 0.1 um. Thus, it may be seen that the gap of the present
embodiment is reduced to about 1/1000th of the size of the gap of the comparative
example. I
[0094] As such, since the gap between the n+ conductive type doped portion 102 I
and the p+ conductive type doped portion 112 does not contribute to an efficiency of
the solar cell 100, and since a size of the gap is reduced, th"eTefficiency of the solar cell
100 may be improved.
[0095] As described above, in the solar cell and the method of fabricating a solar
cell according to embodiments of the present invention, since the gap between the first
and second conductive type doped portions formed on the rear surface of a solar cell
having a back contact structure is narrow, due to using a difference in the growth
speed of portions of an oxide layer according to the first and second conductive layer
1
doping concentrations, an efficiency of the solar cell may be improved.
[0096] Further, since an additional pattern process for adjusting the gap between
the first and second conductive type doped portions is not needed, a fabrication
process time of a solar cell is reduced, and fabrication costs may be reduced.
[0097] Further, since self-alignment is possible, a shunt path due to.an error in
alignment is not generated.
[0098] Further, since a width of the first conductive type doped portion and a width
of the second conductive type doped portion are much reduced, a large number of
interdigitated lines may be formed in a semiconductor substrate.
[0099] It should be understood that the exemplary embodiments described herein
should be considered in a descriptive sense only and not for purposes of limitation.
Descriptions of features or aspects within each embodiment should typically be
considered as available for other similar features or aspects in other embodiments.
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m
- ^ 1
s
• " • • •" !
I
[00100] While embodiments of the present invention has been particularly shown |
and described with reference to exemplary embodiments thereof, it will be understood by one of ordinary skill in the art that various changes in form and details may be made I
therein without departing from the spirit and scope of the present invention as defined
by the following claims, and their equivalents.

WeClaim: ^
1. A method of fabricating a solar cell, the method comprising:
forming a doped portion having a first conductive type on a semiconductor
substrate;
growing an oxide layer on the semiconductor substrate;
forming a plurality of recess portions in the oxide layer;
further growing the oxide layer on the semiconductor substrate;
forming a doped portion having a second conductive type on areas of the
semiconductor substrate corresponding to the recess portions;
forming a first conductive electrode electrically coupled to the doped portion
having the first conductive type; and
forming a second conductive electrode on the semiconductor substrate and
electrically coupled to the doped portion having the second conductive type,

wherein a gap between the doped portions having the first and second
conductive types corresponds to a width of the oxide layer formed by further growing
the oxide layer. "^
2. The method as claimed in claim 1, further comprising doping first
conductive type impurities at a rear surface of the semiconductor substrate at a higher
concentration than a front surface of the semiconductor substrate to form a back
surface field (BSF),
wherein the front surface is configured to receive light.
3. The method as claimed in claim 1, wherein the plurality of recess portions
is formed by:
forming paste on first portions of the oxide layer;
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etching expo^^d second portions of the oxide layer comprising areas other than
the first portions;
removing the paste; and
forming the plurality of recess portions in areas other than the oxide layer on the
doped portion having the first conductive type.
4. The method as claimed in claim 3, wherein the plurality of recess portions
are between where the doped portion having the first concluctive type and the oxide
layer are stacked, and where the semiconductor substrate is exposed due to the
etching of the exposed second portions to remove parts of the doped portion having
the first conductive type.
5. The method as claimed in claim 4, wherein the oxide layer is further
grown both on the areas where the doped portion having the first conductive type and
the oxide layer are stacked, and on the portions where the semiconductor substrate is
exposed, thereby causing the oxide layer at the areas where the doped portiori having
the first conductive type and the oxide layer are stacked to have a thickness in a width
direction that is different than a thickness in a height direction.
6. The method as claimed in claim 5, wherein the thickness of the oxide
layer in the width direction at the areas where the doped portion having the first
conductive type and the oxide layer are stacked is greater than a thickness of the oxide
layer in the height direction on the portions where the semiconductor substrate was
exposed.
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7. The mefhod as claimed in claim 5, further comprising removing the oxide
layer from the portions where the semiconductor substrate was exposed to expose the
semiconductor substrate.
8. The method as claimed in claim 1, further comprising fomning a doped
portion having a second conductive type by injecting a dopant into the portions where
the semiconductor substrate is exposed 'to diffuse second conductive impurities in the
semiconductor substrate. -^—*
9. The method as claimed in claim 8, wherein the doped portion having the
second conductive type and the doped portion having the first conductive type are
formed on a first surface of the semiconductor substrate.
10. The method as claimed in claim 8, further comprising forming a capping
I
layer on the semiconductor substrate where the doped portion having the second
conductive type is formed, and ,
performing a texturing process to remove the doped portion having the second
conductive type from a surface of the semiconductor substrate configured to receive
light.
> 11. The method as claimed in claim 1, wherein the doped portion having the
first conductive type is covered by the oxide layer, and
wherein the areas of the semiconductor substrate corresponding to the recess
portions are between areas of the doped portion having the first conductive type
covered by the oxide layer, and a gap corresponding to a thickness of the oxide layer
is maintained.
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12. The method as claimed in claim 11, wherein the doped portions having
the first and second conductive types are isolated from each other by the oxide layer.
13. The method as claimed in claim 1, wherein the doped portion having the
first conductive type is covered by the oxide layer and is electrically coupled to the first
conductive electrode via a contact hole in the oxide layer to form a first resistance
contact point, and *
wherein the doped portion having the second conductive type is diffusely fonned
in the semiconductor substrate and is electrically coupled to the second conductive
electrode, to form a second resistance contact point.
14. The method as claimed in claim 1, further comprising sequentially
forming a passivation layer and an antireflection layer on a front surface of the
semiconductor substrate, the front surface being configured to receive light.
15. A solar cell comprising: ,
a doped portion having a first conductive type and a doped portion having a
second conductive type on a first surface of a semiconductor substrate;
an oxide layer covering the doped portion having the first conductive type; and
a first conductive electrode and a second conductive electrode electrically
coupled to the doped portion having the first conductive type and the doped portion
having the second conductive type, respectively, to form resistance contact points,
wherein the doped portion having the first conductive type and the doped
portion having the second conductive type are separated from each other by the oxide
layer forming a gap therebetween.
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16. The solar; cell as claimed in claim 15, wherein the doped portion having
the second conductive type is located in the semiconductor substrate between
neighboring areas where the doped portion having the first conductive type and the
oxide layer are stacked.
17. The solar cell as claimed in claim 15, wherein the gap has a size
conresponding to a thickness of the oxides layer covering the doped portion having the
first conductive type. ^^.^*
18. The solar cell as claimed in claim 15, further comprising a passivation
layer and an antireflection layer on a second surface of the semiconductor substrate
configured to receive light.