Description:Scaling of CMOS technology improved the speed nevertheless the leakage currents are
leftover as an adverse effect. The problem has taken a serious turn as the scaling extends into
ultra-deep-submicron (UDSM) region. These unsolicited leakage currents should be
minimized for the smooth functioning of the circuit. In this invention a novel architecture is
proposed to reduce the leakage current for CMOS technology. Figure 1 shows the circuit architecture for CMOS logic. The invention includes one leakage
controlled PMOS (LCT-P) network 101, one leakage controlled NMOS (LCT-N) network 102
and one drain gating (DG) network 103 connected in series. The inputs are applied to the pullup and pull down network. The body connection for pull up network MOSFETs are connected
to the supply voltage and for pull down network MOSFETS it is connected to ground
terminal.Figure 2 shows the internal circuit diagram of leakage controlled PMOS (LCT-P) network
101. The LCT-P network is basically two body biased PMOS connected in series. Due to
series connection it provides extra stack characteristics to the circuit and the body bias
connection can be used to vary the threshold voltage and thereby controlling the leakage
current. As the two PMOS transistors are used only to provide stacking effect, both MOSFETs
have same inputs. Figure 3 shows the internal circuit diagram of leakage controlled NMOS (LCT-N) network
102. The LCT-N network is basically two body biased NMOS connected in series. Due to
series connection it provides extra stack characteristics to the circuit and the body bias
connection can be used to vary the threshold voltage and thereby controlling the leakage
current. As the two NMOS transistors are used only to provide stacking effect, both
MOSFETs have same inputs.The gating approach is a well known approach for power consumption reduction. In this
invention the drain gating technique 103 is used to further reduce the static power
consumption. Sleep and sleep bar signal is applied to the PMOS and NMOS respectively to
deactivate the respecting transistors when there are not in use. This way it block the flow of
leakage current and saves lots of static power consumption. Figure 4 shows the leakage current for NOR gate implemented using the proposed
architecture. Fig. 5 shows the simulation performance for the NOR gate simulated in SPICE
environment. , Claims:The proposed circuit architecture reduces the static power consumption considerably. The architecture uses leakage controlled transistors, drain gating transistors as the main design
component. The leakage controlled transistors are body biased to control the threshold voltage value. This architecture can be used to implement any logic function that follows CMOS technology. The architecture shows good performance in terms of delay also.