DESC:
TECHNICAL FIELD
[0001] The present disclosure relates to the field of power inverter. In particular, the present disclosure pertains to a three (3)-level high power inverter having six (6) IGBT’s per phase.

BACKGROUND
[0002] The background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Traditionally, generation of electricity has involved rotating machines to produce alternating sinusoidal voltage and current. With the development in power segment, electronic device such as an Inverter is primarily utilized to convert direct current (DC) to alternating current (AC), wherein the Inverter can broadly be classified as Voltage Source Inverter (VSI) and Current Source Inverter (CSI), wherein VSI generated AC output is in a voltage waveform, and CSI generated AC output is in a current waveform. Furthermore, on the basis of circuit connection arrangements, inverters are classified as Bridge inverters, Series inverters, Parallel inverters, or multi-level inverters.
[0004] Multi-level inverter is a power electronic device that receives multiple lower level DC voltages as an input and generates desired alternating voltage level at output. For multilevel inverters, the more the levels employed, closer will the output approximate a sine wave and the lower would be the harmonic content. Multi-level inverter incorporates power switching electric appliances such as insulated-gate bipolar transistors (IGBTs) to enable faster switching and reduced demanding of a gate drive requirements. Such multi-level inverter significantly reduces size and weight of passive filter components and offers better voltage waveforms with less harmonic contents. Due to rapid switching capability of IGBTs, it is advantageous to supply them with DC voltages in multiple levels to produce near sinusoidal output voltages. The most frequently used multi-level inverters are two-level inverters and three-level inverters, wherein the three-level inverter/3-level inverter topology with smaller output voltage steps is predominantly used nowadays to replace two-level inverters and mitigate two-level inverter issues such as surge voltages and rate of voltage rise.
[0005] Two-level inverters produce a modulated output having two fixed voltage levels. While potentially low cost, there are some drawbacks associated with using two-level inverters. First, the voltage swing of the inverter transistors is equal to the full, applied DC rail voltage of the inverter. This voltage swing can cause significant switching loss in the inverter transistors. Stated differently, switching loss of an inverter transistor is proportional to the amplitude of the voltage swing. To compensate for these switching losses, a lower PWM frequency may be chosen. However, this frequency may be so low that it creates audible noise (<20 kHz) or excessive output ripple current. A further drawback of two-level inverters is that the voltage output is typically derived directly from the switching bridge and may have a very high content of high frequency harmonics. This may cause additional losses in the output filter when used in typical applications.
[0006] Three-level inverters produce a modulated output consisting of three fixed voltage levels. For a given output voltage, this results in a lower voltage swing across the transistors than in the two-level inverters discussed above. As a result, three-level inverters produce fewer high-frequency voltage harmonics (i.e. significant amounts of energy at frequencies that are multiples of the switching frequency), allowing one to use smaller and cheaper output filter chokes (i.e. the inductive element of the output filter used to isolate the output alternating current from the output of the inverter). The reduced voltage swing and switching losses characteristic of three-level inverters make these inverters generally more efficient than two-level inverters. However, three-level inverters are typically more complex and expensive than two-level inverters.
[0007] FIG. 1A illustrates a conventional three-level inverter showing 4 IGBTs and 2 diodes per phase. As seen in FIG. 1A (Prior Art), the inverter includes a plurality of DC nodes, a positive DC bus node 102, and a negative DC bus node 110. Existing three-level inverter 100 further includes a plurality of DC linking capacitors 104 and 106 connected in series that can define a neutral point (NP) 108 between them. The inverter 100 further includes a plurality of clamping diodes 120 (D5) and 122 (D6), where the neutral point 108 is configured between the two clamping diodes 120 and 122. The conventional inverter 100 further includes 4 Insulated Gate Bipolar Transistors (IGBTs) 112 (Q1), 114 (Q2), 116 (Q3), and 118 (Q4), which, along with the clamping diodes 120 (D5) and122 (D6), convert DC power to AC power. As can be seen, IGBT 112 is connected to positive node 102, and includes a drain terminal 112a, source terminal 112b, and a freewheeling diode 112c connected across the drain terminal 112a and the source terminal 112b. Similar construction is also configured for other IGBTs Q2 to Q4.
[0008] The most common switching elements used in inverter designs are field effect transistors (FET), such as metal oxide field effect transistors (MOSFET), bipolar transistors, such as insulated gate bipolar transistors (IGBT) and bipolar junction transistors (BJT), and gate turn-off thyristors (GTO). Traditionally, MOSFETs have been used for low DC voltage or low power inverter designs; IGBTs have been used in medium to high power or high voltage inverter designs; and GTOs have been used in very high power inverter designs.
[0009] FIG. 1B illustrates control scheme normally implemented by a conventional 3-level diode inverter. The control schemes are normally used to avoid rapid commutation of the body diodes of the FETs/ MOSFETs/ bipolar transistors by using control signals that depend on phase quadrant and further swap control signals between each set of series connected FETs/ MOSFETs and bipolar transistors when operating in second quadrant (Q2) or fourth quadrant (Q4). These control signals may be generated by a micro-controller, a state machine implemented on and FPGA or ASIC, or in a number of other semiconductor devices used in the prior-art.
[0010] However, existing three-level inverters require complex control schemes, and also suffer from a major technical limitation that a charge at mid-point between two DC linking capacitors can accumulate/gather when switching is not balanced, which can lead to DC link capacitor voltage imbalance. Also, other technical problem observed is that oscillations occur in the neutral point (NP) potential (NPP) due to imbalanced DC-link voltage caused by uneven charging/discharging of the DC–link capacitors, leading to distortion of the inverter output voltage. Further, the existing three-level inverters also have the problem of overvoltage spikes of middle IGBT’s used in 3-level inverters, which can be as high as 100%, and therefore are not power efficient. To avoid this most of the conventional power converters use snubber circuitry to protect the switching devices (IGBTs) from overvoltage spikes.
[0011] There is therefore a need in the art to provide a simplified, efficient, cost effective, and fault tolerant improved 3-level high power inverter that provides a better control scheme or strategy to enable higher power efficiency, lower cost, and better performance compared to conventional 3–Level Inverter.
[0012] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0013] In some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
[0014] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0015] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.

OBJECTS OF THE INVENTION
[0016] It is an object of the present disclosure to provide a 3-level high power inverter that includes 6 IGBT’s per phase.
[0017] It is another object of the present disclosure to provide a fault tolerant and improved 3-level inverter that includes 6 (six) IGBTs per phase as compared to conventional 3–level inverter.
[0018] It is another object of the present disclosure to provide an improvised control scheme/strategy with more switching options, which enable higher power efficiency and lower IGBT off-state voltages compared to conventional 3–level inverter.
[0019] It is another object of the present disclosure to control overvoltage spikes of middle IGBT’s without usage of any external circuitry.

SUMMARY
[0020] The present disclosure relates to the field of power inverter. In particular, the present disclosure pertains to a three (3)-level high power inverter having six (6) IGBT’s per phase. An aspect of the present disclosure relates to a three-level inverter apparatus that includes at least six insulated-gate bipolar transistors (IGBTs), at least four of which IGBTs operate as main switches, and at least two of which IGBTs operate as auxiliary switches so as to attain equal voltage sharing between the main switches and the auxiliary switches.
[0021] In aspect, the proposed three-level inverter apparatus balances a direct current (DC) link capacitor voltage under normal operation. The auxiliary switches enable freedom in choosing a path for zero voltage state, wherein the main switches and the auxiliary switches help achieve one or more conduction/switching states. In an aspect, the one or more conduction/switching states are selected from any or combination of a positive conduction state, a negative conduction state, and a zero voltage state.
[0022] In an aspect, the proposed three-level inverter, in the zero voltage state, allows a zero voltage to split through two independent bidirectional paths.
[0023] In an aspect, the proposed three-level inverter enables selection of zero voltage state and one or more conduction/switching states, resulting in balanced switching losses.
[0024] In another aspect, the three-level inverter apparatus further comprises at least two DC linking capacitors that are connected in series.
[0025] Other features of embodiments of the present disclosure will be apparent from accompanying drawings and from detailed description that follows.

BRIEF DESCRIPTION OF DRAWINGS
[0026] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0027] In the figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label with a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
[0028] FIG. 1A illustrates a conventional 3-level diode inverter.
[0029] FIG. 1B illustrates control scheme using a conventional 3-level diode inverter.
[0030] FIG. 2A illustrates schematic diagram showing an improved design of a 3-level high power IGBT based inverter in accordance with an embodiment of the present disclosure.
[0031] FIG. 2B illustrates control scheme using the proposed improved 3-level diode inverter in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION
[0032] All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
[0033] In some embodiments, the numbers expressing quantities of ingredients, properties such as concentration, reaction conditions, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term “about.” Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
[0034] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0035] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0036] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all Markush groups used in the appended claims.
[0037] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims. Each of the appended claims defines a separate invention, which for infringement purposes is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, all references below to the "invention" may in some cases refer to certain specific embodiments only. In other cases it will be recognized that references to the "invention" will refer to subject matter recited in one or more, but not necessarily all, of the claims.
[0038] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0039] Embodiments of the present disclosure include various steps, which will be described below. The steps may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, steps may be performed by a combination of hardware, software, and firmware or by human operators.
[0040] Embodiments of the present disclosure may be provided as a computer program product, which may include a machine-readable storage medium tangibly embodying thereon instructions, which may be used to program a computer (or other electronic devices) to perform a process. The machine-readable medium may include, but is not limited to, fixed (hard) drives, magnetic tape, floppy diskettes, optical disks, compact disc read-only memories (CD-ROMs), and magneto-optical disks, semiconductor memories, such as ROMs, PROMs, random access memories (RAMs), programmable read-only memories (PROMs), erasable PROMs (EPROMs), electrically erasable PROMs (EEPROMs), flash memory, magnetic or optical cards, or other type of media/machine-readable medium suitable for storing electronic instructions (e.g., computer programming code, such as software or firmware).
[0041] Various methods described herein may be practiced by combining one or more machine-readable storage media containing the code according to the present disclosure with appropriate standard computer hardware to execute the code contained therein. An apparatus for practicing various embodiments of the present disclosure may involve one or more computers (or one or more processors within a single computer) and storage systems containing or having network access to computer program(s) coded in accordance with various methods described herein, and the method steps of the disclosure could be accomplished by modules, routines, subroutines, or subparts of a computer program product.
[0042] If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0043] All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0044] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be through and complete and will fully convey the scope of the disclosure to those of ordinary skill in the art. Moreover, all statements herein reciting embodiments of the disclosure, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future (i.e., any elements developed that perform the same function, regardless of structure).
[0045] The present disclosure relates to the field of power inverter. In particular, the present disclosure pertains to a three (3)-level high power inverter having six (6) IGBT’s per phase. An aspect of the present disclosure relates to a three-level inverter apparatus that includes at least six insulated-gate bipolar transistors (IGBTs), at least four of which IGBTs operate as main switches, and at least two of which IGBTs operate as auxiliary switches so as to attain equal voltage sharing between the main switches and the auxiliary switches.
[0046] In aspect, the proposed three-level inverter apparatus balances a direct current (DC) link capacitor voltage under normal operation. The auxiliary switches enable freedom in choosing a path for zero voltage state, wherein the main switches and the auxiliary switches help achieve one or more conduction/switching states. In an aspect, the one or more conduction/switching states are selected from any or combination of a positive conduction state, a negative conduction state, and a zero voltage state.
[0047] In an aspect, the proposed three-level inverter, in the zero voltage state, allows a zero voltage to split through two independent bidirectional paths.
[0048] In an aspect, the proposed three-level inverter enables selection of zero voltage state and one or more conduction/switching states, resulting in balanced switching losses.
[0049] In another aspect, the three-level inverter apparatus further comprises at least two DC linking capacitors that are connected in series.
[0050] FIG. 2A illustrates schematic diagram showing an improved design of a 3-level high power IGBT based inverter in accordance with an embodiment of the present disclosure. In an exemplary embodiment, each phase leg of a 3-level high power IGBT based inverter can be completed by replacement of two clamping diodes 120 and 122 (as shown in FIG. 1A) with two additional IGBTs 124 (Q5) and 126 (Q6) in addition to the remaining four IGBTs 112 (Q1), 114 (Q2), 116 (Q3), and 118 (Q4) as shown previously.
[0051] As shown in FIG. 2A, drain terminal 112a (also sometimes referred to as “collector terminal”) of a first IGBT 112 (Q1) is connected to a positive direct current bus 102, and source terminal 112b (also sometimes referred to as “emitter terminal”) of the first IGBT 112 is connected to a first connection point or node (not shown with reference numeral). In an aspect, the drain terminal 112a and the source terminal 112b of the first IGBT 112 can be bridge-connected to a first free-wheeling diode 112c.
[0052] Furthermore, drain terminal 114a of second IGBT 114 (Q2) is connected to the first connection point or node (not shown with reference numeral), and source terminal 114b of the second IGBT 114 (Q2) is connected to a second connection point or node (not shown with reference numeral), wherein the drain terminal 114a and the source terminal 114b of the second IGBT 114 (Q2) can be bridge-connected to a second free-wheeling diode 114c.
[0053] Similarly, drain terminal 116a of third IGBT 116 (Q3) is connected to the second connection point or node (not shown with reference numeral), and source terminal 116b of the third IGBT 116 (Q2) is connected to a third connection point or node (not shown with reference numeral), wherein the drain terminal 116a and the source terminal 116b of the third IGBT 116 (Q3) can be bridge-connected to a third free-wheeling diode 116c.
[0054] Furthermore, drain terminal 118a of fourth IGBT 118 (Q4) is connected to the third connection point or node (not shown with reference numeral), and source terminal 118b of the fourth IGBT 118 (Q4) is connected to a negative direct current bus, wherein the drain terminal 118a and the source terminal 118b of the fourth IGBT 118 (Q4) can be bridge-connected to a fourth free-wheeling diode 118c.
[0055] In an aspect, drain terminal 124a of fifth IGBT 124 (Q5) can be connected to the first connection point or node (not shown with reference numeral), and source terminal 124b of the fifth IGBT 124 (Q5) can be connected to a fifth connection point or node (not shown with reference numeral). On the other hand, drain terminal 126a of sixth IGBT 126 (Q6) can be connected to the second connection point or node (not shown with reference numeral), and source terminal 126b of the sixth IGBT 126 (Q6) can be connected to a third connection point or node (not shown with reference numeral).
[0056] With reference to any one of the above-possible implementations, in an exemplary implementation, the three-level inverter can further include a first capacitor 104 that can be connected between the positive direct current bus 102 and a neutral point 108, and a second capacitor 108 that can be connected between the negative direct current bus 110 and the neutral point 108.
[0057] In an aspect, switching sequence can be configured to produce (+Vdc/2), 0, (-Vdc/2) voltage levels. In an aspect, for zero voltage stage, there can be four redundant switching states with different current paths. In an aspect, the improved configuration can enable phase current to flow through upper path and lower path in both directions when a particular set of IGBTs are turned ON. In yet another aspect, neutral current only can flow through both the paths in zero voltage state. Even distribution of switching losses in the proposed 3-level inverter can be achieved by selecting upper or lower current paths.
[0058] In an exemplary aspect, the proposed design of 3-level inverter can result in equal turn ON time or conduction time for all the switches. The proposed 3-level inverter can also ensure equal switching of each semiconductor device, and accordingly help in balancing DC link capacitors by choosing proper switching sequence. In an exemplary aspect, the improved design of 3-level inverter can overcome unequal loss and distribution problems of conventional 3-level inverters with clamped diodes.
[0059] In an exemplary aspect, by adding two auxiliary switches/IGBTs instead of clamping diodes, equal voltage sharing between the main and auxiliary switches can be ensured. In another aspect, the proposed design can naturally balance DC link capacitor voltage under normal operation of inverter due to increased switching redundancy created by adding clamping switches instead of clamping diodes. By adding another two additional IGBTs 124 and 126, more freedom in choosing the path for zero voltage state can be provided and more switching states can be available.
[0060] In an aspect, two additional IGBTs 124 and 126 can also take up some losses from the regular transistors to achieve the desired conduction states. In an aspect, more than basic switching states can be defined for the improved 3-level inverter.
[0061] In an aspect, there can be two conduction states, namely positive conduction state and negative conduction state, and therefore zero state, in the present invention, can be achieved in two ways, whereas in the conventional diode clamped 3-level inverter, the zero state depends on current direction due to limitations of the clamped diodes. The proposed design, on the other hand, provides/enables two independent bidirectional paths for zero voltage and more than two switching states that can be used to balance losses among the semiconductors. Due to two independent bidirectional paths for zero voltage, DC link capacitor voltage imbalance can be considerably reduced, leading to minimization of distortion in the inverter output voltage and considerable reduction in middle IGBTs breakdowns.
[0062] FIG. 2B illustrates control scheme using the proposed improved 3-level diode inverter.
[0063] The foregoing descriptions are merely specific embodiments of the present application, but are not intended to limit the protection scope of the present application. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in the present application shall fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
[0064] The above are only exemplary embodiments of the present disclosure, and the present disclosure is therefore not limited to the above embodiments. There may be structural changes during actual implementation leading to modifications and variations, which would not depart from the present spirit and scope of the invention, and of the claims of the invention and equivalents within the technical scope of the present invention is also intended to include these changes and modifications •

ADVANTAGES OF THE INVENTION
[0065] The present disclosure provides a 3-level high power inverter that includes 6 IGBT’s per phase.
[0066] The present disclosure provides fault tolerant an improved 3-level inverter includes 6 (six) IGBTs per phase instead of the usual 4 (four) IGBT’s and 2 (two) diodes in case of a conventional 3–Level Inverter.
[0067] The present disclosure provides a new control strategy with more switching options, which enables higher power efficiency and lower IGBT off-state voltages compared to conventional 3–Level Inverter.
[0068] The present disclosure controls an overvoltage spikes of middle IGBT’s.
[0069] The present disclosure provides more freedom in choosing the path for zero voltage state.
[0070] The present disclosure provides one or more switching states.
,CLAIMS:
1. A three-level inverter apparatus comprising:
at least six insulated-gate bipolar transistors (IGBTs), four of which at least six IGBTs are operate as main switches, and two of which at least six IGBTs operate as auxiliary switches to attain equal voltage sharing between said main switches and said auxiliary switches.

2. The apparatus as claimed in claim 1, wherein said three-level inverter apparatus balances a direct current (DC) link capacitor voltage under normal operation.

3. The apparatus as claimed in claim 1, wherein said auxiliary switches provide freedom in choosing a path for zero voltage state.

4. The apparatus as claimed in claim 1, wherein said main switches and said auxiliary switches help achieve one or more conduction/switching states.

5. The apparatus as claimed in claim 4, wherein said one or more conduction/switching states are selected from any or a combination positive conduction state, negative conduction state, and zero voltage state.

6. The apparatus as claimed in claim 5, wherein said three-level inverter allows, during the zero voltage state, a zero voltage to pass through two independent bidirectional paths.

7. The apparatus as claimed in claim 1, wherein said three-level inverter enables selection of zero voltage state and selection of one or more conduction/switching states so as to result in balanced switching losses.

8. The apparatus as claimed in claim 1, wherein said apparatus further comprises at least two DC linking capacitors connected in series.

9. The apparatus as claimed in claim 1, wherein the apparatus comprises six IGBTs having four IGBTs operating as main switches, and two IGBTs operating as auxiliary switches.

10. An electrical device comprising a three-level inverter apparatus, said apparatus comprising at least six insulated-gate bipolar transistors (IGBTs), four of which at least six IGBTs are operate as main switches, and two of which at least six IGBTs operate as auxiliary switches to attain equal voltage sharing between said main switches and said auxiliary switches.