We Claim:
1. Time arbitration circuit comprising:
. a comparator comprising at least first and second inputs and configured to provide at least a first data item relative to the synchronization status of the signals present on the first and second inputs,
. a clock signal generator connected to an output terminal of the arbitration circuit and delivering an output clock signal,
. a control circuit configured to enable or disable delivery of the output clock signal on the output terminal according to the first data item from the comparator and/or to deliver data relative to the synchronization status according to the first data item,
. the first input of the comparator is connected to a first input terminal of the arbitration circuit designed to be connected to a first source delivering a first clock signal,
. the second input of the comparator is designed to be connected to a second source delivering a second clock signal.
2. Time arbitration circuit according to claim 1, wherein the clock signal generator is connected to the second input of the comparator.
3. Time arbitration circuit according to claim 1, wherein the second input of the comparator is connected to a second input terminal of the arbitration circuit designed to be connected to a second source delivering a second clock signal different from the clock signal generator.
4. Time arbitration circuit according to claim 3, wherein a third input of the comparator is connected to the clock signal generator and wherein the control circuit is configured to:

. synchronize the clock signal generator with one of the signals applied on the first and second inputs of the comparator when the comparator provides at least a first data item indicating synchronization of the signals present on the first and second inputs,
. preventing synchronization of the clock signal generator with one of the signals applied on the first and second inputs of the comparator when the comparator provides at least a first data item indicating non-synchronization of the signals present on the first and second inputs.
5. Time arbitration circuit according to claim 3, wherein a third input of
the comparator is connected to a third source delivering a third clock
signal, and wherein the control circuit is configured to:
. synchronize the clock signal generator with one of the signals applied on the first, second and third inputs of the comparator when the comparator provides at least a first data item indicating synchronization of the signals present on the first, second and third inputs,
. preventing synchronization of the clock signal generator with one of the signals applied on the first, second and third inputs of the comparator when the comparator provides at least a first data item indicating non-synchronization of the signals present on the first, second and third inputs.
6. Time arbitration circuit according to one of claims 4 and 5, wherein the third source is chosen from quartz oscillators and atomic micro-oscillators.
7. Time arbitration circuit according to one of claims 4 to 6, wherein the output clock signal generator is synchronized continuously with the first clock signal or the second clock signal when the time difference does not reach the threshold value.

8. Time arbitration circuit according to one of claims 4 to 6, wherein the output clock signal generator is synchronized at regular intervals with the first clock signal or the second clock signal when the time difference does not reach the threshold value.
9. Time arbitration circuit according to one of claims 4 to 6, wherein the output clock signal generator is synchronized at random intervals with the first clock signal or the second clock signal when the time difference does not reach the threshold value.
10. Time arbitration circuit according to any one of the foregoing claims, wherein the first data item is obtained by means of the time difference between the signals present on the first and second inputs.
11. Time arbitration circuit according to claim 10, wherein the comparator is configured to perform continuous measurement of said time difference.
12. Time arbitration circuit according to claims 4 and 10 or 5 and 10, wherein the first data item is obtained by means of the time difference between the signals present on the first and third inputs and/or the time difference between the signals present on the second and third inputs
13. Time arbitration circuit according to any one of the foregoing claims, wherein the control circuit is configured to stop delivery of the output clock signal if the time difference reaches the threshold value after a predefined time period initiated when the control circuit detects that the time difference has reached the threshold value.
14. Time arbitration circuit according to any one of the foregoing claims, wherein the first clock signal input is connected to a first processing circuit

comprising a processing oscillator, the processing circuit being configured to servo-control the processing oscillator to the signal received on input so that the first processing circuit delivers a clock signal representative of the signal applied on input for the comparator.
15. Time arbitration circuit according to any one of the foregoing claims, wherein the clock signal generator is a quartz oscillator or an atomic oscillator made from a rubidium or caesium base.
16. Time arbitration circuit according to any one of the foregoing claims, wherein the comparator is formed by a plurality of elementary comparators, the comparators being arranged to compare all the inputs of the comparator two by two.
17. Device for providing a clock signal comprising an arbitration device according to any one of claims 1 to 16 and wherein the first source is formed by one or more satellites, by a hard-wired connection or by a signal emitted by radio waves.