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Time Encoded Data Communication Protocol, Apparatus And Method For Generating And Receiving A Data Signal

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

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Notices, Deadlines & Correspondence

Patent Information

Application #
Filing Date
17 February 2020
Publication Number
12/2020
Publication Type
INA
Invention Field
COMMUNICATION
Status
Email
ipo@iphorizons.com
Parent Application
Patent Number
Legal Status
Grant Date
2023-08-24
Renewal Date

Applicants

INTEL CORPORATION
2200 Mission College Boulevard, Santa Clara, California, 95054

Inventors

1. BANIN, Elan
Brener 54A, Raanana 43606
2. MANN, Eytan
Hartzit 9/1, Modiin 71708
3. BANIN, Rotem
21 Hanotea St. P. O. B. 907, Even-Yehuda 4053221
4. GERNIZKY, Ronen
Chochit 3, Zichron Yaakov 3901662
5. DEGANI, Ofir
House 18, Nes-Ammin 228010
6. KUSHNIR, Igal
Aharonson Aharon 3, Hod-Hasharon 4502452
7. PORAT, Shahar
Ein Carmel P. O. B. 73, Hof Harcamel 0308600
8. RUBIN, Amir
8 Rabin Street, Kiryat Ono 5551013
9. VOLOKITIN, Vladimir
Apt. 32, Hazait 23 Nesher 3676014
10. KASHANI, Elinor
Apt. 58, 9th Rivka Gover St., Petach Tikva 4906444
11. FELSENSTEIN, Dmitry
Apt. 45, 16 Ha-Sne St., Ashkelon 7832519
12. ESHKOLI, Ayal
David Elazar 9, Kiryat Tivon 3655205
13. DAVIDSON, Tal
36 Hagiva St., Givat Ada 3780800
14. OOI, Eng Hun
10 Jalan Padang Victoria, Georgetown 10400
15. TSFATI, Yossi
22nd Lilach Street, Rishon Le Zion 7550780
16. SHIMON, Ran
Tel Hai 7, Ramat Gan 5233529

Specification

Claims
What is claimed is:
1. An apparatus for generating a data signal comprising:
a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted; and an output interface circuit configured to output the data signal.
2. The apparatus of claim 1, wherein the first type is a rising edge and the second type is a falling edge, or wherein the second type is a rising edge and the first type is a falling edge.
3. The apparatus of one of the preceding claims, wherein a sum of the first time period and the second time period is lower than 10"7s.
4. The apparatus of one of the preceding claims, wherein the processing circuit is further configured to generate a second data signal, the second data signal being inverted with respect tothe data signal.
5. The apparatus of one of the preceding claims, wherein the first data is represented by a first data symbol and the second data is represented by a second data symbol to be transmitted according to a data communication protocol.
6. The apparatus of one of the preceding claims, further comprising at least one Digital to Time converter configured to generate the data signal.
7. The apparatus of one of the preceding claims, wherein the output interface circuit is
configured to output the data signal to a wired transmission link composed of one or more
transmission lines.

8. Apparatus for receiving a data signal, comprising:
a processing circuit configured to determine a sequence of a first signal edge of a first type, a
second signal edge of a second type, and a third signal edge of the first type in the data signal;
and
a demodulation circuit configured to determine first data based on a first time period between
the first signal edge and the second signal edge; and second data based on a second time period
between the second signal edge and the third signal edge.
9. The apparatus of claim 8, wherein the first type is a rising edge and the second type is a
falling edge, or wherein the second type is a rising edge and the first type is a falling edge.
10. The apparatus of one of the claims 8 or 9, wherein a sum of the first time period and the second time period is lower than 10"7s or 10"8s.
11. The apparatus of one of claims 8 to 10, wherein the processing circuit is further configured to receive a second data signal, the second data signal being inverted with respect to the data signal; and to determine the first signal edge, the second signal edge, and the third signal edge further based on the second data signal.
12. The apparatus of one of claims 8 to 11, wherein a time period between 2 signal edges corresponds to a data symbol of a communication protocol.
13. The apparatus of one of the claims 8 to 12, further comprising at least one time to digital converter configured to determine the first time period and the second time period.
14. An apparatus for generating a data signal, comprising a processing circuit configured to generate the data signal, the data signal comprising alternating signal edges of a first type and of a second type, wherein the time periods between each subsequent pair of signal edges correspond to data to be transmitted, wherein a number of time periods per second is higher than l*107or 1*108.
15. The apparatus of claim 14, wherein a time period between two signal edges corresponds to a data symbol of a communication protocol.

16. The apparatus of one of the preceding claims, wherein the data signal is a digital signal transmitted using a wired transmission link.
17. Means for generating a data signal, comprising:
means for generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted; and means for outputting the data signal
18. The means of claim 17, wherein the first type is a rising edge and the second type is a falling edge, or the second type is a rising edge and the first type is a falling edge.
19. Means for receiving a data signal, comprising:
means for determining a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type in the data signal; and means for determining first data based on a first time period between the first signal edge and the second signal edge; and second data based on a second time period between the second signal edge and the third signal edge.
20. The means of claim 19, wherein the first type is a rising edge and the second type is a falling edge, or wherein the second type is a rising edge and the first type is a falling edge.
21. Means for generating a data signal, comprising means for generating the data signal, the data signal comprising alternating signal edges of a first type and of a second type, wherein the time periods between each subsequent pair of signal edges correspond to data to be transmitted, wherein a number of time periods per second is higher than 1*107 or 1*108.
22. An apparatus for generating a data signal, comprising a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to

first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted.
23. The apparatus of claim 22, further comprising an output interface for the data signal.
24. An apparatus for generating a data signal comprising a processing circuit configured to generate the data signal, wherein the processing circuit is configured to adjust time periods between directly succeeding signal edges of the data signal based on respective data portions to be transmitted.
25. The apparatus of claim 24, further comprising an output interface for the data signal.

Documents

Application Documents

# Name Date
1 202047006748.pdf 2020-02-17
2 202047006748-NOTIFICATION OF INT. APPLN. NO. & FILING DATE (PCT-RO-105) [17-02-2020(online)].pdf 2020-02-17
3 202047006748-FORM 1 [17-02-2020(online)].pdf 2020-02-17
4 202047006748-DRAWINGS [17-02-2020(online)].pdf 2020-02-17
5 202047006748-DECLARATION OF INVENTORSHIP (FORM 5) [17-02-2020(online)].pdf 2020-02-17
6 202047006748-COMPLETE SPECIFICATION [17-02-2020(online)].pdf 2020-02-17
7 202047006748 abstract.jpg 2020-02-19
8 202047006748-FORM-26 [10-03-2020(online)].pdf 2020-03-10
9 202047006748-FORM 18 [06-07-2020(online)].pdf 2020-07-06
10 202047006748-FORM 3 [18-08-2020(online)].pdf 2020-08-18
11 202047006748-FER.pdf 2021-10-18
12 202047006748-Information under section 8(2) [18-02-2022(online)].pdf 2022-02-18
13 202047006748-FORM 3 [18-02-2022(online)].pdf 2022-02-18
14 202047006748-OTHERS [09-03-2022(online)].pdf 2022-03-09
15 202047006748-FER_SER_REPLY [09-03-2022(online)].pdf 2022-03-09
16 202047006748-CLAIMS [09-03-2022(online)].pdf 2022-03-09
17 202047006748-Proof of Right [28-04-2022(online)].pdf 2022-04-28
18 202047006748-PatentCertificate24-08-2023.pdf 2023-08-24
19 202047006748-IntimationOfGrant24-08-2023.pdf 2023-08-24

Search Strategy

1 SearchHistoryE_03-09-2021.pdf

ERegister / Renewals

3rd: 13 Nov 2023

From 17/09/2020 - To 17/09/2021

4th: 13 Nov 2023

From 17/09/2021 - To 17/09/2022

5th: 13 Nov 2023

From 17/09/2022 - To 17/09/2023

6th: 13 Nov 2023

From 17/09/2023 - To 17/09/2024

7th: 27 Aug 2024

From 17/09/2024 - To 17/09/2025

8th: 20 Aug 2025

From 17/09/2025 - To 17/09/2026