A) TECHNICAL FIELD
[0001] The present invention generally relates to power converters and
particularly to a dead time control circuit in power converters such as electronic power converters. The present invention more particularly relates to bipolar junction transistor based dead time control circuit for reducing the dead time between conduction of high side and low side field effect switching transistors.
B) BACKGROUND OF THE INVENTION
[0002] Power switching devices, having a capacitive gate control input such
as MOSFETs, insulated gate bipolar transistors (IGBTs), and MOS-controlled thyristors (MCTs), are used in a multitude of electronic switching applications such as ON/OFF load controllers, power converters, switching amplifiers, motor drivers, switched mode power supplies (SMPSs), and cycloconverters for their superior performance at high switching frequencies. Such devices are turned on by charging the gate capacitance to some appropriate, relatively low voltage value and are turned off by discharging the gate capacitance. Information as to when the power switching device is to be turned on and off is delivered to a gate driver circuit which is designed to rapidly charge and discharge the gate capacitance of the power switching device as a means of turning the device on and off.
[0003] However, in circuits using high-side and low side MOS-gated devices,
such as motor controllers, the two MOS-gated devices cannot be on at the same time, because it creates a direct short circuit known as "shoot-through" condition. A common application involves using two MOS power transistors stacked in series between two power supply rails as the output stage of a switching regulator.

conventionally referred to as a "half-bridge" configuration. In a "shoot-through" condition, when both power switches are turned on at the same time, a low resistance path is created between the two power rails and a large current will flow through the two power switches. A shoot-through wastes power, can cause fluctuations in the power supply voltage, and/or can cause over-heating, which will damage the power switches.
[0004] Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is an
electronic device commonly used in switching and amplifying circuits. MOSFET switching is an efficient method used in electronic power converters. Necessary dead time shall be provided for the operations. Dead time is the time at which the high side and low side switches are held in off state. Discrete driver ICs are available and they can provide the necessary dead time. But the operating voltage range and the dead time duration are limited. In some cases, the dead time is controlled by utilizing the delay elements prior to the drivers, or by utilizing a circuitry to control the driver timing.
[0005] Another method used for controlling the dead time during the
switching off conditions of both the transistors involves providing Kelvin feedback connections directly across the drain and source of one or both of the transistors thereby bypassing signal line resistance and inductances.
[0006] But none of the currently available dead time control circuits are
suitable for operation in high voltage applications. Hence there is a need to control and vary the dead time of the switching transistors in high voltage applications. Also there is a need to vary the dead time using a simple circuit.

[0007] The above mentioned shortcomings, disadvantages and problems are
addressed herein and which will be understood by reading and studying the following specification.
C) OBJECT OF THE INVENTION
[0008] The primary object of the present invention is to develop a transistor
based dead time control circuit in power conversion systems thereby eliminating the need for a separate driver IC.
[0009] Another object of the present invention is to develop a transistor based
dead time control circuit in power conversion systems to adjust and vary the dead time dynamically.
[0010] Yet another object of the present invention is to develop a transistor
based dead time control circuit in power conversion systems at low cost.
[0011] Yet another object of the present invention is to develop a transistor
based dead time control circuit suitable for high voltage applications.
[0012] These and other objects and advantages of the present invention will
become readily apparent from the following detailed description taken in conjunction with the accompanying drawings.
D) SUMMARY OF THE INVENTION
[0013] The various embodiments of the present invention provide a transistor
based dead time control circuit in electronic power conversion systems.

[0014] According to one embodiment of the present invention, a transistor
based dead control system has a pulse width modulation controller. A drive transformer is cormected to the pulse width modulation controller. A first gate charging and discharging circuit is connected to the drive transformer. A second gate charging and discharging circuit is connected to the drive transformer. A first MOSFET is connected to the first gate charging and discharging circuit. A second MOSFET is connected to the second gate charging and discharging circuh. A first transistor is connected to the first MOSFET. A second transistor is cormected to the second MOSFET. A first base resistor is connected to the first transistor. A second base resistor is connected to the second transistor.
[0015] The discharging through the first MOSFET and the second MOSFET are
controlled respectively by controlling the current passing through the first transistor and the second transistor respectively. The current passing through the first transistor and the second transistor are controlled respectively by the first base resistor and the second base resistor.
[0016] The first gate charging and discharging circuit and the second gate
charging and discharging circuit are half bridge circuits. The first transistor and the second transistor are the bipolar junction transistors. The first transistor and the second transistor are the PNP transistors.
[0017] The first MOSFET is a high side MOSFET. The second MOSFET is a
low side MOSFET. A first diode is connected to the first MOSFET. A second diode is connected to the second MOSFET. A third resistance is cormected between the first diode and the first MOSFET. A fourth resistance is connected between the second diode and the second MOSFET. A first zener diode is cormected between the first transistor and the first MOSFET. A second zener diode is connected between the second transistor and the second MOSFET.

[0018] The gate capacitance of the first MOSFET is discharged through the first
transistor. The discharging time of the gate capacitance of the first MOSFET is controlled by adjusting the current through the first transistor using the first resistance to control the dead time. The gate capacitance of the second MOSFET is discharged through the second transistor. The discharging time of the gate capacitance of the second MOSFET is controlled by adjusting the current through the second transistor using the second resistance to control the dead time. The dead time is the dead time between the switching of the first MOSFET and the second MOSFET.
[0019] Electric pulses will be generated by a Pulse Width Modulation (PWM)
controller, with 50% duty cycle. This will be fed into the driver transformer which can drive the high side and low side MOSFETs. The dead time for the half bridge circuit is varied based on the natural ramping in the secondary inductor and gate capacitor of the MOSFET. An easy discharge path is provided to the gate capacitor through a transistor circuit. The discharging current is adjusted by varying the base resistance.
[0020] The present invention can be applied in all the high voltage switching
applications. This provides a cost effective solution for the high side MOSFET switching in the half bridge circuit. This will overcome the challenges in the voltage limitations in the present high side driver. This will eliminate the use of separate driver ICs for the dead time and high side switching.
E) BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The other objects, features and advantages will occur to those skilled
in the art from the following description of the preferred embodiment and the accompanying drawings in which:

[0022] FIG. 1 illustrates the block diagram of a transistor based dead time
control system, according to one embodiment of the present invention.
[0023] FIG.2 illustrates the block circuit diagram of a half bridge circuit used
in the transistor based dead time control system according to one embodiment of the present invention.
[0024] FIG.3 illustrates the block circuit diagram of a bipolar junction
transistor based dead time control system according to one embodiment of the present invention.
[0025] FIG.4 illustrates the output waveform of bipolar junction transistor
based dead time control system indicating the dead time between the switching of the high side and low side MOSFET, according to one embodiment of the present invention.
[0026] Although the specific features of the present invention are shown in
some drawings and not in others. This is done for convenience only as each feature may be combined with any or all of the other features in accordance with the present invention.
F) DETAILED DESCRIPTION OF THE INVENTION
[0027] In the following detailed description, reference is made to the
accompanying drawings that form a part hereof, and in which the specific embodiments that may be practiced is shown by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments and it is to be understood that the logical, mechanical and

other changes may be made without departing from the scope of the embodiments.
The following detailed description is therefore not to be taken in a limiting sense.
[0028] The various embodiments of the present invention provide a BJT
based dead time control circuit. Dead time is the time at which the high side and low side switches are held in off state.
[0029] According to one embodiment of the present invention, a transistor
based dead control system has a pulse width modulation controller. A drive transformer is connected to the pulse width modulation controller. A first gate charging and discharging circuit is connected to the drive transformer. A second gate charging and discharging circuit is connected to the drive transformer. A first MOSFET is connected to the first gate charging and discharging circuit. A second MOSFET is connected to the second gate charging and discharging circuit. A first transistor is connected to the first MOSFET. A second transistor is connected to the second MOSFET. A first base resistor is connected to the first transistor. A second base resistor is connected to the second transistor.
[0030] The discharging through the first MOSFET and the second MOSFET are
controlled respectively by controlling the current passing through the first transistor and the second transistor respectively. The current passing through the first transistor and the second transistor are controlled respectively by the first base resistor and the second base resistor.
[0031] The first gate charging and discharging circuit and the second gate
charging and discharging circuit are half bridge circuits. The first transistor and the second transistor are the bipolar junction transistors. The first transistor and the second transistor are the PNP transistors.

[0032] The first MOSFET is a high side MOSFET. The second MOSFET is a
low side MOSFET. A first diode is connected to the first MOSFET. A second diode is connected to the second MOSFET. A third resistance is connected between the first diode and the first MOSFET. A fourth resistance is connected between the second diode and the second MOSFET. A first zener diode is connected between the first transistor and the first MOSFET. A second zener diode is connected between the second transistor and the second MOSFET.
[0033] The gate capacitance of the first MOSFET is discharged through the first
transistor. The discharging time of the gate capacitance of the first MOSFET is controlled by adjusting the current through the first transistor using the first resistance to control the dead time. The gate capacitance of the second MOSFET is discharged through the second transistor. The discharging time of the gate capacitance of the second MOSFET is controlled by adjusting the current through the second transistor using the second resistance to control the dead time. The dead time is the dead time between the switching of the first MOSFET and the second MOSFET.
[0034] FIG. 1 illustrates the block diagram of a transistor based dead time
control system, according to one embodiment of the present invention. With respect to FlG.l, Electric pulses are generated by a Pulse Width Modulation (PWM) controller 11, with 50% duty cycle. This is fed to the driver transformer 12 which drives the high side 14 and low side 15 MOSFETs. The dead time for the half bridge circuit is set based on the natural ramping in the secondary inductor and gate capacitor of the MOSFET. An easy discharge path is provided to the gate capacitor 13 through a transistor circuit. The discharging current is adjusted by varying the base resistance.
[0035] FIG.2 illustrates the block circuit diagram of a half bridge circuit used
in the transistor based dead time control system according to one embodiment of the present invention. With respect to FIG.2, a gate control circuit 201 is connected to

high side MOSFET 104 and low side MOSFET 105. High side MOSFET 104 and low side MOSFET 105 are connected in series. An output terminal is connected to both the high side and low side MOSFETS 104,105.
[0036] FIG.3 illustrates the block circuit diagram of a bipolar junction
transistor based dead time control system according to one embodiment of the present invention. With respect to FIG.3, the high side and the low side circuits have symmetric operations. The high side and the low side gate capacitors (C4, C5) 315,316 represent the gate capacitances of the high side and the low side MOSFETs.
[0037] A PWM controller is connected to the primary of a transformer 304
through a capacitor 301. The other end of the primary is connected to a voltage source and to a ground respectively through the capacitors 302, 304. A high side gate capacitor 315 and a low side gate capacitor 316 are connected to the secondary of the transformer 304 through the different taps. The high side gate capacitance (C4) 315 and low side gate capacitance (C5) 316 are charged respectively through the diodes (Dl) 305 and (D2) 306 and the resistors (Rl) 307 and (R3) 308. The discharging of the high side gate capacitor (C4) 315 and low side gate capacitor (C5) 316 is done through the transistors (Ql) 311 and (Q2) 312 respectively. The transistor current is controlled with the base resistance i.e. the discharging time of the high side gate capacitance (C4) 315 and low side gate capacitance (C5) 316 is controlled by the base resistors (R2) 309 and (R3) 310. This provides the necessary range of dead time for the circuit operation. A zener diode 313 is connected between the transistor 311 and the high side gate capacitor 315. Another zener diode 314 is connected between the transistor 312 and the low side gate capacitor 316.
[0038] FIG.4 illustrates the output waveform of bipolar junction transistor
based dead time control system indicating the dead time between the switching of the high side and low side MOSFET, according to one embodiment of the present

invention. With respect to FIG.4, the high side MOSFET (Ql) 104 and low side MOSFET (Q2) 105 are turned on and turned off based on the gate pulses such as High side pulse 401, and Low side pulse 402. The dead time 403 between the high side 401 and low side 402 switching is provided by the said circuit
[0039] It is also to be understood that the following claims are intended to
cover all of the generic and specific features of the present invention described herein and all the statements of the scope of the invention which as a matter of language might be said to fall there between.
G) ADVANTAGES OF THE INVENTION
[0040] Thus the various embodiments of the present invention provide a
variable dead time control circuit for controlling the dead time in power converters. The dead time control circuit is used in all the high voltage switching applications. The system provides a cost effective solution for the high side MOSFET switching in the half bridge circuit. The variable dead time control circuit of the present invention overcomes the challenges in the voltage limitations in the present high side driver circuits. The system eliminates the use of separate driver ICs for the control of the dead time and high side switching operations.
[0041] Although the invention is described with various specific
embodiments, it will be obvious for a person skilled in the art to practice the invention with modifications. However, all such modifications are deemed to be within the scope of the claims.
[0042] It is also to be understood that the following claims are intended to
cover all of the generic and specific features of the present invention described herein

and all the statements of the scope of the invention which as a matter of language might be said to fall there between.

CLAIMS
What is claimed is:
1. A transistor based dead control system comprising:
A pulse width modulation controller;
A drive transformer connected to the pulse width modulation controller;
A first gate charging and discharging circuit connected to the drive transformer;
A second gate charging and discharging circuit connected to the drive
transformer;
A first MOSFET connected to the first gate charging and discharging circuit;
A second MOSFET connected to the second gate charging and discharging
circuit;
A first transistor connected to the first MOSFET;
A second transistor connected to the second MOSFET;
A first base resistor connected to the first transistor; and
A second base resistor connected to the second transistor.
2. The system according to claim 1, wherein the discharging through the first MOSFET and the second MOSFET are controlled respectively by controlling the current passing through the first transistor and the second transistor respectively.
3. The system according to claim 1, wherein the current passing through the first transistor and the second transistor are controlled respectively by the first base resistor and the second base resistor.
4. The system according to claim 1, wherein the first gate charging and discharging
circuit and the second gate charging and discharging circuit are half bridge
circuits.

5. The system according to claim 1, wherein the first transistor and the second transistor are the bipolar junction transistors.
6. The system according to claim 1, wherein the first transistor and the second transistor are the PNP transistors.
7. The system according to claim 1, wherein the first MOSFET is a high side
MOSFET.
8. The system according to claim 1, wherein the second MOSFET is a low side MOSFET.
9. The system according to claim 1, further comprising a first diode connected to the first MOSFET.
10. The system according to claim 1, further comprising a second diode connected to the second MOSFET.
11. The system according to claim 1, further comprising a third resistance connected between the first diode and the first MOSFET.
12. The system according to claim 1, further comprising a fourth resistance connected between the second diode and the second MOSFET.
13. The system according to claim 1, further comprising a first zener diode connected between the first transistor and the first MOSFET.
14. The system according to claim 1, further comprising a second zener diode
connected between the second transistor and the second MOSFET.

15. The system according to claim 1, wherein the gate capacitance of the first
MOSFET is discharged through the first transistor.
16. The system according to claim 1, wherein the discharging time of the gate
capacitance of the first MOSFET is controlled by adjusting the current through
the first transistor using the first resistance to control the dead time.
17. The system according to claim 1, wherein the gate capacitance of the second
MOSFET is discharged through the second transistor.
18. The system according to claim 1, wherein the discharging time of the gate
capacitance of the second MOSFET is controlled by adjusting the current
through the second transistor using the second resistance to control the dead
time.
19. The system according to claim 1, wherein the dead time is the time elapsed
between the switching of the first MOSFET and the second MOSFET.

To,
The Controller of Patents,
The Patent office, At Chennai