DESCRIPTION
[Title of Invention]
TRANSMISSION CIRCUIT, RECEPTION CIRCUIT, ITIANSMISSION
METHOD, RECEPTION METHOD, COMMUNICATION SYSTEM AND
5 COMMUNICATION METHOD THEREFOR
[Technical Field]
[0001]
The present invention relates to a transmitting circuit, a receiving circuit, a
transmission method, a reception method, a communication system, and a
10 communication method for the communication system for performing serial
transmission using channel coding to carry out communications, and, in particular,
to technology for achieving early establishment of synchronization and reduction of
coding loss.
[Background Art]
15 [0002]
With recent development in technology for miniaturizing semiconductor
devices and accelerating the processing speed thereof, the amount of data
communicated between devices or LSIs (Large Scale Integrations) provided in the
devices is increasing more than ever. With increasing amount of communicated data,
20 it is desirable that the number of terminals (pads) required for data communications
also increase. Nevertheless, a strict restriction is still posed on the number of
termmals in an LSI, which affects the costs. For the purpose of achieving high-speed
data communications with a fewer number of terminals in an LSI, the interface
standards employing serial transmission have widely prevailed.
25 [0003]
In the serial transmission scheme, it is common to superimpose information
regarding clock edges onto serial data. It is therefore necessary to limit a run-length
indicated by the number of consecutive bits each having a value of either "0" or "1".
1
In this scheme, it is also desirable that transmission be perfonned with good DC
balance, i.e. frequency of values "0" and " 1 " within a predetermined time period. In
order to limit the run-length and maintain the DC balance, channel coding is used in
the serial transmission.
5 [0004]
One example of the chaimel coding is symbol mapping in which an m-bit
data character is mapped to an n-bit (m < n) encoded symbol. Another example of
the channel coding is scrambling in which a bit pattern of a data character of
consecutive m bits is randomized to generate an encoded block.
10 [0005]
Patent Literature 1 discloses 8B/10B coding as an example of the sjmibol
mapping. Non-Patent Literature 1 discloses 64B/66B coding as an example of the
scrambling.
[0006]
15 Patent Literature 2 discloses technology for switching between the symbol
mapping and the scrambling after error detection/correction bits are added using the
scrambling so that a word length in coding in the scrambling matches that in the
symbol mapping.
[Citation List]
20 [Patent Literature]
[0007]
[Patent Literature 1]
US Patent No. 4,486,739
[Patent Literature 2]
25 WO2008/059588
[Non-Patent Literature]
[0008]
[Nfon-Patent Literature 1]
2
IEEE Std 802.3-2008, "PartS: Carrier Sense Multiple Access with Collision
Detection (CSMA/CD) access method and Physical Layer specifications", Clause 49
[Summary of Invention]
[Technical Problem]
5 [0009]
The symbol mapping takes advantage of redundancy provided by extending
m bits to n bits. For example, a COM (comma) symbol (K28.5) is defined in the
8B/10B coding. This means that, in the symbol mapping, a delimiter symbol having
a unique bit pattern in serial data can be defined. In the symbol mapping, detection
10 of a first bit of the encoded symbol within the serial data is facilitated by the
presence of the delimiter symbol. That is to say, the symbol mapping has an
advantage that symbol synchronization for performing serial-to-parallel conversion
at a precise timing is achieved with ease and speed by the presence of the delimiter
symbol. The symbol mapping, however, has a disadvantage that coding efficiency is
15 low and data transfer efficiency is thus reduced, as a single data character is mapped
to an encoded symbol by taking the run-length and the DC balance into
consideration.
[0010]
On the other hand, in the scrambling, a plurality of data characters are
20 brought together, and a synchronization header that is shorter than a data length of a
data character to be transmitted is added thereto. Therefore, it can be said that the
coding efficiency of the scrambling is higher than that of the symbol mapping. For
example, in the 8B/10B coding as an example of the symbol mapping, the number of
redundant bits is two for each eight-bit data character, resulting in coding loss of
25 25% (2/8). On the other hand, in the 64B/66B coding as an example of the
scrambling, the number of redundant bits is only two for each 64-bit data character,
resulting in coding loss of only approximately 3% (64/66). In the scrambling,
however, data characters are randomized by scrambling, and a unique bit pattern
3
cannot be defined within serial data. The scrambling thus takes more time in
establishing symbol synchronization (block synchronization) than the symbol
mapping. For example, in the 64B/66B coding, a two-bit synchronization header is
defined as "01" or "10". In order to establish symbol synchronization (block
5 synchronization) in the scrambling, it is necessary to detect synchronization headers
cyclically embedded for every 66 bits within serial data, for 64 or more blocks in
succession. Accordingly, considering cases where symbol synchronization fails due
to a transmission error and the like and where transmission is stopped in an idle
period to save power, overheads required to restore symbol synchronization (block
10 synchronization) increase in the scrambling. That is to say, the scrambling has such a
problem that data transmission performance is significantly reduced.
[0011]
The present invention has been conceived in view of the above-mentioned
problem, and aims to achieve early establishment of symbol synchronization while
15 suppressing reduction of data transmission efficiency occurring due to reduction of
coding efficiency.
[Solution to Problem]
[0012]
In order to solve the above-mentioned problem, a transmitting circuit
20 according to the present invention is a transmitting circuit that performs channel
coding and transmits channel-coded serial data to a receiving circuit via a serial
channel, comprising: a first encoding circuit configured to perform first channel
coding in which an m-bit control character is mapped to an n-bit (m < n) encoded
symbol; a second encoding circuit configured to perform second channel coding in
25 which a bit pattern of a data character is randomized by scrambling to generate an
encoded block, the second channel coding taking more time in establishing
synchronization with the receiving circuit and having less coding loss than the first
channel coding; a transmission control unit configured to select one of the first
4
encoding circuit and the second encoding circuit to be used for transmission; and a
serial driver configured to, when the transmission control unit selects the first
encoding circuit, convert the encoded symbol generated by the first encoding circuit
into serial data and transmit the serial data via the serial channel, and to, when the
5 transmission control unit selects the second encoding circuit, convert the encoded
block generated by the second encoding circuit into serial data and transmit the
serial data via the serial channel, wherein the transmission control unit selects the
first encoding circuit in a period for not transmitting the data character, and selects
the second encoding circuit in a period for transmitting the data character.
10 [0013]
A receiving circuit according to the present invention is a receiving circuit
that receives channel-coded serial data from a transmitting circuit via a serial
charmel, the channel-coded serial data being obtained by either first charmel coding
in which an m-bit control character is mapped to an n-bit (m < n) encoded symbol or
15 second channel coding in which a bit pattern of a data character is randomized by
scrambling to generate an encoded block, the second channel coding taking more
time in establishing synchronization and having less coding loss than the first
channel coding, the receiving circuit comprising: a first decoding circuit configured
to decode the encoded symbol into the control character; a second decoding circuit
20 configured to decode the encoded block into the data character by descrambling; a
reception control unit configured to select one of the first decoding circuit and the
second decoding circuit to be used for reception; and a serial receiver configured to
convert the channel-coded serial data received via the serial charmel into parallel
data, and output the parallel data to one of the first decoding circuit and the second
25 decoding circuit selected by the reception control unit, wherein the reception control
unit selects the first decoding circuit in a period for not receiving the encoded block,
and selects the second decoding circuit in a period for receiving the encoded block.
[0014]
5
A communication system according to the present invention is a
communication system that transmits chaimel-coded serial data from a transmitting
circuit to a receiving circuit via a serial channel, wherein the transmitting circuit
includes: a first encoding circuit configured to perform first channel coding in which
5 an m-bit control character is mapped to an n-bit (m < n) encoded symbol; a second
encoding circuit configured to perform second channel coding in which a bit pattern
of a data character is randomized by scrambling to generate an encoded block, the
second channel coding taking more time in establishing synchronization with the
receiving circuit and having less coding loss than the first channel coding; a
10 transmission control unit configured to select one of the first encoding circuit and
the second encoding circuit to be used for transmission; and a serial driver
configured to, when the transmission control unit selects the first encoding circuit,
convert the encoded symbol generated by the first encoding circuit into serial data
and transmit the serial data via the serial channel, and to, when the transmission
15 control unit selects the second encoding circuit, convert the encoded block generated
by the second encoding circuit into serial data and transmit the serial data via the
serial channel, the transmission control unit selects the first encoding circuit in a
period for not transmitting the data character, and selects the second encoding circuit
in a period for transmitting the data character, the receiving circuit includes: a first
20 decoding circuit configured to decode the encoded symbol into the control character;
a second decoding circuit configured to decode the encoded block into the data
character by descrambling; a reception control unit configured to select one of the
first decoding circuit and the second decoding circuit to be used for reception; and a
serial receiver configured to convert the channel-coded serial data received via the
25 serial channel into parallel data, and output the parallel data to one of the first
decoding circuit and the second decoding circuit selected by the reception control
unit, and the reception control unit selects the first decoding circuit in a period for
not receiving the encoded block, and selects the second decoding circuit in a period
6
for receiving the encoded block.
[0015]
A communication method according to the present invention is a
communication method for use in a communication system that transmits
5 channel-coded serial data from a transmitting circuit to a receiving circuit via a serial
channel, wherein channel coding includes: first chaimel coding in which an m-bit
control character is mapped to an n-bit (m < n) encoded symbol; and second channel
coding in which a bit pattern of a data character is randomized by scramblmg to
generate an encoded block, the second channel coding takes more time in
10 establishing synchronization between the transmitting circuit and the receiving
circuit, and has less coding loss than the first channel coding, and the
communication method for use in the communication system transmits the
channel-coded serial data while switching between the first channel coding and the
second channel coding, and uses the first channel coding in a period for not
15 transmitting the encoded block, and uses the second channel coding in a period for
transmitting the encoded block.
[0016]
A transmission method according to the present invention is a transmission
method for use in a transmitting circuit that performs channel coding and transmits
20 channel-coded serial data to a receiving circuit via a serial channel, the transmission
method comprising: a first encoding step of performing first cheirmel coding in
which an m-bit control character is mapped to an n-bit (m < n) encoded symbol; a
second encoding step of performing second channel coding in which a bit pattern of
a data character is randomized by scrambling tp generate an encoded block, the
25 second channel coding taking more time in establishing synchronization with the
receiving circuit and having less coding loss than the first channel coding; a
transmission control step of controlling transmission by selecting one of the first
channel coding and the second channel coding to be used for transmission; and a
7
transmission step of converting, when the transmission control step selects the first
channel coding, the encoded symbol generated by the first encoding step into serial
data and transmitting the serial data via the serial channel, and converting, when the
transmission control step selects the second channel coding, the encoded block
5 generated by the second encoding step into serial data and transmitting the serial
data via the serial channel, wherein the transmission control step selects the first
channel coding in a period for not transmitting the data character, and selects the
second channel coding in a period for transmitting the data character.
[0017]
10 A reception method according to the present invention is a reception method
for use in a receiving circuit that receives channel-coded serial data from a
transmitting circuit via a serial channel, the channel-coded serial data being obtained
by either first channel coding in which an m-bit control character is mapped to an
n-bit (m < n) encoded symbol or second channel coding in which a bit pattern of a
15 data character is randomized by scrambling to generate an encoded block, the
second channel coding taking more time in establishing synchronization and having
less coding loss than the first channel coding, the reception method comprising: a
first decoding step, by a first decoding circuit included in the receiving circuit, of
decoding the encoded symbol into the control character; a second decoding step, by
20 a second decoding circuit included in the receiving circuit, of decoding the encoded
block into the data character by descrambling; a reception control step of selecting
one of the first decoding circuit and the second decoding circuit to be used for
reception; and an output step of converting the channel-coded serial data received
via the serial channel into parallel data, and output the parallel data to one of the first
25 decoding circuit and the second decoding circuit selected by the reception control
step, wherein the reception control step selects the first decoding circuit in a period
for not receiving the encoded block, and selects the second decoding circuit in a
period for receiving the encoded block.
8
[Advantageous Effects of Invention]
[0018]
The present invention achieves early establishment of symbol
synchronization while suppressing reduction of data transfer efficiency occurring
5 due to reduction of coding efficiency.
[Brief Description of Drawings]
[0019]
FIG. 1 is a block diagram illustrating an example of the overall structure of a
communication system according to an embodiment.
10 FIG. 2 is a block diagram illustrating an example of the detailed structure of
a transmitting circuit in the communication system according to the embodiment.
FIG. 3 is a block diagram illustrating an example of the detailed structure of
a receiving circuit in the communication system according to the embodiment.
FIG. 4A and 4B respectively illustrate examples of the structures of a
15 scrambler and a descrambler in the communication system according to the
embodiment.
FIG. 5 is a table showing allocation of functions to special symbols in
8B/1 OB coding.
FIG. 6 shows an example of a symbol set for control used in the
20 communication system according to the embodiment.
FIG. 7 is a timing diagram illustrating an example of an operation of the
communication system according to the embodiment.
FIG. 8 is a timing diagram illustrating a restoration operation from a
power-saving state of a communication system according to a first modification.
25 FIG. 9 is a timing diagram illustrating a transition operation to the
power-saving state of the communication system according to the first modification.
FIG. 10 is a block diagram illustrating an example of the detailed structure
of a transmitting circuit in a communication system according to a second
9
modification.
FIG. 11 is a block diagram illustrating an example of the detailed structure
of a receiving circuit in the communication system according to the second
modification.
5 FIG. 12 is a timing diagram illustrating an example of an operation of the
communication system according to the second modification.
FIG. 13 is a block diagram illustrating an example of the detailed structure
of a transmitting circuit in a commimication system according to a third
modification.
10 FIG. 14 is a block diagram illustrating an example of the detailed structure
of a receiving circuit in the communication system according to the third
modification.
FIGs. 15A to 15D each illustrate an example of the structure of a coding
frame used by the communication system according to the third modification.
15 FIG. 16 is a timing diagram illustrating an example of an operation before
the start of data transmission of the communication system according to the third
modification.
FIG. 17 is a timing diagram illustrating an example of a transition operation
to an idle period of the communication system according to the third modification.
20 [Description of Embodiments]
[0020]

TTie following describes a communication system as an embodiment of the
present invention with reference to the drawings.
25 [0021]
FIG. 1 is a block diagram illustrating an example of the structure of the
communication system.
[0022]
10
As illustrated in FIG. 1, the communication system includes a host device
100 and a target device 110. The host device 100 and the target device 110 are
connected to each other via serial channels 121 and 122.
[0023]
5 Each of the serial channels 121 and 122 is a pair of signal lines used for data
transmission in differential signaling. The serial channel 121 includes signal lines
D0+ and DO-, and is used to perform data transmission from the host device 100 to
the target device 110. Similarly, the serial charmel 122 includes signal lines D1+ and
D1-, and is used to perform data transmission from the target device 110 to the host
10 device 100. In a case where a differential signal is transmitted, antiphase signals
relative to signals passing though the signal lines D0+ and D1+ pass through the
respective signal lines DO- and Dl- in principle.
[0024]
The host device 100 includes a data processing unit 101, an interface circuit
15 102, a D0+ terminal 106, a DO- terminal 107, a D1+ terminal 108, and a Dlterminal
109.
[0025]
The data processing unh 101 performs data processing in data transmission
using the interface circuit 102. For example, the data processing unit 101 designates
20 data to be transmitted and transmits the designated data to the interface circuit 102,
or performs processing of data fransmitted from the interface circuit 102.
[0026]
The interface circuit 102 includes a fransmitting circuit 103, a PLL (Phase
Locked Loop) 104, and a receiving circuit 105.
25 [0027]
In an idle period for not transmitting actual data (also referred to as valid
data or a packet payload) to the target device 110, the transmitting circuit 103
performs 8B/10B coding to transmit a confrol signal and the like to the target device
11
no. On the other hand, in a period for transmitting actual data received from the
data processing unit 101 to the target device 110, the transmitting circuit 103
performs scrambling to transmit actual data to the target device 110. The detailed
structure of the transmitting circuit 103 is described later with use of FIG. 2.
5 [0028]
The PLL 104 generates a clock used for the interface circuit 102 to perform
data transmission.
[0029]
The receiving circuit 105 receives, via the D1+ terminal 108 and the Dl-
10 terminal 109, a differential signal transmitted from the target device 110 to the serial
channel 122, and decodes a control signal or actual data. The receiving circuit 105
receives a control signal encoded using the 8B/10B coding, and decodes the
received control signal using the 8B/10B coding. In a period for receiving actual
data, the receiving circuit 105 switches the coding scheme to the scrambling to
15 decode the received actual data.
[0030]
The target device 110 includes a back-end unit HI, an interface circuit 112,
a D0+ terminal 116, a DO- terminal 117, a D1+ terminal 118, and a Dl- terminal
119.
20 [0031]
The back-end unit 111 performs data processing in data transmission using
the interface circuit 112. The back-end unit 111 reads, from a recording medium (not
illustrated), data to be transmitted and outputs the read data to the interface circuit
112, or writes data output from the interface circuit 112 into the recording medium.
25 [0032]
The interface circuit 112 includes a receiving circuit 113, a PLL 114, and a
transmitting circuit 115.
[0033]
12
The receiving circuit 113 receives, via the D0+ terminal 116 and the DOterminal
117, a differential signal transmitted from the host device 100 to the serial
channel 121, and performs decoding. The receiving circuit 113 receives a control
signal encoded using the 8B/10B coding, and decodes the received control signal
5 using the 8B/10B coding. In the period for receiving actual data, the receiving
circuit 113 switches the coding scheme to the scrambling to decode the received
actual data. Details of the receiving circuit 113 are described later with use of FIG. 3.
[0034]
The PLL 114 generates a clock used for the interface circuit 112 to perform
10 data transmission.
[0035]
The transmitting circuit 115 transmits, by an instruction from the back-end
unit 111, the control signal and the like encoded using the 8B/10B coding to the host
device 100 in the idle period for not fransmitting actual data (a packet payload) to
15 the host device 100. The fransmitting circuit 115 transmits, using a differential signal,
the control signal and the like encoded using the 8B/10B coding to the host device
100 via the DH- terminal 118 and the Dl- terminal 119. On the other hand, when
fransmitting the actual data received from the back-end unit 111 to the host device
100, the transmitting circuit 115 encodes the actual data using the scrambling, and
20 transmits the encoded actual data to the host device 100. The transmitting circuit 115
fransmits, using a differential signal, the actual data encoded using the scrambling to
the host device 100 via the D1+ terminal 118 and the Dl- terminal 119.
[0036]
FIG. 2 illustrates an example of the detailed structure of the fransmitting
25 circuit 103 included in the host device 100. The following describes the fransmitting
circuit 103 with use of FIG. 2. The fransmitting circuit 115 included in the target
device 110 has a similar structure to the transmitting circuit 103 except that
fransmission data is input not from the data processing vmit 101 but from the
13
back-end unit 111, and a tenninal to which the transmission data is output is
different. Description on an example of the detailed structure of the transmitting
circuit 115 is thus omitted.
[0037]
5 As illustrated in FIG. 2, the transmitting circuit 103 includes a first encoding
circuit 201, a second encoding circuit 202, a transmission control unit 203, and a
serial driver 204.
[0038]
The first encoding circuit 201 maps an eight-bit control character (TXC: TX
10 Control character) input fi"om the transmission control unit 203 to a 10-bit encoded
symbol. Furthermore, the first encoding circuit 201 outputs the 10-bit encoded
symbol generated as a result of the mapping to the serial driver 204.
[0039]
The second encoding circuit 202 receives, as input, a data character (TXD:
15 TX Data character) of consecutive eight bits fi"om the transmission control unit 203.
The second encoding circuit 202 scrambles the input data character (TXD: TX Data
character) of consecutive eight bits into an eight-bit encoded block according to a
predetermined scrambling polynomial. Furthermore, the second encoding circuit 202
outputs the generated eight-bit encoded block to the serial driver 204.
20 [0040]
In the idle period during which there is no transmission request via a
transmission bus (TBUS), the transmission control unit 203 selects the first encoding
circuit 201 by setting a transmission selection signal (TSEL) to Low. As used herein,
the phrase "the transmission control unit 203 selects the first encoding circuit 201"
25 means that the transmission control unit 203 causes a serializer (SER: Serializer)
205 to process the encoded symbol output fi-om the first encoding circuit 201.
[0041]
In order to transmit the encoded symbol in the idle period, the transmission
14
control unit 203 outputs the eight-bit control character (TXC) to the first encoding
circuit 201. The transmission control unit 203 uses, as the encoded symbol having
been encoded using the 8B/10B coding, a D symbol and a K symbol in combination
with each other. The D symbol indicates a normal data byte, whereas the K symbol
5 is a symbol for control. In this case, the transmission control unit 203 also outputs a
one-bit encoding mode (TXM: TX coding Mode) for identifying one of the D
symbol and the K symbol into which a character is encoded.
[0042]
When there is a transmission request via the transmission bus (TBUS), the
10 transmission control unit 203 switches the encoding circuit to the second encoding
circuit 202 by setting the transmission selection signal (TSEL) to High upon output
of an encoded symbol indicating a start position of a packet (SOP: Start Of Packet).
The transmission control unit 203 then outputs transmission data (packet payload)
transmitted via the transmission bus (TBUS) to the second encoding circuit 202 as
15 the eight-bit data character (TXD). The transmission control unit 203 switches the
encoding circuit to the first encoding circuit 201 by setting the transmission
selection signal (TSEL) to Low again upon transmission of an encoded block
terminating the packet payload. The transmission control unit 203 completes packet
transmission by transmitting an encoded symbol indicating an end position of the
20 packet.
[0043]
The transmission control unit 203 stores therein a predetermined packet size
(e.g. 512 bytes) as a data size of a packet of valid data to be transmitted to the
receiving circuit 113. Upon transmission of a packet of the above-mentioned data
25 size, the transmission control unit 203 switches fi-om the second encoding circuit
202 to the first encoding circuit 201. That is to say, the transmission control unit 203
switches the transmission selection signal (TSEL) fi-om High to Low. When there is
any residual valid data transmitted via the transmission bus (TBUS), the
15
transmission control unit 203 transmits the SOP again, and then switches from the
first encoding circuit 201 to the second encoding circuit 202 to perform data
transmission.
[0044]
5 The serial driver 204 converts parallel data into serial data, and outputs the
serial data via the serial channel 121. The serial driver 204 includes the SER 205 and
a differential driver 206.
[0045]
The SER 205 selects one of a signal output from the first encoding circuit
10 201 and a signal output from the second encoding circuit 202 according to an
instruction indicated by the transmission selection signal (TSEL) transmitted from
the transmission control unit 203. Furthermore, the SER 205 converts the encoded
symbol or the encoded block input thereto into serial data, and transmits the serial
data to the differential driver 206. Specifically, the SER 205 selects a signal output
15 from the first encoding circuit 201 when the fransmission selection signal (TSEL)
indicates Low and selects a signal output from the second encoding circuit 202 when
the transmission selection signal (TSEL) indicates High.
[0046]
The differential driver 206 converts the serial data output from the SER 205
20 into a differential signal, and outputs the differential signal to the serial channel 121
via the D0+ terminal 106 and the DO- terminal 107.
[0047]
The differential driver 206 can generally include an analog circuit operated
by a constant current source. The differential driver 206 thus consumes power even
25 in the idle period for not transmitting valid data. For this reason, the transmission
control unit 203 also has a fiinction to confrol an enable signal (TXEN) for the serial
driver 204 so that a transmission operation is stopped in the idle period. When the
transmission operation is stopped by setting the enable signal (TXEN) to Low, the
16
differential driver 206 pulls up or down potentials on both signal lines constituting
the serial channel 121 to set differential amplitude, which is a difference between
potentials of signals flowing through the both signal lines, to 0 V. The differential
driver 206 may pull down the potentials by fixing an output potential of the
5 differential driver 206 at a ground level, for example. Ahematively, the differential
driver 206 may pull down the potentials by being put into a high impedance state
and fixing the output potential of the differential driver 206 at a ground level by
using a separate pull-down resistor. Furthermore, a pull-up resistor may include an
on-chip resistor formed from a transistor within a semiconductor chip.
10 [0048]
FIG. 3 illustrates an example of the detailed structure of the receiving circuit
113. The following describes the receiving circuit 113 with use of FIG. 3. Note that
the receiving cu"cuit 105 has a similar structure to the receiving circuit 113 except
that reception data has been output not from the data processing unit 101 but from
15 the back-end unit 111, and a terminal receiving the reception data is different.
Description on an example of the detailed structure of the receiving circuit 105 is
thus omitted.
[0049]
As illustrated in FIG. 3, the receiving circuit 113 includes a serial receiver
20 301, a first decoding circuit 302, a second decoding circuit 303, and a reception
control unit 304.
[0050]
The serial receiver 301 converts serial data received via the serial channel
121 into parallel data, and outputs the parallel data to the first decoding circuit 302
25 or the second decoding circuit 303.
[0051]
The serial receiver 301 includes a differential receiver 305 and a
de-serializer (DES: DE-Serializer) 306.
17
[0052]
The differential receiver 305 outputs, as serial data, a differential signal
received via the serial channel 121 to the de-serializer 306.
[0053]
5 The de-serializer 306 converts the serial data input thereto into parallel data,
and outputs the parallel data to the first decoding circuit 302 or the second decoding
circuit 303 according to a reception selection signal (RSEL) output from the
reception control unit 304. Specifically, the de-serializer 306 outputs the parallel
data as a 10-bit encoded symbol to the first decoding circuit 302 when the reception
10 selection signal (RSEL) is Low. The de-serializer 306 outputs the parallel data as an
eight-bit encoded block to the second decoding circuit 303 when the reception
selection signal (RSEL) is High.
[0054]
The first decoding circuit 302 receives, as input, the 10-bit encoded symbol
15 from the serial receiver 301. The first decoding circuit 302 further decodes the 10-bit
encoded symbol input thereto into an eight-bit control character (RXC: RX Control
character) according to the 8B/10B coding. In this case, the first decoding circuit
302 passes, to the reception control unit 304, a decoding mode (RXM: RX coding
Mode) indicating whether the decoded encoded symbol is a K symbol or a D
20 symbol.
[0055]
The second decoding circuit 303 receives, as input, an eight-bit encoded
block having been scrambled using the second channel coding from the serial
receiver 301. The second decoding circuit 303 fiirther decodes the eight-bit encoded
25 block input thereto into an eight-bit data character (RXD: RX Data character) by
descrambling.
[0056]
The reception control unit 304 has a function to switch between the first
18
decoding circuit 302 and the second decoding circuit 303, and a function to receive
the data character having been decoded by the second decoding circuit 303 and
output the received data character via a reception bus (RBUS).
[0057]
5 At initialization and restoration from a power-saving state, the reception
control unit 304 sets the reception selection signal (RSEL) to Low to select the first
decoding circuit 302 until symbol synchronization is established. After symbol
synchronization is established, the reception control unit 304 continues selecting the
first decoding circuit 302 by setting the reception selection signal (RSEL) to Low, as
10 long as an encoded symbol indicating the idle period is received.
[0058]
Upon reception of an encoded symbol indicating a start position of a packet,
the reception control unit 304 sets the reception selection signal (RSEL) to High to
switch the decoding circuit to the second decoding circuit 303. Upon reception of an
15 encoded block of a predetermined size terminating a packet payload, the reception
control unit 304 sets the reception selection signal (RSEL) to Low to switch the
decoding circuit to the first decoding circuit 302. The reception control unit 304
completes packet reception upon reception of an encoded symbol indicating an end
position of a packet.
20 [0059]
The reception control unit 304 also stores therein information on a
predetermined packet size (e.g. 512 bytes) as a packet size of valid data transmitted
from the transmitting circuit 103. Upon reception of a packet of the predetermined
packet size after the second decoding circuit 303 is selected, the reception control
25 unit 304 switches the decoding circuit to the first decoding circuit 302. In the present
embodiment, each of the transmitting circuit 103 and the receiving circuit 113 stores
therein a transmission size (the predetermined packet size) of valid data. With this
structure, in the present embodiment, valid data is accurately transmitted from the
19
transmitting circuit 103 to the receiving circuit 113, and the receiving circuit 113
appropriately switches from the second decoding circuit 303 to the first decoding
circuit 302.
[0060]
5 A detection circuit 307 obtains differential amplitude from potentials on
both signal lines constituting the serial channel 121, and, when the detected signal is
a Low fixed signal or a High fixed signal, notifies the reception confrol unit 304
accordingly. The notification from the detection circuit 307 triggers transition to the
power-saving state or restoration from the power-saving state. Details thereof,
10 however, are described later in a first modification.
[0061]
FIG. 4A illustrates the structure of a scrambler used for the scrambling
performed by the second encoding circuit 202, and FIG. 4B illustrates the structure
of a descrambler used for the descrambling performed by the second decoding
15 circuit 303.
[0062]
FIG. 4A illustrates the structure of the scrambler when a generating
polynomial is represented by X'40 + X'38 + X*21 + X"19 + 1. The scrambler
illustrated in FIG. 4A is one example of the structure of the second encoding circuit
20 202.
[0063]
FIG. 4B illustrates a descrambler corresponding to the scrambler illusfrated
in FIG. 4A. FIG. 4B illustrates the structure of the descrambler when the generating
polynomial is represented by X''40 + X'38 + X'21 + X'19 + 1. The descrambler
25 illustrated in FIG. 4B is one example of the structure of the second decoding circuit
303.
[0064]
The scrambler in FIG. 4A and the descrambler in FIG. 4B are respectively a
20
self-synchronizing scrambler and a self-synchronizing descrambler each initialized
by input data. The scrambler and the descrambler are each embodied by a linear
feedback shift register.
[0065]
5 In FIGs. 4A and 4B, SO to S39 and DO to D39 each represent a shift register,
eind a plus sign "+" represents bitwise exclusive or. In FIGs. 4A and 4B, each shift
register is required to shift by synchronization with a serial clock (SCLK: Serial
Clock). Processing equivalent to that illustrated in each of FIGs. 4A and 4B,
however, may be performed in parallel by synchronization with a parallel clock
10 (PLCK: Parallel Clock), which is slower than the serial clock synchronization. Shift
registers S3 to S17, S22 to S36, D3 to D17, and D22 to D36 are omitted from FIGs.
4A and 4B.
[0066]
In the present embodiment, the scrambler illustrated in FIG. 4A receives an
15 eight-bit data character as input, and scrambles the eight-bit data character into an
eight-bit encoded block. The descrambler illustrated in FIG. 4B receives an eight-bit
encoded block as input, and descrambles the eight-bit encoded block into an
eight-bit data character.
[0067]
20 The self-synchronizing scrambler and the self-synchronizing descrambler
respectively illustrated in FIGs. 4A and 4B are each required to be initialized so that
the shift registers SO to S39 and DO to D39 share the same value. To this end, in the
transmitting circuit, an encoded symbol transmitted in a period during which the
first encoding circuit 201 is selected is input into the scrambler illustrated in FIG. 4A,
25 which is the second encoding circuit 202. By doing so, the shift registers SO to S39
are initialized before input of the data character (TXD). Similarly, in the receiving
circuit, an encoded symbol received in a period during which the first decoding
circuit 302 is selected is input into the descrambler illustrated in FIG. 4B, which is
21
the second decoding circuit 303. In this way, the shift registers DO to D39 are
initialized to have the same value as the shift registers SO to S39 by using the
encoded symbol received via the chaimels.
[0068]
5 With this structure, the second encoding circuit 202 can scramble an
eight-bit data character, and the second decoding circuit 303 can descramble an
eight-bit encoded block.
[0069]

10 The following describes the encoded symbol having been encoded using the
8B/10B coding. In the present embodiment, in the 8B/10B coding employed as the
first channel coding, eight-bit data is converted into 10-bit data. In the 8B/10B
coding, by taking advantage of redundancy of two-bit data generated by the
above-mentioned conversion, a special K symbol for controlling communications
15 between a transmitter and a receiver is usable in addition to a D symbol representing
normal eight-bit data.
[0070]
Regarding the special K symbol, FIG. 5 shows correspondences among a
"symbol name", a "mnemonic", a "fimction", a "(hexadecimal) control character",
20 and a "(binary) encoded symbol" for each K symbol.
[0071]
The "symbol name" indicates a name given to a corresponding K symbol
for convenience sake.
[0072]
25 The "mnemonic" indicates a notational example of a corresponding K
symbol when the K symbol is expressed in mnemonic form. In many cases, a
notation relating to a fianction of the K symbol is used.
[0073]
22
The "function" indicates a fiinction defined by a corresponding K symbol.
The function refers to a function required in communications. Examples of the
function are notification of a start of packet transmission and notification of an end
of a packet.
5 [0074]
The "control character" indicates a notation when a corresponding K
symbol is expressed in hexadecimal.
[0075]
The "encoded symbol" indicates a notation when a corresponding K symbol
10 is expressed by a binary encoded symbol. The K symbol transmitted from a
transmitter to a receiver is the encoded symbol.
[0076]
FIG. 5 shows K symbols "K28.1", "K28.3", "K28.5", and "K29.7". The
following describes details thereof
15 [0077]
A COM (Comma) symbol (K28.5) is a symbol used as a delimiter to
perform symbol synchronization. This is because the COM symbol has a unique
signal pattern that cannot be generated from any combination of other two encoded
symbols within serial data including encoded symbol sequences having been
20 encoded using the 8B/10B coding. The symbol synchronization refers to a state
where a receiver in serial data transmission recognizes positions (first bits) at which
serial data is delimited into encoded symbols, and properly receives the encoded
symbols as parallel data.
[0078]
25 An SOP (Start Of Packet) symbol (K28.1) is used to cause the receiver to
recognize a steirt position of a packet, and is added to the start position. Upon
receiving the SOP, the receiver recognizes that the following data is actual data
(packet pay load).
23
[0079]
An EOP (End Of Packet) symbol (K29.7) is used to cause the receiver to
recognize an end position of a packet, and is added to the end position. Although
recognizing the end position by receiving a packet of a predetermined size, the
5 receiver properly recognizes that data transmission of a packet payload is actually
completed by receiving the EOP.
[0080]
An LIDL (Logical Idle) symbol (K28.3) is a logical idle signal output in the
idle period for not transmitting data, and is used to maintain symbol synchronization
10 in the idle period.
[0081]
The symbol synchronization is necessary not only at initialization and
restoration from a power-saving state but also at restoration from an unforeseen
transmission error state. It is therefore desirable that the COM symbol used as a
15 delimiter to perform symbol synchronization be transmitted on a regular basis. In the
present embodiment, a symbol set generated by combining the COM symbol with an
encoded symbol other than the COM symbol is used. With this structure, in the
present embodiment, the COM symbol is surely transmitted on a regular basis, and
other D symbols are used to give notification of the idle period, and a start position
20 and an end position of a packet.
[0082]
FIG. 6 shows examples of the symbol set used in the present embodiment.
In FIG. 6, an SYN (Synchronization) symbol set includes the COM symbol (K28.5)
and a particular D symbol (D31.5). The SYN (Synchronization) symbol set is
25 transmitted for a predetermined time period to establish symbol synchronization at
the initialization and the restoration from a power-saving state. As shown in FIG. 6,
the first symbol of each symbol set is the COM symbol (K28.5), and the second
symbol of each symbol set is a symbol other than the COM symbol. By transmitting
24
the control characters in units of symbol sets, communication control on regular
transmission of the COM symbol and notification of a start position and an end
position of a packet is achieved. Hereinafter, unless particularly distinguished, the
SOP, the EOP, the LIDL, and the SYN represent symbol sets corresponding to
5 respective symbol set names shown in FIG. 6.

The following describes an operation of the communication system
according to the present embodiment with use of a timing diagram illustrated in FIG.
7. In the following description on the operation of the communication system, the
10 functional block diagrams of FIGs. 1, 2, and 3 are used as well. In the present
embodiment, data transmission from the host device 100 to the target device 110 is
described. Since data transmission from the target device 110 to the host device 100
is similar to the data transmission from the host device 100 to the target device 110,
the detailed explanation thereof is omitted in the present description.
15 [0083]
The horizontal axis in FIG. 7 indicates time. In FIG. 7, signals collectively
indicated by the term "Transmitter" (PCLK, TBUS, TSEL, TXC (TXM), and TXD)
are signals used in the transmitting circuit. On the other hand, in FIG. 7, signals
collectively indicated by the term "Receiver" (PCLK, RSEL, RXC (RXM), RXD,
20 and RBUS) are signals used in the receiving circuit. The other signals are signals
flowing through the serial charmel 121.

The transmission control unit 203 receives, as input, transmission data via
the transmission bus (TBUS) by synchronization with the PCLK, and outputs the
25 received transmission data to the second encoding circuit 202 an eight-bit data
character (TXD) at a time. Upon receiving the eight-bit data character (TXD) as
input, the second encoding circuit 202 converts the eight-bit data character into an
eight-bit encoded block and outputs the eight-bit encoded block to the serial driver
25
204. The serial driver 204 converts the eight-bit encoded block input by
synchronization with the PCLK into serial data by synchronization with the SCLK
(Serial Clock), which has a frequency eight times higher than that of the PCLK. The
serial driver 204 outputs, as a differential signal, the serial data generated as a result
5 of the conversion via the D0+ terminal 106 and the DO- terminal 107. As described
above, when a frequency ratio of the PCLK to the SCLK is 1:8, data transmission is
performed with no interruption of transmission data caused by excessively
high-speed conversion processing and with no delay caused by excessively
low-speed conversion processing.
10 [0084]
The first encoding circuit 201 converts an eight-bit control character (TXC)
input from the transmission control unit 203 by synchronization with the PCLK into
a 10-bit encoded symbol, and outputs the 10-bit encoded symbol to the serial driver
204. The serial driver 204 converts the 10-bit encoded symbol input by
15 synchronization with the PCLK into serial data by synchronization with the SCLK,
which has a frequency eight times higher than that of the PCLK. Since the serial
driver 204 can convert only eight bits of the 10-bit data into the serial data for one
PCLK, a surplus of two bits is generated, leading to delay. This means that, when a
control character is transmitted, the serial driver 204 cannot output the encoded
20 symbol input thereto as serial data at the same speed as a speed at which the encoded
symbol is input. To address the problem, the transmission control unit 203 generates
a 40-bit coding frame in a period during which the first encoding circuit 201 is
selected. The bit length of the 40-bit coding frame is equal to the least common
multiple of the bit length of the encoded symbol (10) and the bit length of the
25 encoded block (8). The transmission control unit 203 performs confrol so that
encoded symbols are transmitted in units of 40-bit coding frames thus generated. In
order to output the 40-bit coding frame, a cycle time of five cycles of the PCLK is
necessary. The transmission control unit 203 therefore provides a standby time of
26
one cycle each time four control characters (TXCs) corresponding to a coding frame
are output in a cycle time of four cycles of the PCLK. With this structure, all the
coding frames output from the first encoding circuit 201 by synchronization with the
PCLK are output from the serial driver 204 by synchronization with the SCLK. That
5 is to say, by providing the standby time of one cycle, the host device 100 can absorb,
for each one cycle, the surplus of two bits generated each time a 10-bit encoded
symbol is transmitted.
[Time TO to Time Tl]
A period between Time TO and Time Tl is an idle period during which there
10 is no transmission request via the transmission bus (TBUS). In the idle period, the
transmission control unit 103 selects the first encoding circuit 201 by setting the
transmission selection signal (TSEL) to Low. The first encoding circuit 201
repeatedly outputs a symbol set generated by combining the COM for the symbol
synchronization with the LIDL as the idle signal, according to the 8B/10B coding.
15 Furthermore, the serial driver 204 transmits, to the receiving circuit 113, a coding
fretme generated by converting a symbol set including the COM and the LIDL into
the serial data. Hereinafter, description is made on the assumption that each control
character is a symbol set including the COM and another symbol, and explanation
thereof is omitted.
20 [0085]
As illusfrated in FIG. 7, a signal transmitted from the transmitting circuit
103 reaches the receiving circuit 113 with a slight delay (fransmission latency,
reception latency) from the time of transmission.
[Time Tl to Time T3]
25 Upon reception of a transmission request via the fransmission bus (TBUS)
at Time Tl, the transmission confrol unit 203 performs confrol so that a coding
frame including the SOP indicating a start position of a packet is transmitted. The
fransmission confrol unit 203 then switches the transmission selection signal (TSEL)
27
to High at Time T2, and outputs transmission data transmitted via the transmission
bus (TBUS) to the second encoding circuit 202 as an eight-bit data character (TXD)
at a time. Following the 40-bit coding frame that is input from the first encoding
circuit 201 and includes the SOP, the serial driver 204 continuously outputs eight-bit
5 encoded blocks input from the second encoding circuit 202.
[At and After Time T3]
At Time T3, the transmission control unit 203 completes transmission of the
data character (TXD) of a predetermined packet size. The fransmission control unit
203 switches the transmission selection signal (TSEL) to Low to select the first
10 encoding circuit 201, and performs control so that the coding frame including the
EOP indicating an end position of a packet is transmitted. At and after Time T4, the
transmission control unit 203 performs control so that a coding frame that includes
the LIDL and indicates the idle period is transmitted, as in the period between Time
TO and Time Tl.
15 [0086]
When a size of the fransmission data transmitted via the fransmission bus
(TBUS) exceeds a predetermined packet size, the fransmission request via the
fransmission bus (TBUS) continues at Time T3. As a result, the transmitting circuit
103 once switches from the second encoding circuit 202 to the first encoding circuit
20 201, and transmits a coding frame including the SOP as in the period between Time
Tl and Time T2. The transmitting circuit 103 then switches the encoding circuit to
the second encoding circuit 202 again, and the second encoding circuit 202 encodes
residual transmission data an eight-bit data character (TXD) at a time. The
transmitting circuit 103 continuously outputs encoded blocks generated as a result of
25 encoding from the serial driver 204.

When the receiving circuit 113 receives packets, transmission latency to
perform transmission from the transmitting circuit 103 to the serial charmel 121
28
occurs. When the receiving circuit 113 receives packets, reception latency to
perform reception from the serial channel 121 occurs as well. Thereft)re, in FIG. 7,
Time TO to Time T4 with respect to the transmitting circuit 103 respectively
correspond to Time TO' to Time T4' with respect to the receiving circuit 113.
5 [0087]
The reception control unit 304 included in the receiving circuit 113 selects
the first decoding circuit 302 by setting the reception selection signal (RSEL) to Low.
In this period, the serial receiver 301 outputs serial data received via the serial
channel 121 by synchronization with the SCLK to the first decoding circuit 302 as a
10 10-bit encoded symbol by synchronization with the PCLK. Similarly to the
transmitting circuit 103, the frequency ratio of the PCLK to the SCLK is assumed to
be 1:8 in the receiving circuit 113. As a result, only eight bits of the 10-bit encoded
symbol can be received in a cycle time of one cycle of the PCLK. To address the
problem, the serial receiver 301 outputs a coding frame including four encoded
15 symbols to the second decoding circuit 303 for every five cycles of the PCLK.
[0088]
On the other hand, in a period during which the reception control unit 304
selects the second decoding circuit 303 by setting the reception selection signal
(RSEL) to High, the reception control unit 304 continuously outputs encoded blocks
20 to the second decoding circuit 303 by synchronization with the PCLK, since the
serial receiver 301 can receive an eight-bit encoded block in a cycle time of one
cycle of the PCLK.
[Time TO'to Time Tl']
The reception confrol unit 304 included in the receiving circuit 113 selects
25 the first decoding circuit 302 at Time TO' by setting the reception selection signal
(RSEL) to Low, since it is the idle period before data reception. At Time TO', the
serial receiver 301 starts receiving a coding frame including the LIDL. The first
decoding circuit 302 converts the 10-bit encoded symbol input from the serial
29
receiver 301 into an eight-bit control character (RXC). The first decoding circuit 302
outputs the control character to the reception control unit 304 along with the
decoding mode (RXM) indicating whether the received encoded symbol is a K
symbol or a D symbol. The reception control unit 304 confirms that the idle period
5 is continued by receiving the control character (RXC) or the decoding mode (RXM)
corresponding to the LIDL.
[Time Tl'to Time T3']
A coding frame including the SOP is received in a period between Time Tl'
and Time T2'. Triggered by reception of the SOP at Time T2' at which the reception
10 of the encoded symbol including the SOP is completed, the reception control unit
304 switches the reception selection signal (RSEL) to High. Thereafter, the serial
receiver 301 outputs an eight-bit encoded block, at a time, of the serial data received
via the serial channel 121 to the second decoding circuit 303 by synchronization
with the PCLK. The second decoding circuit 303 descrambles the encoded block
15 input thereto into the data character (RXD), and inputs the data character into the
reception control unit 304. The reception control unit 304 outputs the data character
as the reception data via the reception bus (REUS).
[At and After Time T3']
Upon completion of reception of the data character (RXD) of a
20 predetermined packet size at Time T3', the reception control unit 304 switches the
reception selection signal (RSEL) to Low to select the first decoding circuit 302, and
performs reception of the coding frame including the EOP. After completing the
reception of the coding frame including the EOP at Time T4', the reception control
unit 304 continues reception of the coding fi-ame including the LIDL as in the period
25 between Time TO' and Time Tl'. When data transmission from the transmitting
circuit 113 continues at and after Time T3', the coding frame including the SOP is
received again. As a result, the reception control unit 304 performs data reception as
in the period between Time T2' and Time T3'.
30

According to the present embodiment, the transmitting circuit 103 (115) and
the receiving circuit 113 (105) corresponding thereto do not influence the
transmission efficiency. This means that, in the present embodiment, in the idle
5 period for not transmitting valid data, symbol synchronization is maintained by
repeatedly transmitting an idle signal in the 8B/10B format. Furthermore, in the
present embodiment, even when symbol synchronization fails due to a
communication error or other factors, early restoration of symbol synchronization is
achieved. In the present embodiment, at the time of transmitting the valid data, data
10 is eflRciently transmitted using the scrambling having no coding loss.
[0089]

The following describes a first modification of the communication system
according to the present invention with reference to the drawings. In the
15 embodiment described above, in the idle period for not transmitting valid data, the
coding fi-ame including the LIDL is repeatedly transmitted to maintain symbol
synchronization. In the embodiment described above, however, it can be said that
power is wastefiilly consumed as the transmission of the coding fi-ame is continued
even to maintain symbol synchronization. In the first modification, the structure that
20 reduces power consumption is described.

The structure itself is similar to that shown in the embodiment described
above. Although not shown in detail in the embodiment described above, in the
interface circuit in the first modification, the transmission control unit 203 has a
25 fimction to put the transmitting circuit 103 (115) into a power-saving state. The
receiving circuit 113 (105) has a function to transition to the power-saving state and
a function to be activated fi"om the power-saving state, upon notification from the
transmitting circuit 103 (115). More specifically, each of the enable signal (TXEN)
31
for the serial driver 204 included in the transmitting circuit shown in FIG. 2 and the
enable signal (RXEN) for the serial receiver 301 shown in FIG. 3 is Enable at all
times in the embodiment described above. The first modification, however, is
different from the embodiment described above in that the enable signals are
5 controlled by the transmission control unit and the reception control unit to be
Disable in the idle period.

The following describes data transmission according to the first
modification with use of a timing diagram illustrated in FIG. 8. In order to describe
10 the structure, the functional block diagrams of FIGs. 1, 2, and 3 are also referred to.
In the first modification, operation to be restored from the power-saving state and
operation to fransition to the power-saving state are described with use of FIGs. 8
and 9, respectively. A state not being the power-saving state is also referred to as a
normal state.
15
[Time TO to Time Tl]
As illustrated in FIG 8, for the transmitting circuit 103, a period between
Time TO and Time Tl is an idle period during which there is no transmission request
via the transmission bus (TBUS). The transmission control unit 203 sets the enable
20 signal (TXEN) for the serial driver 204 to Disable, so that the serial channel 121 is
pulled down. This puts the serial driver 204 into the power-saving state.
[Time Tl to Time T2]
When there is the transmission request via the transmission bus (TBUS) at
Time Tl, the transmission confrol unit 203 sets the enable signal (TXEN) for the
25 serial driver 204 to Enable to restore the serial driver 204 from the power-saving
state. The transmission control unit 203 fixes an output from the serializer 205 to
Low for a predetermined time period during restoration from the power-saving state,
so that a Low fixed signal is output from the differential driver 206.
32
[Time T2 to Time T3]
After the Low fixed signal is output for the predetermined time period, the
transmission control unit 203 starts transmission of a coding fi-ame including the
SYN by using the first encoding circuit 201. As shown in FIG. 6, the SYN has been
5 generated by combining the COM symbol as a delimiter with a particular D symbol
with a high edge-density of signals. The SYN is transmitted fi"om the transmitting
circuit 103 to the receiving circuit 113 for a predetermined time period to establish
symbol synchronization at the restoration fi"om the power-saving state.
[At and After Time T3]
10 The transmission control unit 203 starts transmission of the coding frame
including the SOP at Time T3. Upon completion of the transmission of the coding
frame, the transmission control unit 203 switches the transmission selection signal
(TSEL) to High, and outputs transmission data transmitted via the transmission bus
(TBUS) to the second encoding circuit 202 an eight-bit data character (TXD) at a
15 time. Thereafter, the valid data is transmitted in the first modification as in the
embodiment described above.

[Time TO'to Time Tl']
As illustrated in FIG. 8, in the idle period, the transmitting circuit 103 is in
20 the power-saving state in which the serial channel 121 is pulled down, and the
receiving circuit 113 is also in the power-saving state during the period between
Time TO' and Time Tl'. In a period during which the enable signal (RXEN) for the
serial receiver 301 is set to Disable, the detection circuit 307 monitors differential
amplitude on the serial charmel 121. This means that the detection circuit 307
25 monitors an absolute value of a difference between the potentials on the signal lines
D0+ and DO- constituting the serial channel 121. Since the serial channel 121 is
pulled down during the period between Time TO' and Time Tl', a detection signal
(DET) output fi-om the detection circuit 307 is Low, indicating that the differential
33
amplitude is nearly zero. Upon receiving the detection signal (DET) being Low, the
reception control unit 304 maintains the enable signal (RXEN) for the serial receiver
301 to Disable.
[Time Tl'to Time T2']
5 When detecting the differential amplitude of the Low fixed signal output
from the transmitting circuit 103 at some point in the period between Time Tl' and
Time T2', the detection circuit 307 switches the detection signal (DET) from Low to
High. In response to this, the reception control unit 304 restores the serial receiver
301 from the power-saving state by setting the enable signal (RXEN) to Enable at
10 Time T2'. When the differential receiver 305 is activated upon setting of the enable
signal (RXEN) to Enable, the detection circuit 307 is no longer needed, and the
detection signal (DET) as an output from the detection circuit 307 is no longer used.
This means that the detection circuit 307 itself is operated, but is not referred to
because the detection signal output from the detection circuit 307 is not needed until
15 the detection signal serves as a frigger to restore the serial receiver 301 from the
power-saving state next time.
[Time T2' to Time T3']
In the period between Time T2' and Time T3', the serial receiver 301
receives the coding frame including the SYN from the transmitting circuit 103. At
20 this point, however, symbol synchronization is not yet established as the
de-serializer 306 is just started being activated. The de-serializer 306 therefore
cannot correctly receive signals as encoded symbols. To address this problem, the
reception control unit 304 monitors signals input into the de-serializer 306, and
detects a signal pattern in which the COM symbol cyclically appears for every two
25 symbols to establish symbol synchronization.
[At and After Time T3']
When symbol synchronization is established at Time T3', the de-serializer
306 outputs correctly-separated 10-bit encoded symbols to the first decoding circuit
34
302. Thereafter, the receiving circuit 113 performs reception of data upon reception
of the SOP as in the embodiment described above. That is to say, the receiving
circuit 113 starts reception of the coding frame including the SOP at Time T3'. At
after Time T4' at which the reception of the coding frame including the SOP is
5 completed, the receiving circuit 113 switches the reception selection signal (RSEL)
to High, and outputs, as the reception data, the data character (RXD) received from
the second decoding circuit 303 via the transmission bus (RBUS).

[Time T4 to Time T6]
10 As illustrated in FIG. 9, upon completion of transmission of the data
character (TXD) of a predetermined packet size at Time T5, the transmission control
unit 203 included in the transmitting circuit 103 switches the transmission selection
signal (TSEL) to Low to select the first encoding circuit 201. The serial driver 204
then transmits the coding frame including the EOP.
15 [At and After Time T6]
After performing control so that the serial driver 204 outputs the High fixed
signal for a predetermined time period at Time T6, the transmission confrol unit 203
sets the enable signal (TXEN) to Disable to cause the serial driver 204 to transition
to the power-saving state. By doing so, the serial channel 121 is pulled down at and
20 after T7.

[Time T4' to Time T6']
As illustrated in FIG. 9, upon completion of reception of the data character
(TXD) of the predetermined packet size at Time T5', the reception control unit 304
25 included in the receiving circuit 113 switches the reception selection signal (RSEL)
to Low to select the first decoding circuit 302. The serial receiver 301 then starts
receiving the coding frame including the EOP.
[At and After Time T6']
35
At Time T6', the serial receiver 301 starts receiving the High fixed signal
(Fixed High) output from the transmitting circuit 103. When the High fixed signal is
input into the de-serializer 306, the reception control unit 304 starts transition to the
power-saving state. Since the detection signal (DET) output from the detection
5 circuit 307 is used as a trigger to restore the receiving circuit 113 from the
power-saving state next time, the detection signal (DET) should certainly be set to
Low before the transition to the power-saving state. The detection circuit 307 is a
comparator that detects negative differential amplitude of the Low fixed signal as
High. Therefore, by inputting positive differential amplitude of the High fixed signal,
10 it is possible to make sure that the detection signal (DET) as an output from the
detection circuit 307 becomes Low. In the first modification, when the detection
signal (DET) becomes Low after the High fixed signal is received, the enable signal
(RXEN) for the serial receiver 301 is set to Disable to cause the receiving circuit 113
to start fransitioning to the power-saving state at Time T7'.
15
According to the first modification, the fransmitting circuit 103 (115) and
the receiving circuit 113 (105) corresponding thereto transition to the power-saving
state in the idle period. At the time of restoration from the power-saving state, early
establishment of symbol synchronization is achieved by using the COM symbol
20 having a unique signal pattern in the 8B/10B coding to resume transmission of the
valid data. Since it is possible to save power in the idle period, the first modification
is especially effective in a case where valid data is not transmitted frequently.
[0090]

25 The following describes a second modification of the embodiment
according to the present invention with reference to the drawings. In the
embodiment described above, the fransmission data is scrambled an eight-bit data
character at a time to generate eight-bit encoded blocks. The bit length of the data
36
character, however, is not limited to eight bits. For example, suppose that the target
device 110 illustrated in FIG. 1 is a display device, it is considered that pixel
information with 10-bit precision of each of RGB colors is transmitted as the data
character. In this case, the bit length of the encoded symbol generated by encoding
5 the control character using the 8B/10B coding corresponds to the bit length of the
encoded block generated using a second coding scheme for transmitting the valid
data. In the second modification, description is made on a case where the bit length
of the encoded symbol is equal to the bit length of the data character as described
above.
10
FIG. 10 is a block diagram illustrating the structure of the transmitting
circuit according to the second modification. In the second modification, the host
device 100 and the target device 110 each include a transmitting circuit 1000
illustrated in FIG. 10, in place of the transmitting circuits 103 and 115, respectively.
15 [0091]
The transmitting circuit 1000 illustrated in FIG. 10 differs fi-om the
transmitting circuit 103 illustrated in FIG. 2 in that it includes a second encoding
circuit 1002 in place of the second encoding circuit 202. The second encoding
circuit 1002 illustrated in FIG. 10 differs fi-om the second encoding circuit 202
20 shown in the embodiment described above in the following points. That is, the bit
length of the data character (TXD) input into the second encoding circuit 1002
illustrated in FIG. 10 and the bit length of the output encoded symbol are each 10
bits, and the second encoding circuit 1002 scrambles 10-bit data at a time.
[0092]
25 Encoding is performed by inputting the encoded symbol fi-om the first
encoding circuit 1001 to the serial driver 1004 or inputting the encoded block from
the second encoding circuit 1002 to the serial driver 1004 by synchronization with
the PCLK. Each of the encoded symbol and the encoded block is 10-bit parallel data.
37
The serial driver 1004 therefore receives the 10-bit parallel data as input, and
outputs serial data by synchronization with the SCLK, which has a frequency 10
times higher than that of the PCLK. With this structure, in a period during which the
first encoding circuit 1001 is selected, the transmission control unit 1003 does not
5 need to provide the standby time for each coding frame as shown in the embodiment
described above.
[0093]
Furthermore, a receiving circuit 1100 illustrated in FIG. 11 differs from the
receiving circuit 113 illustrated in FIG. 3 in that it includes a second decoding circuit
10 1103 in place of the second decoding circuit 303. The second decoding circuit 1103
receives a 10-bit encoded block as input, decodes 10-bit data at a time, and outputs a
10-bit data character.
[0094]
A serial receiver 1101 outputs the encoded symbol to the first decoding
15 circuit 1102 or outputs the encoded block to the second decoding circuit 1103 by
synchronization with the PCLK. Each of the encoded symbol and the encoded block
output from the serial receiver 1101 is 10-bit parallel data. The serial receiver 1101
receives serial data as input by synchronization with the SCLK, which has a
frequency 10 times higher than that of the PCLK, and outputs the serial data as the
20 10-bit parallel data by synchronization with the PCLK.

The following describes operations of the transmitting circuit and the
receiving circuit according to the second modification with use of a timing diagram
illustrated in FIG. 12. FIG. 12 is the timing diagram illustrating data transmission
25 from the transmitting circuit 1000 to the receiving circuit 1100 according to the
second modification.
[Time TO to Time Tl]
As illustrated in FIG. 12, for the transmitting circuit 1000, a period between
38
Time TO and Time Tl is an idle period during which there is no transmission request
via the transmission bus (TBUS). The transmitting circuit 1000 sets the transmission
selection signal (TSEL) to Low to select the first encoding circuit 1001. The first
encoding circuit 1001 repeatedly outputs the LIDL, which is the idle signal
5 according to the 8B/10B coding. The serial driver 1004 converts the LIDL into serial
data, and transmits the serial data to the receiving circuit 1100.
[Time Tl to Time T3]
Upon reception of a transmission request via the transmission bus (TBUS)
at Time Tl, the transmission control unit 1003 performs control so that the SOP
10 indicating a start position of a packet is transmitted. As described above, in the
second modification, there is no need to transmit the encoded symbol (or the symbol
set) in units of coding frames, as there is no need to control the speed at which serial
data is processed and the speed at which parallel data is processed. In the second
modification, in response to the transmission request, the transmission control unit
15 1003 immediately performs control so that the SOP is transmitted, and switches the
encoding circuit to the second encoding circuit 1002 at Time T2. At and after Time
T2, the transmission control unit 1003 outputs transmission data transmitted via the
transmission bus (TBUS) to the second encoding circuit 1002 a 10-bit data character
(TXD) at a time. The second encoding circuit 1002 randomizes a bit pattern of the
20 10-bit data character by scrambling to generate a 10-bit encoded block, and outputs
the 10-bit encoded block to the serial driver 1004. The serial driver 1004 converts
the encoded block input thereto into serial data, and outputs the serial data via the
serial channel 121.
[At and After Time T3]
25 Upon completion of transmission of the data character (TXD) of a
predetermined packet size at Time T3, the transmission control unit 1003 switches
the transmission selection signal (TSEL) to Low to select the first encoding circuit
1001. The transmission control unit 1003 performs control so that the coding frame
39
including the EOP indicating an end position of a packet is transmitted. At and after
Time T4, the transmission control unit 1003 performs control so that the encoded
symbol LIDL indicating the idle period is repeatedly transmitted as in the period
between Time TO and Time Tl.
5 [0095]
When a size of transmission data transmitted via the transmission bus
(TBUS) exceeds the predetermined packet size, the transmission request via the
transmission bus (TBUS) continues at Time T3. As a result, the transmitting circuit
1000 once switches from the second encoding circuit 1002 to the first encoding
10 circuit 1001, and transmits the coding frame including the SOP as in the period
between Time Tl and Time T2. The transmitting circuit 1000 then switches the
encoding circuit to the second encoding circuit 1002 again, and the second encoding
circuit 1002 encodes residual transmission data a 10-bit data character (TXD) at a
time. The transmitting circuit 1000 continuously outputs encoded blocks generated
15 as a result of encoding from the serial driver 1004.

[Time TO'to Time Tl']
The reception control unit 1104 included in the receiving circuit 1100
selects the first decoding circuit 1102 at Time TO' by setting the reception selection
20 signal (RSEL) to Low, as it is the idle period before data reception. The reception
control unit 1104 confirms that the idle period is continued by repeatedly receiving
the LIDL at and after Time TO'.
[Time Tl'to Time T3']
In the period between Time Tl' and Time T2', the reception control unit
25 1104 performs reception of the SOP. Triggered by the reception of the SOP at Time
T2' at which the reception is completed, the reception control unit 1104 switches the
reception selection signal (RSEL) to High. In response to the switching of the
reception selection signal (RSEL) to High, the serial receiver 1101 receives the
40
serial data via the serial channel 121 a 10-bit encoded block at a time. The serial
receiver 1101 then outputs the received 10-bit serial data to the second decoding
circuit 1103 as 10-bit parallel data by synchronization with the PCLK. The second
decoding circuit 1103 descrambles the encoded block input thereto into the data
5 character (RXD), and inputs the data character to the reception control unit 1104.
The reception control unit 1104 outputs, as reception data, the received data
character (RXD) to the back-end unit via the reception bus (REUS).
[At and After Time T3']
Upon completion of reception of the data character (RXD) of a
10 predetermined packet size at Time T3', the reception control unit 1104 switches the
reception selection signal (RSEL) to Low to select the first decoding circuit 1102,
and performs reception of the EOP. Upon completion of the reception of the EOP at
Time T4', the reception control unit 1104 continues reception of the LIDL as in the
period between Time TO' and Time Tl'. When data transmission from the
15 transmitting circuit 1000 continues at and after Time T3', the reception control unit
1104 performs data reception as in the period between Time T2' and Time T3' by
receiving the SOP again.

According to the second modification, the transmitting circuit 1000 and the
20 receiving circuit 1100 corresponding thereto can switch between the first channel
coding and the second channel coding with a simple structure without controlling
the standby time for each coding frame. In particular, because parallel data pieces
handled by synchronization with the PCLK by the serial drivers 1004 and 1101 have
the same bit length (i.e. 10 bits), the structure can be simplified compared to the
25 structure in which eight-bit data and 10-bit data are both used.
[0096]
In the communication system according to the second modification, even
when the bit length of each of the data characters handled by the transmission bus
41
(TBUS) and the reception bus (RBUS) is eight bits, the data characters are
transmitted a 10-bit encoded block at a time on the serial charmel 121. With this
structure, the above-mentioned advantageous effect that the structure is simplified is
obtained.
5 [0097]
In this case, the transmission control unit 1003 is required to convert a
sequence of eight-bit data characters input via the transmission bus (TBUS) into
10-bit data characters (TXDs) and output the 10-bit data characters to the second
encoding circuit 1002. When a packet size of the transmission data is not a multiple
10 of 10 bits, appropriate padding data may be added to an end of the packet so that the
packet size becomes a multiple of 10 bits. The transmission control unit 1003 may
have the function to add the padding data.
[0098]
The reception control unit 1104 performs control so that the received 10-bit
15 data characters (RXDs) are converted into reception data eight bits at a time, and the
eight-bit reception data is output via the reception bus (RBUS). In this case, before
the output of the reception data, it is necessary to remove the padding data having
been added to the end of the packet in accordance with a packet size shared in
advance. The reception control unit 1104 may have the function to remove the
20 padding data.
[0099]

The following describes a third modification of the embodiment according
to the present invention with reference to the drawings. In the embodiment described
25 above, the transmission data is scrambled by the second encoding circuit and
transmitted as the serial data. The run-length at the time of transmitting the serial
data, however, is not ensured. Therefore, in the embodiment described above, values
"0" or " 1 " may continue for a long time period, depending on the transmission data.
42
[0100]
To address this problem, in the third modification, description is made on a
case where a scheme in which a predetermined number of consecutive data
characters are scrambled, and a synchronization header is added to the
5 predetermined number of data characters to generate the encoded block is applied as
the second channel coding. Specifically, description is made on the assumption that
the 64B/66B coding is used as the second channel coding. In the 64B/66B coding,
eight data characters of consecutive eight bits are scrambled into a 64-bit data
character, and a 2-bit synchronization header is added to the 64-bit data character to
10 generate a 66-bit encoded block. In this case, for the purpose of ensuring the
run-length, only "01" and "10", each of which includes a bit transition from 0 to 1 or
from 1 to 0, are used as the synchronization header. As for the synchronization
header, "01" is used as a non-terminating synchronization header (NTSYNC). On
the other hand, "10" is used as a terminating synchronization header (TSYNC). A
15 termination identifying signal (TERM) is used to identify a non-terminating block
(NTBLK), which is an encoded block including the non-terminating synchronization
header (NTSYNC), and a terminating block (TBLK), which is an encoded block
including the terminating synchronization header (TSYNC).

20 FIG. 13 is a block diagram illustrating the structure of a transmitting circuit
1300 according to the third modification. In the transmitting circuit 1300 illustrated
in FIG. 13, a second encoding circuit 1302 receives the termination identifying
signal (TERM) from a transmission control unit 1303. The transmitting circuit 1300
differs from the transmitting circuit 103 according to the embodiment described
25 above in that, upon reception of the termination identifying signal (TERM), one of
the non-terminating synchronization header (NTSYNC) and the terminating
synchronization header (TSYNC) is output as the synchronization header.
[0101]
43
The termination identifying signal (TERM) is used to cause the receiving
circuit to identify whether the encoded block output from the transmission control
unit 1303 is the non-terminating block (NTBLK) or the terminating block (TBLK).
[0102]
5 The second encoding circuit 1302 scrambles eight data characters (TXDs),
and outputs the eight scrambled data characters to the serial driver 1304 in a cycle
time of eight cycles of the PCLK. In this case, the second encoding circuit 1302 also
outputs the two-bit synchronization header (SYNC) in the first cycle of the eight
cycles. The second encoding circuit 1302 thus outputs a 66-bit encoded block
10 including the synchronization header in the cycle time of eight cycles of the PCLK.
[0103]
The serial driver 1304 outputs the encoded block via the serial channel 121
as the serial data in a cycle time of 66 cycles of the SCLK. In the third modification,
the frequency ratio of the PCLK to the SCLK is 8:66, so that a speed at which the
15 transmission data is input matches a speed at which the serial data is output. This
means that the amount of input data corresponds to the amount of output data per
unit time.
[0104]
FIG. 14 illustrates the structure of a receiving circuit 1400 according to the
20 third modification. The receiving circuit 1400 has approximately the same structure
as the receiving circuit 113 in the embodiment described above. The receiving
circuit 1400, however, differs from the receiving circuit 113 in that the termination
identifying signal (TERM) is output from the serial driver 1401 to the reception
control unit 1404. The reception control unit 1404 is capable of detecting an end of
25 the reception data by using the termination identifying signal (TERM). Therefore, in
contrast to the embodiment described above, there is no need to share a packet size
between a transmitter and a receiver.
[0105]
44
The serial receiver 1401 outputs serial data received via the serial channel
121 by synchronization with the SCLK to the first decoding circuit 1402 as 10-bit
encoded symbols by synchronization with the PCLK. Similarly to the transmitting
circuit 1300, the fi-equency ratio of the PCLK to the SCLK is 8:66 in the receiving
5 circuit 1400. As a result, each of the 10-bit encoded symbols cannot be received in a
cycle time of one cycle of the PCLK. The serial receiver 1401 thus receives a coding
fi-ame including 33 encoded symbols for every 40 cycles of the PCLK.
[0106]
On the other hand, in a period during which the reception control unit 1404
10 selects the second decoding circuit 1403 by setting the reception selection signal
(RSEL) to High, the serial receiver 1401 receives a 66-bit encoded block in a cycle
time of eight cycles of the PCLK. Eight eight-bit data characters generated as a
result of the scrambling, which are valid data within the encoded block, are
continuously output to the second decoding circuit 1403 in a cycle time of eight
15 cycles of the PCLK. When outputting the eight eight-bit data characters, the serial
receiver removes the synchronization header.
[0107]
Since the other functional structures of the transmitting circuit 1300 and the
receiving circuit 1400 are similar to those in the embodiment described above,
20 detailed description thereon is omitted.

The following describes the structure of the coding fi"ame in the third
modification. Similarly to the embodiment described above, the bit length of the
encoded symbol (10) differs from the bit length of the encoded block (66) in the
25 third modification.
[0108]
In the third modification, the bit length of the coding fi-ame is set to 330 bits,
which is equal to the least common multiple of bit length of the encoded symbol
45
(10) and the bit length of the encoded block (66). When the first encoding circuit
1301 is selected, the encoded symbols are transmitted in units of 330-bit coding
frames.
[0109]
5 FIGs. 15A to 15D each illustrate the structure of the coding fi-ame in the
third modification.
[0110]
The following describes the basic structure of the coding fi-ame according to
the third modification, with use of FIG. 15 A. As illustrated in FIG. 15 A, the coding
10 frame includes a frame synchronization symbol (F: Frame Sync) and 16 symbol sets
(SSO to SSI5: Symbol Sets). The frame synchronization symbol (F) is the COM
symbol (K28.5) added to the beginning of the coding frame. As in the embodiment
described above, each of 16 symbol sets has been generated by combining the COM
symbol (K28.5) with a symbol other than the COM symbol. Since, in each coding
15 frame, the first symbol set (SSO) following the frame synchronization symbol (F) is
immediately followed by the COM, a receiver can recognize a boundary between
coding frames.
[0111]
FIG. 15B illustrates one example of the structure of the coding frame (an
20 idle frame) for notifying the receiving circuit 1400 of the idle period in the third
modification. As illustrated in FIG. 15B, the idle frame includes the frame
synchronization symbol (C) including the COM symbol, and 16 LIDLs.
[0112]
FIG. 15C illustrates one example of the structure of the SOP frame used for
25 notification of a start position of a packet, and FIG. 15D illusfrates one example of
the structure of the EOP frame used for notification of an end position of a packet.
[0113]
As illustrated in FIG. 15C, in the SOP frame, each of the symbol sets SSO to
46
SS14 is the LIDL, and the symbol set SS15 is the SOP. As illustrated in FIG. 15D, in
the EOP frame, the symbol set SSO is the EOF, and each of the symbol sets SSI to
SSlSistheLIDL.

5 The following describes an operation of the communication system
according to the third modification with use of a timing diagram illustrated in FIG.
16. FIG. 16 is a timing diagram illustrating an operation before the start of data
transmission of the communication system according to the third modification. In
order to describe the structure, the system diagram of FIG. 1 and the block diagrams
10 of FIGs. 13 and 14 are also referred to.

[Time TO to Time Tl]
As illustrated in FIG. 16, since the period between Time TO and Time Tl is
the idle period during which there is no transmission request via the transmission
15 bus (TBUS), the transmission control unit 1303 selects the first encoding circuit
1301 by setting the transmission selection signal (TSEL) to Low. The transmitting
circuit 1300 thus transmits the idle frame illustrated in FIG. 15B to the receiving
circuit 1400.
[Time Tl to Time T3]
20 The transmission control unit 1303 starts transmission of the next coding
frame at Time Tl. The transmission control unit 1303 outputs four control characters
(TXCs) for every five cycles of the PCLK, and provides the standby time in the first
cycle. The transmission control unit 1303 performs control so that the control
character (TXC) corresponding to the frame synchronization symbol, i.e. the COM
25 symbol (K28.5), is output only in the standby time, such as Time Tl, at the
beginning of the coding frame. With this structure, the transmission control unit
1303 can perform control so that 33 confrol characters (TXCs) corresponding to a
coding frame is output in a cycle time of 40 cycles of the PCLK, i.e. in a period
47
between Time Tl and Time T3.
[0114]
Upon reception of the transmission request via the transmission bus (TBUS)
at Time T2, the transmission control unit 1303 performs control so that the last
5 symbol set (SSI5) within the coding frame is the SOP. The transmission control unit
1303 performs control so that the SOP frame illustrated in FIG. 15C is output in the
period between Time Tl and Time T3. The fransmission control unit 1303 then
switches the transmission selection signal (TSEL) to High at Time T3 so that
transmission data fransmitted via the transmission bus (TBUS) is output to the
10 second encoding circuit 1302 an eight-bit data character (TXD) at a time.
[At and After Time T3]
At and after Time T3, the transmission control unit 1303 sets the
termination identifying signal (TERM) to Non-Terminating, and performs control so
that eight data characters (TXDs) are output at a time to the second encoding circuit
15 1302. The second encoding circuit 1302 scrambles the output eight data characters
(TXDs), and adds the non-terminating synchronization header (NTSYNC) to the
scrambled eight data characters to generate the non-terminating block (NTBLK).
The serial driver 1304 converts the non-terminating block (NTBLK) into the serial
data, and outputs the serial data to the serial channel 121.
20
[Time TO'to Time Tl']
As illustrated in FIG. 16, the reception control unit 1404 sets the reception
selection signal (RSEL) to Low at Time TO' to select the first decoding circuit 1402
in the idle period before reception of data, so that the idle frame as illustrated in FIG.
25 15B is received.
[Time Tl'to Time T3']
The reception control unit 1404 starts reception of the next coding frame at
Time Tl'. The serial receiver 1401 outputs four encoded symbols to the second
48
decoding circuit 1403 for every five cycles of the PCLK, and provides the standby
time in the first cycle. The reception control unit 1404 performs control so that the
COM as the fi-ame synchronization symbol is received only in the standby time,
such as Time Tl', at the beginning of the coding frame.
5 [0115]
The reception control unit 1404 can perform control so that 33 control
characters (RXCs) corresponding to a coding frame are received in a cycle time of
40 cycles of the PCLK, i.e. in a period between Time Tl' and Time T3'. Upon
completion of reception of the SOP frame as illustrated in FIG. 15C at Time T3', the
10 reception control unit 1404 switches the reception selection signal (RSEL) to High.
[At and After Time T3']
The serial receiver 1401 receives, as input, a 66-bit encoded block, at a time,
of the serial data via the serial channel 121 at and after Time T3'. The serial receiver
1401 consecutively outputs 64-bit valid data, which has been generated by removing
15 the synchronization header (SYNC) from the encoded block input thereto, to the
second decoding circuit 1403 in a cycle time of eight cycles of the PCLK. The
reception control unit 1404 outputs, as the reception data, the data character (RXD)
generated as a result of descrambling by the second decoding circuit 1403 via the
reception bus (RBUS).
20 [0116]
The following describes a transition operation to the idle period of the
transmitting circuit 1300 and the receiving circuit 1400 in the third modification.
FIG. 17 is a timing diagram illustrating the transition operation.

25 [Time T3 to Time T5]
As illustrated in FIG. 17, at and after Time T3, the transmission control unit
1303 sets the termination identifying signal (TERM) to Non-Terminating, and
performs control so that transmission of the non-terminating block (NTBLK) is
49
continued. At Time T4, the transmission control unit 1304 switches the termination
identifying signal (TERM) to Terminating, and performs control so that the
terminating block (TBLK) is transmitted as the last encoded block of the
transmission data.
5 [At and After Time T5]
Upon completion of the transmission of the terminating block (TBLK) at
Time T5, the transmitting circuit 1300 switches the transmission selection signal
(TSEL) to Low to select the first encoding circuit 1301. Thereafter, the transmitting
circuit 1300 transmits the EOP frame as illustrated in FIG. 15D. Upon completion of
10 the transmission of the EOP frame at Time T6, the transmitting circuit 1300
repeatedly transmits the idle frame as illustrated in FIG. 15B and transitions to the
idle period.

[Time T3'to Time T5']
15 As illustrated in FIG. 17, since reception of the non-terminating block
(NTBLK) is continued at and after Time T3', the reception control imit 1404 sets the
termination identifying signal (TERM) to Non-Terminating. Upon reception of the
terminating block (TBLK) at Time T4', the reception control unit 1404 switches the
termination identifying signal (TERM) to Terminating, and detects an end of
20 reception data.
[At and After Time T5']
When the reception of the terminating block (TBLK) is completed at Time
T5', the reception control unit 1404 switches the reception selection signal (RSEL)
to Low to select the first decoding circuit, and then performs control so that the EOP
25 frame as illustrated in FIG. 15D is received. The reception control unit 1404
performs control so that the idle frame as illusfrated in FIG. 15D is repeatedly
received at and after Time T6' at which the reception of the EOP frame is completed,
so that the receiving circuit 1400 transitions to the idle period.
50

In the third modification, by adding the synchronization header (SYNC)
"10" or "01", each encoded block includes a bit transition from 0 to 1 or from 1 to 0
at least one time. It is therefore possible to limit the run-length of the transmission
5 data. Furthermore, in the third modification, by using the non-terminating
synchronization header (NTSYNC) or the terminating synchronization header
(TSYNC) as the synchronization header (SYNC), a timing at which the data
transmission is completed is shared between the transmitting circuit 1300 and the
receiving circuit 1400. With this structure, it becomes unnecessary to share a packet
10 size in advance in the third modification.
[0117]

While the embodiment of the transmitting circuit, the receiving circuit, and
the communication system including the transmitting circuit and the receiving
15 circuit according to the present invention has been described above, the
above-exemplified communication system may be modified as described below. The
present invention is in no way limited to the commimication system as described in
the above-mentioned embodiment.
(1) In the embodiment described above, the 8B/10B coding is taken as an
20 example of the first channel coding. The first channel coding, however, is not
limited to the 8B/10B coding, and may be any scheme as long as it is symbol
mapping in which m-bit data is mapped to n-bit data. In addition, the first channel
coding may be any scheme as long as it is a coding scheme that can achieve early
establishment of synchronization. Similarly, the 64B/66B coding is taken as an
25 example of the second channel coding. The second channel coding, however, is not
limited to the 64B/66B coding, and may be any scheme as long as it is a scheme
having less coding loss than the first channel coding even though establishment of
synchronization is slower than the first channel coding.
51
(2) In the embodiment described above, the scrambler and the descrambler
are respectively described as the self-synchronizing scrambler and the
self-synchronizing descrambler. The scrambler and the descrambler, however, may
not be the self-synchronizing scrambler and the self-synchronizing descrambler,
5 respectively. That is to say, the scrambler and the descrambler each may set each of
the shift registers (SO to S39 and DO to D39) included in the respective circuits to
have a predetermined default value according to a timing at which the transmittmg
circuit switches the encoding circuit to the second encoding circuit 202 and the
receiving circuit switches the decoding circuit to the second decoding circuit 303.
10 [0118]
As for the setting of the default value, in the transmitter, the second
encoding circuit 202 may hold in advance a default value to be stored in each of the
shift registers included in the scrambler and set each of the shift registers to have the
default value according to the timing described above. Alternatively, the
15 transmission control unit 203 may provide the setting.
[0119]
Similarly, in the receiver, the second decoding circuit 303 may hold in
advance a default value to be stored in each of the shift registers included in the
descrambler and set each of the shift registers to have the default value according to
20 the timing described above. Alternatively, the reception control unit 304 may
provide the setting.
(3) In the embodiment described above, the detection circuit included in the
receiving circuit detects the Low fixed signal and the High fixed signal fi-om
differential amplitude based on potentials on both signal lines constituting a serial
25 chimnel. The detection circuit may detect the Low fixed signal and the High fixed
signal in another way.
[0120]
For example, the detection circuit may detect a potential on only one of the
52
signal lines constituting the serial channel. The transmitter outputs the Low fixed
signal, which is a signal whose potential is fixed to Low, and the High fixed signal,
which is a signal whose potential is fixed to High. Note that the detection circuit is
configured to distinguish the control character fi-om the Low fixed signal and the
5 High fixed signal. To this end, the transmitter is configured to output the Low fixed
signal and the High fixed signal for a longer time than continuously-output control
characters having the same value. For example, in the 8B/10B coding, the same
value is never continuously output for six or more clocks. The transmitter caa cause
the receiver to recognize the Low fixed signal and the High fixed signal by
10 outputting the Low fixed signal and the High fixed signal for six or more clocks.
The present invention may have the above-mentioned structure so that the Low fixed
signal and the High fixed signal are detected.
(4) The generating polynomial indicated in the embodiment described above
is just one example. Another generating polynomial may be used as long as the same
15 generating polynomial is shared between the transmitter and the receiver.
(5) In the third modification described above, the fi-ame synchronization
symbol (F) included in the coding fi-ame is not limited to the COM symbol (K28.5).
The fi-ame synchronization symbol (F) included in the coding frame may be any
symbol as long as it defines a boundary between coding frames shared between the
20 transmitter and the receiver. The frame synchronization symbol (F) may be at any
position as long as it is at a predetermined position. The position of the frame
synchronization symbol (F) is not limited to the beginning of the coding frame. For
example, the frame synchronization symbol (F) can define a boundary between
coding frames as shown in the modification described above by adding the same
25 symbol as the second symbol included in the last symbol set (SS15) to the end of the
coding frame. The frame synchronization symbol (F) may be inserted into the
coding frame. Specifically, the frame synchronization symbol (F) may define a
boundary between coding frames by sharing, between the transmitter and the
53
receiver, symbol sets between which the frame synchronization symbol (F) is
inserted.
(6) In the third modification described above, symbol sets included in the
SOP frame illustrated in FIG. 15C and symbol sets included in the EOF frame
5 illustrated in FIG. 15D are not limited to the LIDLs. Another symbol set may be used
in place of the LIDL. For example, in place of the LIDLs, the SOPs may further be
included in the SOP frame so as to address such a problem that the receiver cannot
accurately receive the last SOP (SSI5) due to a communication error or other causes.
Similarly, in place of the LIDLs, the EOPs may further be included in the EOP
10 frame so as to address such a problem that the receiver cannot accurately receive the
last EOP (SSO) due to a communication error or other causes.
[0121]
Alternatively, with the structure in which the system fransitions to the
power-saving state as shown in the second modification, the SOP frame may include
15 the SYNCs described in the second modification in place of all the LIDLs. With the
above-mentioned structure, establishment of symbol synchronization and
notification of a start position of a packet can be achieved by only one SOP frame.
[0122]
The last symbol set (SSI5) of the EOP frame may be the SOP so that
20 continuous data transmission is achieved. That is to say, one coding frame may be
provided with the function as the EOP and the function as the SOP.
(7) In the embodiment described above, in the communication system
illustrated in FIG. 1, a clock channel may be provided between the host device 100
and the target device 110 so that a reference clock for generating various clocks may
25 be shared between the PEL 108 and the PEL 113.
(8) In the embodiment described above, the serial data is transmitted via the
serial channel in differential signaling. The method for transmitting the serial data
via the serial channel may not be limited to the differential signaling, and may be
54
another method such as a single-ended signaling.
(9) Specific examples of the back-end unit included in the target device in
the embodiment described above are as follows. For example, in a case where the
target device is a semiconductor memory card, nonvolatile memory and a controller
5 therefor fall under the back-end unit. In this case, a drive for a nonvolatile memory
card installed in a PC falls under the host device 100. In a case where the target
device is a communication device, a communication module including an RF (Radio
Frequency) transceiver, a baseband circuit, and an MAC (Media Access Control)
circuit and the like fall under the back-end unit. Suppose that the target device 110
10 performs simplex high-speed transmission with the host device 100, as exemplified
by a display device and a camera device. In this case, depending on a transmission
direction, the interface circuit included in each of the host device 100 and the target
device 110 may include only one of the transmitting circuit and the receiving circuit.
(10) Each of the transmitting circuit and the receiving circuit described in
15 the above embodiment may be implemented as a circuit for performing the function
described above, or may be implemented by one or more processors executing a
program. The communication system described in the embodiment may be
configured as a package of an IC, LSI, and other integrated circuits. The package is
provided for use by being incorporated into^ various devices. With this structure, the
20 various devices can achieve functions described in the embodiment and
modifications.
(11) A control program including a program code for causing a processor
such as the host device and the target device, and various circuits connected to the
processor to perform operations pertaining to the communications, processing to
25 switch between encoding circuits and processing to switch between decoding
circuits described in the above embodiment may be recorded on a recording medium,
or may be circulated or distributed via various communication channels. Examples
of the recording medium are an IC card, a hard disk, an optical disc, a flexible disk,
55
ROM, and flash memory. The control program thus circulated or distributed is
provided for use by being stored in memory and the like readable to a processor. By
the processor executing the control program, various functions described in the
embodiment are achieved.
5
The following describes the structures, the modifications, and the effects of
the transmitting circuit, the receiving circuit, and the communication system as one
embodiment of the present invention.
(1) The first transmitting circuit according to the present invention is a
10 transmitting circuit that performs channel coding and transmits channel-coded serial
data to a receiving circuit via a serial channel, comprising: a first encoding circuit
configured to perform first channel coding in which an m-bit control character is
mapped to an n-bit (m < n) encoded symbol; a second encoding circuit configured to
perform second channel coding in which a bit pattern of a data character is
15 randomized by scrambling to generate an encoded block, the second channel coding
taking more time in establishing synchronization with the receiving circuit and
having less coding loss than the first channel coding; a transmission control unit
configured to select one of the first encoding circuit and the second encoding circuit
to be used for transmission; and a serial driver configured to, when the transmission
20 control unit selects the first encoding circuit, convert the encoded symbol generated
by the first encoding circuit into serial data and transmit the serial data via the serial
channel, and to, when the transmission control unit selects the second encoding
circuit, convert the encoded block generated by the second encoding circuit into
serial data and transmit the serial data via the serial channel, wherein the
25 transmission control unit selects the first encoding circuit in a period for not
transmitting the data character, and selects the second encoding circuit in a period
for transmitting the data character.
[0123]
56
With this structure, in an idle period not influencing the transmission
efficiency, the transmitting circuit can select the first encoding circuit configured to
perform channel coding having large coding loss but achieving early establishment
of synchronization. In a period for transmitting the encoded block generated based
5 on the data character, i.e. a packet payload, the transmitting circuit can select the
second encoding circuit configured to perform channel coding having less coding
loss and higher transmission efficiency than the first channel coding.
(2) In the second transmitting circuit according to the above-mentioned first
transmitting circuit, in the period for not transmitting the data character, the
10 transmission control unit puts the serial driver into a power-saving state, and when
restoring the serial driver from the power-saving state so as to cause the serial driver
to transmit the data character, the transmission control unit controls, prior to
transmission of the data character, the serial driver to continue transmitting a
synchronization symbol determining a synchronization timing defined in the first
15 channel coding for a predetermined time period and to transmit an encoded symbol
indicating a start position of the data character, in a state where the first encoding
circuit is selected, and then switches fi"om the first encoding circuit to the second
encoding circuit.
[€124]
20 With this structure, even when the transmitting circuit is put into the
power-saving state in the idle period, early establishment of symbol synchronization
with the receiver is achieved by transmitting the control character by performing the
first channel coding, and packet transmission is achieved with high efficiency by
switching the encoding circuit to the second encoding circuit.
25 (3) In the third transmitting circuit according to the above-mentioned first
transmitting circuit, the second encoding circuit generates the encoded block by
scrambling the data character of consecutive m bits into an m-bit encoded block
according to a predetermined scrambling polynomial.
57
[0125]
With this structure, the transmitting circuit can switch between the first
encoding circuit and the second encoding circuit while performing control so that a
speed at which the encoded symbol is transmitted matches a speed at which the
5 encoded block is transmitted.
(4) In the fourth transmitting circuit according to the above-mentioned third
transmitting circuit, the serial driver converts encoded symbols in units of coding
frames, the number of bits constituting each coding frame being equal to the least
common multiple of the number of bits constituting each of the encoded symbols
10 and the number of bits constituting the encoded block.
[0126]
With this structure, it is possible to perform communications while readily
absorbing the difference in timing resuUing from the difference in size of
transmission data between the first channel coding and the second channel coding.
15 (5) In the fifth transmitting circuit according to the above-mentioned fourth
transmitting circuit, the transmission control unit switches from the first encoding
circuit to the second encoding circuit upon transmission of a coding frame including
an encoded symbol indicating a start position of the data character.
[0127]
20 With this structure, the transmitting circuit can appropriately switch from
the first encoding circuit to the second encoding circuit.
(6) In the sixth transmitting circuit according to the above-mentioned first
transmitting circuit, the second encoding circuit generates the encoded block by
scrambling the data character of consecutive n bits into an n-bit encoded block
25 according to a predetermined scrambling polynomial.
[0128]
With this structure, in a case where the bit length of the data character is the
same as the bit length of the encoded symbol, the transmitting circuit does not
58
require the standby time and the like to control the speed at which serial data is
processed and the speed at which parallel data is processed. The transmitting circuit
can therefore easily switch between the first encoding circuit and the second
encoding circuit.
5 (7) In the seventh transmitting circuit according to the above-mentioned
first transmitting circuit, the second encoding circuit generates encoded blocks by
scrambling n bits, at a time, of consecutively-input m-bit data characters into an
n-bit encoded block according to a predetermined scrambling polynomial.
[0129]
10 With this structure, in a case where the bit length of the data character is the
same as the bit length of the encoded symbol, the transmitting circuit does not
require the standby time and the like to control the speed at which serial data is
processed and the speed at which parallel data is processed. The transmitting circuit
can therefore easily switch between the first encoding circuit and the second
15 encoding circuit.
(8) In the eighth transmitting circuit according to the above-mentioned sixth
or seventh transmitting circuit, the transmission control unit switches fi"om the first
encoding circuit to the second encoding circuit upon transmission of an encoded
symbol indicating a start position of the data character.
20 [0130]
With this structure, the transmitting circuit can switch fi-om the first
encoding circuit to the second encoding circuit according to an appropriate timing.
(9) In the ninth transmitting circuit according to the above-mentioned eighth
'^ transmitting circuit, the transmission control unit switches fi-om the second encoding
25 circuit to the first encoding circuit upon transmission of an encoded block
terminating a predetermined number of data characters.
[0131]
With this structure, upon transmission of the encoded block, the transmitting
59
circuit can easily switch between the first encoding circuit and the second encoding
circuit without the need for extra data.
(10) In the tenth transmitting circuit according to the above-mentioned first
transmitting circuit, the second encoding circuit generates the encoded block by
5 scrambling a predetermined number of consecutive data characters and adding an
s-bit synchronization header to the predetermined number of consecutive data
characters.
[0132]
With this structure, in a case where the synchronization header is added by
10 the second encoding circuit, the transmitting circuit can switch from the first
encoding circuit to the second encoding circuit while performing control so that the
speed at which the encoded symbol is transmitted matches the speed at which the
encoded block is transmitted.
(11) In the eleventh transmitting circuit according to the above-mentioned
15 tenth transmitting circuit, the synchronization header is two-bit or longer additional
information including a bit transition fi-om 0 to 1 or from 1 to 0 at least one time, the
synchronization header includes a non-terminating synchronization header added to
an encoded block not terminating the predetermined number of consecutive data
characters, and a terminating synchronization header added to an encoded block
20 terminating the predetermined number of consecutive data characters, and the
transmission control unit switches from the first encoding circuit to the second
encoding circuit upon transmission of the encoded block to which the terminating
synchronization header has been added.
[0133]
25 With this structure, the transmitting circuit can clearly notify the receiving
circuit as a communication partner of the end of the encoded block generated based
on the data character, i.e. the packet payload.
(12) In the twelfth transmitting circuit according to the above-mentioned
60
first transmitting circuit, the transmission control unit performs control so that a
sequence of encoded symbols output from the first encoding circuit is input into the
second encoding circuit in the period for not transmitting the data character, and the
second encoding circuit initializes a scrambler by using the sequence of the encoded
5 symbols.
[0134]
With this structure, the transmitting circuit can initialize the scrambler with
use of data determined in advance to be used, without the need for extra data.
(13) The first receiving circuit according to the present invention is a
10 receiving circuit that receives channel-coded serial data from a transmitting circuit
via a serial channel, the channel-coded serial data being obtained by either first
channel coding in which an m-bit control character is mapped to an n-bit (m < n)
encoded symbol or second channel coding in which a bit pattern of a data character
is randomized by scrambling to generate an encoded block, the second channel
15 coding taking more time in establishing synchronization and having less coding loss
than the first channel coding, the receiving circuit comprising: a first decoding
circuit configured to decode the encoded symbol into the control character; a second
decoding circuit configured to decode the encoded block into the data character by
descrambling; a reception control unit configured to select one of the first decoding
20 circuit and the second decoding circuit to be used for reception; and a serial receiver
configured to convert the channel-coded serial data received via the serial channel
into parallel data, and output the parallel data to one of the first decoding circuit and
the second decoding circuit selected by the reception confrol unit, wherein the
reception control imit selects the first decoding circuit in a period for not receiving
25 the encoded block, and selects the second decoding circuit in a period for receiving
the encoded block.
[0135]
With this structure, in the idle period not influencing the fransmission
61
efficiency, the receiving circuit can select the first decoding circuit configured to
perform channel coding having large coding loss but achieving early establishment
of synchronization. In the period for transmitting the encoded block generated based
on the data character, i.e. the packet payload, the receiving circuit can select the
5 second decoding circuit configured to perform channel coding having less coding
loss and higher transmission efiiciency than the first channel coding.
(14) In the second receiving circuit according to the above-mentioned first
receiving circuit, the reception control unit selects the first decoding circuit at
initialization and restoration from a power-saving state, and the reception control
10 unit switches from the second decoding circuit to the first decoding circuit upon
reception of an encoded symbol indicating an end position of a packet or upon
reception of a predetermined number of encoded blocks.
[0136]
With this structure, the receiving circuit can appropriately select one of the
15 first decoding circuit and the second decoding circuit, and receive the data character
transmitted after performing channel coding having little coding loss.
(15) In the third receiving circuit according to the above-mentioned first
receiving circuit, the reception control unit switches from the first decoding circuit
to the second decoding circuit upon reception of an encoded symbol indicating a
20 start position of a packet.
[0137]
With this structure, the receiving circuit can appropriately switch from the
fu"st decoding circuit to the second decoding circuit, and receive the data character.
(16) In the fourth receiving circuit according to the above-mentioned first
25 receiving circuit, while selecting the first decoding circuit, the reception control unit
puts the serial receiver into a power-saving state upon reception of a signal
requesting transition to the power-saving state via the serial channel, and when the
serial receiver is restored from the power-saving state upon reception of a signal
62
requesting restoration from the power-saving state from the transmitting circuit via
the serial channel, and synchronization is established upon reception of a
synchronization symbol requesting establishment of synchronization a plurality of
times, the reception control unit switches, upon reception of an encoded symbol
5 indicating a start position of a packet, from the first decoding circuit to the second
decoding circuit according to a timing indicated by the start position.
[0138]
Even when the receiving circuit is put into the power-saving state in the idle
period, early establishment of symbol synchronization is achieved by receiving the
10 control character by performing the first channel coding, and packet reception is
achieved with high efficiency by switching the decoding circuit to the second
decoding circuit.
(17) In the fifth receiving circuit according to the above-mentioned first
receiving circuit, the second decoding circuit descrambles an m-bit encoded block
15 input from the serial receiver into an m-bit data character according to a
predetermined scrambling polynomial.
[0139]
With this structure, the receiving circuit can switch from the first decoding
circuit to the second decoding circuit while performing confrol so that the speed at
20 which the encoded symbol is transmitted matches the speed at which the encoded
block is transmitted.
(18) In the sixth receiving circuit according to the above-mentioned first
receiving circuit, the second decoding circuit descrambles an n-bit encoded block
input from the serial receiver into an n-bit data character according to a
25 predetermined scrambling polynomial.
[0140]
With this structure, in a case where the bit length of the data character is the
same as the bit length of the encoded symbol, the receiving circuit does not require
63
the standby time and the like to control the speed at which serial data is processed
and the speed at which parallel data is processed. The receiving circuit can therefore
easily switch between the first decoding circuit and the second decoding circuit.
(19) In the seventh receiving circuit according to the above-mentioned first
5 receiving circuit, the second decoding circuit decodes n-bit encoded blocks
consecutively input fi-om the serial receiver into a sequence of m-bit data characters
by descrambling according to a predetermined scrambling polynomial.
[0141]
With this structure, in a case where the bit length of the encoded symbol is
10 the same as the bit length of the encoded block, the receiving circuit can easily
switch between the first decoding circuit and the second decoding circuit without the
need for extra data.
(20) In the eighth receiving circuit according to the above-mentioned first
receiving circuit, the encoded block has been generated by scrambling a
15 predetermined number of consecutive data characters and adding an s-bit
synchronization header to the predetermined number of consecutive data characters,
and the second decoding circuit removes the synchronization header from each of
encoded blocks consecutively input fi-om the serial receiver, and decodes each of the
encoded blocks fi-om which the synchronization header has been removed into the
20 predetermined number of consecutive data characters by descrambling according to
a predetermined scrambling polynomial.
[0142]
With this structure, in a case where the second decoding circuit decodes the
encoded block to which the synchronization header has been added, the receiving
25 circuit can switch from the first decoding circuit to the second decoding circuit
while performing control so that the speed at which the encoded symbol is
transmitted matches the speed at which the encoded block is transmitted.
(21) In the ninth receiving circuit according to the above-mentioned eighth
64
receiving circuit, the synchronization header is two-bit or longer information
including a bit transition from 0 to 1 or from 1 to 0 at least one time, the
synchronization header includes a non-terminating synchronization header used for
an encoded block not terminating the predetermined number of data characters, and
5 a terminating synchronization header used for an encoded block terminating the
predetermined number of data characters, and the reception control unit switches
from the second decoding circuit to the first decoding circuit upon reception of an
encoded block including the terminating synchronization header.
[0143]
10 With this structure, the receiving circuit can clearly detect the end of the
encoded block generated based on the data character, i.e. the packet payload.
(22) In the tenth receiving circuit according to the above-mentioned first
receiving circuit, the serial receiver converts the serial data into encoded symbols in
units of coding frames, the number of bits constituting each coding frame being
15 equal to the least common multiple of the number of bits constituting each of the
encoded symbols and the number of bits constituting the encoded block.
[0144]
With this structure, the receiving circuit can perform conversion into the
encoded symbol without caring the difference in timing resulting from the difference
20 in size of fransmission data between the first channel coding and the second channel
coding.
(23) In the eleventh receiving circuit according to the above-mentioned first
receiving circuit, the reception control unit performs control so that a sequence of
encoded symbols input into the first decoding circuit is also input into the second
25 decoding circuit in the period for not receiving the encoded block, and the second
decoding circuit initializes a descrambler by using the sequence of the encoded
symbols.
[0145]
65
With this structure, the receiving circuit can initialize the descrambler with
use of data determined in advance to be used, without the need for extra data.
(24) The first communication system according to the present invention is a
communication system that transmits channel-coded serial data from a transmitting
5 circuit to a receiving circuit via a serial channel, wherein the transmitting circuit
includes: a first encoding circuit configured to perform first channel coding in which
an m-bit control character is mapped to an n-bit (m < n) encoded symbol; a second
encoding circuit configured to perform second channel coding in which a bit pattern
of a data character is randomized by scrambling to generate an encoded block, the
10 second channel coding taking more time in establishing synchronization with the
receiving circuit and having less coding loss than the first channel coding; a
transmission control unit configured to select one of the first encoding circuit and
the second encoding circuit to be used for transmission; and a serial driver
configured to, when the transmission control unit selects the first encoding circuit,
15 convert the encoded symbol generated by the first encoding circuit into serial data
and transmit the serial data via the serial channel, and to, when the transmission
control unit selects the second encoding circuit, convert the encoded block generated
by the second encoding circuit into serial data and transmit the serial data via the
serial channel, the transmission control unit selects the first encoding circuit in a
20 period for not transmitting the data character, and selects the second encoding circuit
in a period for transmitting the data character, the receiving curcuit includes: a first
decoding circuit configured to decode the encoded symbol into the control character;
a second decoding circuit configured to decode the encoded block into the data
character by descrambling; a reception control unit configured to select one of the
25 first decoding circuit and the second decoding circuit to be used for reception; and a
serial receiver configured to convert the channel-coded serial data received via the
serial channel into parallel data, and output the parallel data to one of the first
decoding circuit and the second decoding circuit selected by the reception control
66
unit, and the reception control unit selects the first decoding circuit in a period for
not receiving the encoded block, and selects the second decoding circuit in a period
for receiving the encoded block.
[0146]
5 The first communication method for use in the first communication system
according to the present invention is a communication method for use in a
communication system that transmits channel-coded serial data fi"om a transmitting
circuit to a receiving circuit via a serial channel, wherein channel codmg includes:
first channel coding in which an m-bit control character is mapped to an n-bit (m <
10 n) encoded symbol; and second channel coding in which a bit pattern of a data
character is randomized by scrambling to generate an encoded block, the second
channel coding takes more time in establishing synchronization between the
transmitting circuit and the receiving circuit, and has less coding loss than the first
channel coding, and the communication method for use in the communication
15 system transmits the channel-coded serial data while switching between the first
channel coding and the second channel coding, and uses the first channel coding in a
period for not transmitting the encoded block, and uses the second channel coding in
a period for transmitting the encoded block.
[0147]
20 With this structure, in the idle period not influencing the transmission
efficiency, the communication system can select the first encoding circuit configured
to perform channel coding having large coding loss but achieving early
establishment of synchronization. In the period for transmitting the encoded block
generated based on the data character, i.e. the packet payload, the communication
25 system can select the second encoding circuit configured to perform chaimel coding
having less coding loss and higher transmission efficiency than the first channel
coding.
[Industrial Applicability]
67
[0148]
The transmitting circuit, the receiving circuit, and the communication
system including both of the circuits according to the present invention are each
usable, as a circuit system that achieves early establishment of symbol
5 synchronization while suppressing reduction of coding efficiency, in devices
between which data transmission is performed.
[Reference Signs List]
[0149]
100 host device
10 101 data processing unit
102 interface circuit
103 transmitting circuit
104 PLL
105 receiving circuit
15 106 D0+terminal
107 DO-terminal
108 D1+terminal
109 Dl-terminal
110 target device
20 111 back-end unit
112 interface circuit
113 receiving circuit
114 PLL
115 transmitting circuit
25 116 D0+terminal
117 DO-terminal
118 D1+terminal
119 Dl-terminal
68
121,122 serial channel
201 first encoding circuit
202 second encoding circuit
203 transmission control unit
5 204 serial driver
205 serializer (SER)
206 differential driver
301 serial driver
302 first decoding circuit
10 303 second decoding circuit
304 reception control unit
305 differential receiver
306 de-serializer
307 detection circuit
15
69

CLAIMS
1. A transmitting circuit that performs channel coding and transmits channel-coded
serial data to a receiving circuit via a serial channel, comprising:
5 a first encoding circuit configured to perform first channel coding in which
an m-bit control character is mapped to an n-bit (m < n) encoded symbol;
a second encoding circuit configured to perform second channel coding in
which a bit pattern of a data character is randomized by scrambling to generate an
encoded block, the second channel coding taking more time in establishing
10 synchronization with the receiving circuit and having less coding loss than the first
channel coding;
a transmission control unit configured to select one of the first encoding
circuit and the second encoding circuit to be used for transmission; and
a serial driver configured to, when the transmission control unit selects the
15 first encoding circuit, convert the encoded symbol generated by the first encoding
circuit into serial data and transmit the serial data via the serial channel, and to,
when the transmission control unit selects the second encoding circuit, convert the
encoded block generated by the second encoding circuit into serial data and transmit
the serial data via the serial channel, wherein
20 the transmission control unit selects the first encoding circuit in a period for
not transmitting the data character, and selects the second encoding circuit in a
period for transmitting the data character.
2. The transmitting circuit of Claim 1, wherein
25 in the period for not transmitting the data character, the transmission control
unit puts the serial driver into a power-saving state, and
when restoring the serial driver fi"om the power-saving state so as to cause
the serial driver to transmit the data character, the transmission control unit
70
controls, prior to transmission of the data character, the serial driver
to continue transmitting a synchronization symbol determining a synchronization
timing defined in the first channel coding for a predetermined time period and to
transmit an encoded symbol indicating a start position of the data character, in a
5 state where the first encoding circuit is selected, and then
switches fi-om the first encoding circuit to the second encoding
circuit.
3. The transmitting circuit of Claim 1, wherein
10 the second encoding circuit generates the encoded block by scrambling the
data character of consecutive m bits into an m-bit encoded block according to a
predetermined scrambling polynomial.
4. The transmitting circuit of Claim 3, wherein
15 the serial driver converts encoded symbols in units of coding fi-ames, the
number of bits constituting each coding fi-ame being equal to the least common
multiple of the number of bits constituting each of the encoded symbols and the
number of bits constituting the encoded block.
20 5. The transmitting circuit of Claim 4, wherein
the transmission control unit switches from the first encoding circuit to the
second encoding circuit upon transmission of a coding fi-ame including an encoded
symbol indicating a start position of the data character.
25 6. The transmitting circuit of Claim 1, wherein
the second encoding circuit generates the encoded block by scrambling the
data character of consecutive n bits into an n-bit encoded block according to a
predetermined scrambling polynomial.
71
7. The transmitting circuit of Claim 1, wherein
the second encoding circuit generates encoded blocks by scrambling n bits,
at a time, of consecutively-input m-bit data characters into an n-bit encoded block
5 according to a predetermined scrambling polynomial.
8. The transmitting circuit of Claim 6 or 7, wherein
the transmission control unit switches from the first encoding circuit to the
second encoding circuit upon transmission of an encoded symbol indicating a start
10 position of the data character.
9. The transmitting circuit of Claim 8, wherein
the transmission control unit switches from the second encoding circuit to
the first encoding circuit upon transmission of an encoded block terminating a
15 predetermined number of data characters.
10. The fransmitting circuit of Claim 1, wherein
the second encoding circuit generates the encoded block by scrambling a
predetermined number of consecutive data characters and adding an s-bit
20 synchronization header to the predetermined number of consecutive data characters.
11. The transmitting circuit of Claim 10, wherein
the synchronization header is two-bit or longer additional information
including a bit transition from 0 to 1 or from 1 to 0 at least one tune,
25 the synchronization header includes a non-terminating synchronization
header added to an encoded block not terminating the predetermined number of
consecutive data characters, and a terminating synchronization header added to an
encoded block terminating the predetermined number of consecutive data characters,
72
and
the transmission control unit switches from the first encoding circuit to the
second encoding circuit upon transmission of the encoded block to which the
terminating synchronization header has been added.
5
12. The transmitting circuit of Claim 1, wherein
the transmission control unit performs control so that a sequence of encoded
symbols output from the first encoding circuit is input into the second encoding
circuit in the period for not transmitting the data character, and
10 the second encoding circuit initializes a scrambler by using the sequence of
the encoded symbols.
13. A receiving circuit that receives channel-coded serial data from a transmitting
circuit via a serial channel, the channel-coded serial data being obtained by either
15 first channel coding in which an m-bit control character is mapped to an n-bit (m <
n) encoded symbol or second channel coding in which a bit pattern of a data
character is randomized by scrambling to generate an encoded block, the second
channel coding taking more time in establishing synchronization and having less
coding loss than the first channel coding, the receiving circuit comprising:
20 a first decoding circuit configured to decode the encoded symbol into the
control character;
a second decoding circuit configured to decode the encoded block into the
data character by descrambling;
a reception control unit configured to select one of the first decoding circuit
25 and the second decoding circuit to be used for reception; and
a serial receiver configured to convert the channel-coded serial data
received via the serial channel into parallel data, and output the parallel data to one
of the first decoding circuit and the second decoding circuit selected by the reception
73
control unit, wherein
the reception control unit selects the first decoding circuit in a period for not
receiving the encoded block, and selects the second decoding circuit in a period for
receiving the encoded block.
5
14. The receiving circuit of Claim 13, wherein
the reception control unit selects the first decoding circuit at initialization
and restoration from a power-saving state, and
the reception control unit switches fi"om the second decoding circuit to the
10 first decoding circuit upon reception of an encoded symbol indicating an end
position of a packet or upon reception of a predetermined number of encoded
blocks.
15. The receiving circuit of Claim 13, wherein
15 the reception control unit switches from the first decoding circuit to the
second decoding circuit upon reception of an encoded symbol indicating a start
position of a packet.
16. The receiving circuit of Claim 13, wherein
20 while selecting the first decoding circuit, the reception control unit puts the
serial receiver into a power-saving state upon reception of a signal requesting
transition to the power-saving state via the serial channel, and
when the serial receiver is restored from the power-saving state upon
reception of a signal requesting restoration from the power-saving state from the
25 transmitting circuit via the serial channel, and synchronization is established upon
reception of a synchronization symbol requesting establishment of synchronization a
plurality of times, the reception control unit switches, upon reception of an encoded
symbol indicating a start position of a packet, from the first decoding circuit to the
74
second decoding circuit according to a timing indicated by the start position.
17. The receiving circuit of Claim 13, wherein
the second decoding circuit descrambles an m-bit encoded block input from
5 the serial receiver into an m-bit data character according to a predetermined
scrambling polynomial.
18. The receiving circuit of Claim 13, wherein
the second decoding circuit descrambles an n-bit encoded block input from
10 the serial receiver into an n-bit data character according to a predetermined
scrambling polynomial.
19. The receiving circuit of Claim 13, wherein
the second decoding circuit decodes n-bit encoded blocks consecutively
15 input from the serial receiver into a sequence of m-bit data characters by
descrambling according to a predetermined scrambling polynomial.
20. The receiving circuit of Claim 13, wherein
the encoded block has been generated by scrambling a predetermined
20 number of consecutive data characters and adding an s-bit synchronization header to
the predetermined number of consecutive data characters, and
the second decoding circuit removes the synchronization header from each
of encoded blocks consecutively input from the serial receiver, and decodes each of
the encoded blocks from which the synchronization header has been removed into
25 the predetermined number of consecutive data characters by descrambling according
to a predetermined scrambling polynomial.
21. The receiving circuit of Claim 20, wherein
75
the synchronization header is two-bit or longer information including a bit
transition from 0 to 1 or from 1 to 0 at least one time,
the synchronization header includes a non-terminating synchronization
header used for em encoded block not terminating the predetermined number of data
5 characters, and a terminating synchronization header used for an encoded block
terminating the predetermined number of data characters, and
the reception control unit switches from the second decoding circuit to the
first decoding circuit upon reception of an encoded block including the terminating
synchronization header.
10
22. The receiving circuit of Claim 13, wherein
the serial receiver converts the serial data into encoded symbols in units of
coding frames, the number of bits constituting each coding frame being equal to the
least common multiple of the number of bits constituting each of the encoded
15 symbols and the number of bits constituting the encoded block.
23. The receiving circuit of Claim 13, wherein
the reception control unit performs control so that a sequence of encoded
symbols input into the first decoding circuit is also input into the second decoding
20 circuit in the period for not receiving the encoded block, and
the second decoding circuit initializes a descrambler by using the sequence
of the encoded symbols.
24. A communication system that transmits channel-coded serial data from a
25 transmitting circuit to a receiving circuit via a serial channel, wherein
the transmitting circuit includes:
a first encoding circuit configured to perform first channel coding
in which an m-bit control character is mapped to an n-bit (m < n) encoded sjmibol;
76
a second encoding circuit configured to perform second channel
coding in which a bit pattern of a data character is randomized by scrambling to
generate an encoded block, the second channel coding taking more time in
establishing synchronization with the receiving circuit and having less coding loss
5 than the first channel coding;
a transmission control unit configured to select one of the first
encoding circuit and the second encoding circuit to be used for transmission; and
a serial driver configured to, when the transmission control unit
selects the first encoding circuit, convert the encoded symbol generated by the first
10 encoding circuit into serial data and transmit the serial data via the serial channel,
and to, when the transmission control unit selects the second encoding circuit,
convert the encoded block generated by the second encoding circuit into serial data
and transmit the serial data via the serial channel,
the transmission control unit selects the first encoding circuit in a period for
15 not transmitting the data character, and selects the second encoding circuit in a
period for transmitting the data character,
the receiving circuit includes:
a first decoding circuit configured to decode the encoded symbol
into the control character;
20 a second decoding circuit configured to decode the encoded block
into the data character by descrambling;
a reception control unit configured to select one of the first
decoding circuit and the second decoding circuit to be used for reception; and
a serial receiver configured to convert the channel-coded serial data
25 received via the serial channel into parallel data, and output the parallel data to one
of the first decoding circuit and the second decoding circuit selected by the reception
control imit, and
the reception control unit selects the first decoding circuit in a period for not
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receiving the encoded block, and selects the second decoding circuit in a period for
receiving the encoded block.
25. A communication method for use in a communication system that transmits
5 charmel-coded serial data from a transmitting circuit to a receiving circuit via a serial
channel, wherein
channel coding includes:
first channel coding in which an m-bit control character is mapped
to an n-bit (m < n) encoded symbol; and
10 second channel coding in which a bit pattern of a data character is
randomized by scrambling to generate an encoded block,
the second channel coding takes more time in establishing synchronization
between the transmitting circuit and the receiving circuit, and has less coding loss
than the first channel coding, and
15 the communication method for use in the communication system
transmits the chemnel-coded serial data while switching between the
first channel coding and the second channel coding, and
uses the first channel coding in a period for not transmitting the
encoded block, and uses the second channel coding in a period for transmitting the
20 encoded block.
26. A transmission method for use in a transmitting circuit that performs channel
coding and transmits channel-coded serial data to a receiving circuit via a serial
channel, the transmission method comprising:
25 a first encoding step of performing first channel coding in which an m-bit
control character is mapped to an n-bit (m < n) encoded symbol;
a second encoding step of performing second channel coding in which a bit
pattern of a data character is randomized by scrambling to generate an encoded
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block, the second channel coding taking more time in establishing synchronization
with the receiving circuit and having less coding loss than the first channel coding;
a transmission control step of controlling transmission by selecting one of
the first channel coding and the second channel coding to be used for transmission;
5 and
a transmission step of converting, when the transmission control step selects
the first channel coding, the encoded symbol generated by the first encoding step
into serial data and transmitting the serial data via the serial charmel, and converting,
when the transmission control step selects the second channel coding, the encoded
10 block generated by the second encoding step into serial data and transmitting the
serial data via the serial channel, wherein
the transmission control step selects the first channel coding in a period for
not transmitting the data character, and selects the second channel coding in a period
for transmitting the data character.
15
27. A reception method for use in a receiving circuit that receives channel-coded
serial data from a transmitting circuit via a serial channel, the channel-coded serial
data being obtained by either first channel coding in which an m-bit control
character is mapped to an n-bit (m < n) encoded symbol or second channel coding in
20 which a bit pattern of a data character is randomized by scrambling to generate an
encoded block, the second channel coding taking more time in establishing
synchronization and having less coding loss than the first channel coding, the
reception method comprising:
a first decoding step, by a first decoding circuit included in the receiving
25 circuit, of decoding the encoded symbol into the control character;
a second decoding step, by a second decoding circuit included in the
receiving circuit, of decoding the encoded block into the data character by
descrambling;
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a reception control step of selecting one of the first decoding circuit and the
second decoding circuit to be used for reception; and
an output step of converting the channel-coded serial data received via the
serial channel into parallel data, and outputting the parallel data to one of the first
5 decoding circuit and the second decoding circuit selected by the reception control
step, wherein
the reception control step selects the first decoding circuit in a period for not
receiving the encoded block, and selects the second decoding circuit in a period for
receiving the encoded block.