[0001]
　The present disclosure, transmission apparatus applied to the transmission of the data signal and the clock signal, the receiving apparatus, and communication system, and a signal transmission method, a signal receiving method, and a communication method.
Background technique
[0002]
　In recent years, such as in a portable device or a camera device such as a smart phone, the capacity of the image data proceeds and speed for data transmission within or between different devices the device, and low power consumption are required to handle. To meet this demand, as a connection interface for mobile devices and a camera device, MIPI (Mobile Industry Processor Interface) standards of high-speed interface standards such Alliance developed the C-PHY standard or D-PHY standard is underway . C-PHY standard or D-PHY standard physical layer of the communication protocol: an interface standard (physical layer PHY). Further, as the upper protocol layer of the C-PHY standard or D-PHY standard, DSI (Display Serial Interface) for the display of the mobile device and, CSI for a camera device (Camera Serial Interface) exists. Patent Document 1, a technique to stabilize the signal transmission D-PHY standard has been proposed.
CITATION
Patent Literature
[0003]
Patent Document 1: JP-T 2014-522204 Patent Publication
Summary of the Invention
[0004]
　The C-PHY standard or D-PHY standard described above, the transmission of the actual data signal fast: is used (High Speed ​​HS) differential signal. Further, the blanking period of the clock signal and data signal low power: is used (Low Power LP) signal. HS differential signal and LP signal are transmitted on a common transmission channel. For example, in the D-PHY standard, one transmission line for transmitting a clock signal and (clock lanes), one or more transmission path for transmitting the data signal (data lane) exists. The transmission period of the signal in each of the clock lane and the data lane, there is a period for performing transmission in a period and LP signal for transmission on the HS differential signal. In each of the clock lane and the data lanes, and the HS differential signal and LP signal are transmitted on a common transmission channel. However, LP signal is a single-ended signal rather than the differential signal, the voltage value required for signal transmission is different from the HS differential signal. Therefore, circuits for transmitting and receiving each of the HS differential signal and LP signal are required separately.
[0005]
　Transmission apparatus that can reduce power consumption during data transmission, the receiving device, and communication systems, as well as signal transmission method, to provide a signal receiving method, and a communication method preferable.
[0006]
　Transmission apparatus according to an embodiment of the present disclosure, a clock signal transmitting circuit for outputting a clock signal to a clock signal line, a data signal transmission circuit for outputting a data signal to the data signal line, in the blanking period of the data signal synchronization with, the clock signal line from the clock signal transmission circuit, as a predetermined blanking signal instead of the clock signal is outputted, in which a blanking control unit for controlling the clock signal transmission circuit.
[0007]
　Receiving apparatus according to an embodiment of the present disclosure, the data signal receiving circuit for receiving a data signal via a data signal line, a clock signal and a predetermined blanking that are output in synchronization with the blanking period of the data signal a ranking signal, in which a clock signal receiving circuit for receiving via a clock signal line.
[0008]
　Communication system according to an embodiment of the present disclosure outputs a clock signal to a clock signal line, and outputs the data signal to the data signal line, in synchronism with the blanking period of the data signal, instead of the clock signal by a predetermined a transmitting device for outputting a blanking signal, receives the data signal via a data signal line, in which a clock signal and a predetermined blanking signal and a receiver for receiving via a clock signal line .
[0009]
　Signal transmission method according to an embodiment of the present disclosure, and outputting a clock signal to a clock signal line, and outputting the data signal to the data signal line, in synchronism with the blanking period of the data signal, a clock to the signal line, it is intended to include and outputting a predetermined blanking signal instead of the clock signal.
[0010]
　Signal receiving method according to an embodiment of the present disclosure is to receive the data signals through the data signal line and a clock signal and data signal blanking period in synchronization with the output, predetermined blanking signals preparative, is intended to include a receiving via a clock signal line.
[0011]
　Communication method according to an embodiment of the present disclosure, and outputting a clock signal to a clock signal line, and outputting the data signal to the data signal line, in synchronism with the blanking period of the data signal, a clock signal line, and outputting a predetermined blanking signal instead of the clock signal, receiving a data signal via a data signal line, a clock signal and a predetermined blanking signal via a clock signal line receiving it is intended to include the method comprising.
[0012]
　Transmitting device or a communication system according to an embodiment of the present disclosure or, in the signal transmission method or communication method, in synchronism with the blanking period of the data signal, a clock signal line, a predetermined blanking instead of the clock signal signal is output.
[0013]
　Given the receiving device or communication system or a signal receiving method or a communication method, according to an embodiment of the present disclosure, via a clock signal line, a clock signal, which is output in synchronization with the blanking period of the data signal a blanking signal is received.
[0014]
　Transmitting device or a communication system according to an embodiment of the present disclosure or, according to a signal transmission method or communication method, in synchronism with the blanking period of the data signal, a clock signal line, a predetermined place of the clock signal since so as to output a blanking signal, it is possible to reduce the power consumption during data transmission.
[0015]
　Receiving device or communication system according to an embodiment of the present disclosure or, according to a signal receiving method or a communication method, via a clock signal line, a clock signal is output in synchronization with the blanking period of the data signal since was to receive a predetermined blanking signal, it is possible to reduce the power consumption during data transmission.
　Here, the advantages described in the present invention is not necessarily limited, it may be any of the effects described in the present disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016]
Is a block diagram showing an overview of a communication system for transmitting and [1] data signal and the clock signal.
Is a block diagram showing a configuration example of a communication system according to the comparative example [2] to realize the communication system shown in FIG.
3 is a circuit diagram showing a specific circuit configuration example of the communication system shown in FIG.
Is an explanatory diagram showing an example of each signal waveform to be transmitted to the clock lane data lane in the communication system shown in FIG. 4 FIG.
5 is a block diagram showing an overview of a communication system according to a first embodiment of the present disclosure.
It is a circuit diagram showing a specific circuit configuration example of the communication system shown in FIG. 6 FIG.
7 is an explanatory diagram showing an example of each signal waveform in the communication system shown in FIG. 5 is transmitted to the clock lane and the data lane.
8 is an explanatory diagram of a differential signal.
9 is a circuit diagram showing a specific circuit configuration example of a communication system according to the second embodiment.
It is an explanatory diagram showing an example of each signal waveform to be transmitted to the clock lane data lane in the communication system shown in FIG. 10 FIG.
11 is an explanatory diagram showing an example of each signal waveform is transmitted to the clock lane data lane in a communication system according to a first modification of the second embodiment.
FIG. 12 is an explanatory diagram showing an example of each signal waveform is transmitted to the clock lane data lane in a communication system according to a second modification of the second embodiment.
FIG. 13 is an explanatory diagram showing an example of each signal waveform is transmitted to the clock lane data lane in a communication system according to a third modification of the second embodiment.
FIG. 14 is an explanatory diagram showing an example of each signal waveform is transmitted to the clock lane data lane in a communication system according to a fourth modification of the second embodiment.
FIG. 15 is an explanatory diagram showing an example of each signal waveform is transmitted to the clock lane data lane in a communication system according to a fifth modification of the second embodiment.
16 is a block diagram showing an overview of a communication system according to the third embodiment.
Is a block diagram showing a specific application example of the communication system shown in FIG. 17 FIG. 16.
Is a flowchart showing an example of a data transmission process in the application example shown in FIG. 18 FIG. 17.
19 is a block diagram showing an overview of a communication system according to the fourth embodiment.
FIG. 20 is an explanatory diagram showing a first example of each signal waveform to be transmitted to the clock lane data lane in a communication system according to the fourth embodiment.
FIG. 21 is an explanatory diagram showing a second example of each signal waveform to be transmitted to the clock lane data lane in a communication system according to the fourth embodiment.
22 is a perspective view illustrating an example of the appearance of smartphones communication system is applied according to each embodiment.
FIG. 23 is a block diagram illustrating a configuration example of the application processor to the communication system is applied according to each embodiment.
FIG. 24 is a block diagram illustrating a configuration example of an image sensor communication system is applied according to each embodiment.
[FIG 25 is an explanatory diagram showing an example of an installation example of a vehicle-mounted camera that communication system is applied according to each embodiment.
FIG. 26 is a block diagram showing a configuration example of applying the communication system of the embodiments in the vehicle-mounted type of camera.
DESCRIPTION OF THE INVENTION
[0017]
　It will be described in detail with reference to the drawings, embodiments of the present disclosure. The description will be made in the following order.
　0. Communication system using LP signals and HS differential signal (Comparative Example) (FIGS.
　1-4) 1. First Embodiment (first example of a communication system using only HS differential signal) (FIGS. 5 to 7)
　2. (Second example of a communication system using only HS differential
　　signal) Second Embodiment 2.1 Configuration and Operation
　　(FIGS. 9-10) 2.2 Modification (FIGS. 11 to
　15) 3. Third Embodiment (two communication modes can be switched communication system) (FIGS. 16 to
　18) 4. Fourth Embodiment (Communication System is omitted termination control) (FIGS. 19 to
　21) 5. Application Example
　　5.1 the first application example (FIGS. 22 to
　　24) 5.2 second application example (FIGS. 25 to
　26) 6. Other Embodiments
[0018]
<0. Communication system> using LP signals and HS differential signal
　before describing the communication system of the present embodiment, firstly, as a comparative example, an outline of a communication system using the LP signal and the HS differential signal.
[0019]
　Figure 1 shows an overview of a communication system that supports, for example, in a communication interface of C-PHY standard or D-PHY standard. Communication system shown in FIG. 1 includes a transmitter TX, a receiver RX. Further, this communication system is straddling a transmitter TX and a receiver RX, includes a clock lane CL for transmitting a clock signal, for example, a data lane DL for transmitting data signals such as image data. In FIG. 1, as the data lanes DL, an example is shown having four data lanes DL1, DL2, DL3, DL4, the number of data lanes DL is not limited to this, for example, only one data lane DL1 it may be.
[0020]
　Transmitting unit TX includes a transmit digital circuit TX-DIGITAL, and a transmission analog circuit TX-ANALOG. In between the transmission digital circuit TX-DIGITAL a transmission analog circuit TX-ANALOG, such as a parallel signal of 16 bits or 8 bits are transmitted.
[0021]
　Receiver RX includes a receiving digital circuit RX-DIGITAL, a reception analog circuit RX-ANALOG. In data lanes DL1, DL2, DL3, DL4, in between the reception analog circuit RX-ANALOG and receiving digital circuit RX-DIGITAL, such as a parallel signal of 16 bits or 8 bits are transmitted. In clock lane CL, in between the reception analog circuit RX-ANALOG and receiving digital circuit RX-DIGITAL, for example, a serial signal of two bits are transmitted.
[0022]
　In clock lane CL, between the transmission analog circuit TX-ANALOG a reception analog circuit RX-ANALOG is connected with the clock signal line 30 for transmitting a clock signal of the differential. In data lanes DL1, DL2, DL3, DL4, between the transmission analog circuit TX-ANALOG a reception analog circuit RX-ANALOG is connected with the data signal lines 31, 32, 33, 34 for transmitting the data signal of the differential ing. Each of the clock signal line 30 and the data signal lines 31, 32, 33, 34, and a pair of positive signal line Dp and the negative signal line Dn for transmitting differential signals. Respectively to the clock signal line 30 and the data signal lines 31, 32, 33, 34, for example a serial signal of two bits are transmitted.
[0023]
　Figure 2 implements the communication system shown in FIG. 1 shows an exemplary configuration of a communication system according to a comparative example. In FIG. 2, as a data lane DL in FIG. 1 shows only one data lane DL1, other data lanes DL2, DL3, DL4 may be substantially similar configuration for,
[0024]
　Communication system according to this comparative example includes a transmission unit 101 corresponding to the transmission unit TX of Fig. 1, a receiving section 102 which corresponds to the receiver RX of Fig.
[0025]
　In clock lane CL, the transmission unit 101 includes a CL-HS circuit 111 for processing HS differential signal, and a CL-LP circuit 112 for processing LP signals. In data lanes DL1, the transmission unit 101 includes a DL-HS circuit 113 for processing HS differential signal, a DL-LP circuit 114 for processing LP signals.
[0026]
　In clock lane CL, the receiving unit 102 includes a CL-HS circuit 121 for processing HS differential signal, and a CL-LP circuit 122 for processing LP signals. In data lanes DL1, reception unit 102 includes a DL-HS circuit 123 for processing HS differential signal, a DL-LP circuit 124 for processing LP signals.
[0027]
　Figure 3 shows a specific circuit configuration example of a communication system according to a comparative example shown in FIG. Further, FIG. 4 shows an example of each signal waveform in a communication system according to the comparative example shown in FIG. 2 is transmitted to the clock lane CL and data lanes DL1.
[0028]
　As shown in FIG. 4, in the communication system according to this comparative example, in a clock lane CL, the status of the signal output from the transmission unit 101 to the clock signal line 30 is in a state of transmitting the HS differential signal HPS and duration of (High Speed ​​state), and the duration of a state for transmitting the LP signal LPS (Low Power state) exists. Substantial clock signal is output at HS differential signal during the HPS.
[0029]
　Similarly, in data lanes DL1, status signal output from the transmission unit 101 to the data signal line 31, and duration of HPS which a state of transmitting the HS differential signal, the LPS serving as a state for transmitting the LP signal there is a period of time. Substantial data signal is output by the HS differential signal during the HPS. In FIG. 4, it referred to parts of the actual data signal and HST. In addition, the duration of the HPS, TRAIL period T HS-TRAIL and SYNC (synchronization) period T HS-SYNC include and the like. Blanking period without the part of the substantive data signal is included in the period of LPS. Substantial data signal is output, for example, Byte units.
[0030]
　As shown in FIG. 3, the communication system includes a crystal oscillator (XTAL) 82 and PLL circuit 81 supplies a clock signal to each circuit unit in the transmission section 101, a clock signal to each circuit unit in the receiver 102 and a crystal oscillator (XTAL) 83 for supplying.
[0031]
　CL-HS circuit 111, a HS state machine (HS FSM) 51, a selector 52, a parallel / serial (PS) converter 53, clock divider and (DIV) 54, a HS driver (HS DRV) 55 have. Selector 52, and the Toggle signal, a signal having a value 0 (ALL0), selectively outputs the value 1 of the signal (ALL1). Toggle signal is, for example, 8 bits of the clock signal (1010_1010).
[0032]
　CL-LP circuit 112, a LP state machine (LP FSM) 41, and LP encoder (LP ENC) 42, and a LP driver (LP DRV) 43. The LP state machine 41, a clock lane control signal is input.
[0033]
　DL-HS circuit 113, a HS state machine (HS FSM) 71, a selector 72, a parallel / serial (PS) converter 73, and a HS driver (HS DRV) 74. From HS state machine 71, data transmission ready signal TxReadyHS is output. The selector 72 includes a transmission data TxDataHS, a synchronization code signal SYNC, and the value 0 of the signal (ALL0), selectively outputs the value 1 of the signal (ALL1).
[0034]
　DL-LP circuit 114, the LP state machine (LP FSM) 61, and LP encoder (LP ENC) 62, and a LP driver (LP DRV) 63. The LP state machine 61, a data transmission request signal TxRequestHS is input.
[0035]
　Incidentally, in the transmission section 101, an LP driver 43, the HS driver 55, and LP driver 63, HS driver 74 corresponds to a transmission analog circuit TX-ANALOG in FIG.
[0036]
　CL-HS circuit 121 includes a terminal circuit (TERM) 56 as a clock signal termination circuit, the HS receiver (HS RCV) 57, clock divider and a (DIV) 58. Termination circuit 56 has a termination resistor.
[0037]
　CL-LP circuit 122, the LP receiver (LP RCV) 44, and LP decoder (LP DEC) 45, and a LP state machine (LP FSM) 46. LP state machine 46 outputs a status signal of the clock lane CL.
[0038]
　DL-HS circuit 123, a terminating circuit (TERM) 75 as a data signal termination circuit, the HS receiver (HS RCV) 76, clock divider and (DIV) 77, and a word alignment correction circuit (ALN) 78 It has. Termination circuit 75 has a termination resistor. Word alignment correction circuit (ALN) 78 outputs the synchronized reception signal RxSyncHS, a reception enable signal RxValidHS, the received data RxDataHS.
[0039]
　DL-LP circuit 124, and a LP receiver (LP RCV) 64, LP decoder (LP DEC) 65, LP state machine (LP FSM) 66. LP state machine 66 outputs the received active signal RxActiveHS.
[0040]
　Incidentally, the receiving unit 102, mainly, the LP receiver 44, a termination circuit 56, an HS receiver 57, and LP receiver 64, a termination circuit 75, the HS receiver 76, the reception analog circuit RX-ANALOG in FIG 1 Equivalent to.
[0041]
<1. First Embodiment>
　Next, a description will be given of a first embodiment of the present disclosure. Hereinafter, elements having substantially the same configuration and operation as the comparative example, will not be further described.
[0042]
　Figure 5 implements a communication system shown in FIG. 1 shows an overview of a communication system according to a first embodiment of the present disclosure. Figure 6 shows a specific circuit configuration example of the communication system shown in FIG. Further, FIG. 7 shows an example of each signal waveform is transmitted to the clock lane CL and data lanes DL1 in the communication system shown in FIG. In FIGS. 5 to 7, as a data lane DL in FIG. 1 shows only one data lane DL1, other data lanes DL2, DL3, DL4 may be substantially similar configuration for.
[0043]
　Communication system according to this embodiment includes a transmitting unit 1 (transmission apparatus) corresponding to the transmission unit TX of Fig. 1, a receiver 2 (receiving apparatus) which corresponds to the receiver RX of Fig.
[0044]
　As shown in FIG. 7, in the communication system according to this embodiment, the clock lane CL, the signal output from the transmission section 1 to the clock signal line 30 are all, including the blanking period HS differential signal only It has become. As described later, in clock lane CL, the blanking period, Sadobu of the clock signal line 30 from the transmitting unit 1, as a predetermined blanking signals, a predetermined first signal value (e.g., HS-0) and ranking the signal, a predetermined second signal value different from the first signal value predetermined and differential signals (e.g., HS-1) is outputted.
[0045]
　Incidentally, HS-0 indicates the differential signal equal to zero (differential 0 (Differential-0)) and becomes a differential signal, HS-1 is the value 1 (Differential 1 (Differential-1)). More specifically, as shown in FIG. 8, the signal of the HS-0 is next voltage level of the positive signal line Dp is Low, the voltage level of the negative signal line Dn becomes High in the transmission line of a differential signal It refers to a differential signal. The signal of the HS-1, the voltage level of the positive signal line Dp in the transmission line of the differential signal refers to a differential signal becomes High, the voltage level of the negative signal line Dn becomes Low.
[0046]
　Similarly, in data lanes DL1, signal output from the transmission unit 1 to the data signal line 31 are all including the blanking period becomes only HS differential signal.
　In FIG. 7, marks the part of the substantive data signal HST. The period before and after the actual data signal SYNC (synchronization) period T HS-SYNC and TRAIL period T HS-TRAIL may include and. In data lanes DL1, total blanking the blanking period, the data signal line 31 from the transmitting unit 1, as predetermined data blanking signal, the blanking period any differential signal (e.g., HS-0 or HS-1) it may be output over.
[0047]
　As shown in FIG. 6, the communication system according to this embodiment includes a crystal oscillator (XTAL) 82 and PLL circuit 81 supplies a clock signal to each circuit of the transmission unit 1, each of the receiving section 2 and a crystal oscillator (XTAL) 83 and PLL circuit 84 supplies a clock signal to the circuit portion.
[0048]
　In clock lane CL, the transmission unit 1 includes a CL-HS circuit 11 for processing HS differential signal. In data lanes DL1, transmitter 1 includes a DL-HS circuit 13 for processing HS differential signal.
　CL-HS circuit 11 may be a differential clock signal transmitting circuit for outputting the HS differential signals including a clock signal of the differential clock signal line 30. DL-HS circuit 13 may be a differential data signal transmission circuit for outputting a data signal of the differential to the data signal line 31.
[0049]
　The transmitting unit 1 in this embodiment, may not include the circuit corresponding to CL-LP circuit 112 and DL-LP circuit 114 for processing a LP signal in the comparative example.
[0050]
　CL-HS circuit 11, as shown in FIG. 6 may have substantially the same circuit as the CL-HS circuit 111 in FIG. 3. That, CL-HS circuit 11 includes a HS state machine (HS FSM) 51, a selector 52, a parallel / serial (PS) converter 53, clock divider and (DIV) 54, HS driver (HS DRV) 55 and may have. Selector 52, Toggle signal and a predetermined first signal value (HS-0) and a value 0 signal (ALL0), a predetermined second signal value (HS-1) become the value 1 of the signal ( ALL1) and selectively outputs. Toggle signal is, for example, 8 bits of the clock signal (1010_1010). In this embodiment, the clock lane control signal and a data transmission request signal TxRequestHS is input to the HS state machine 51.
[0051]
　DL-HS circuit 13, as shown in FIG. 6 may have substantially the same circuit as the DL-HS circuit 113 in FIG. 3. That, DL-HS circuit 13, the HS state machine (HS FSM) 71, a selector 72, a parallel / serial (PS) converter 73 may have a HS driver (HS DRV) 74. From HS state machine 71, data transmission ready signal TxReadyHS is output. The selector 72 includes a transmission data TxDataHS, a synchronization code signal SYNC, predetermined first signal value (HS-0) and becomes a value 0 signal (ALL0), a predetermined second signal value (HS-1) selectively outputs the value serving as the first signal (ALL1).
[0052]
　Transmitting unit 1 includes a blanking control unit 20. As shown in FIG. 6, the blanking control section 20 may have a HS state machine 51 and the HS state machine 71.
[0053]
　Blanking control unit 20 in synchronization with the start time of the blanking period of the data signal, the data signal line 31 from DL-HS circuit 13, instead of the data signal, so that the predetermined data blanking signal is output , it controls the DL-HS circuit 13. Further, blanking control unit 20 in synchronization with the start time of the blanking period of the data signal, a clock signal line 30 from the CL-HS circuit 11, a predetermined first for more than a predetermined time period instead of the clock signal as the differential blanking signal 1 signal values ​​(e.g., HS-0) are continuous is output, controls the CL-HS circuit 11. Here, the predetermined period is a period longer than the clock period of the clock signal. The differential blanking signals, over a period longer than the clock period of the clock signal by a predetermined first signal which the signal value is continuous, in the clock state discrimination circuit 59 of the receiving unit 2 to be described later, the signal can be used to detect changes, it is possible to detect that the blanking period is started.
[0054]
　Further, blanking control unit 20 in synchronization with the end time of the blanking period of the data signal, from the CL-HS circuit 11 to the clock signal line 30, instead of the differential blanking signal, and the differential blanking signal It is such that different predetermined differential signal is output, controls the CL-HS circuit 11. Specifically, as a predetermined differential signal, the differential signal predetermined second signal value different from the first signal value predetermined (e.g. HS-1) is continuous for more than a predetermined time period as output, it controls the CL-HS circuit 11. It is also possible to HS-1 a predetermined first signal value, a predetermined second signal value to HS-0 in the above description. A predetermined differential signal and the second signal value different predetermined the predetermined first signal value is a differential signal that continuously for more than a predetermined period, the receiving unit 2 to be described later clock in the state determination circuit 59 can detect a change in the signal, the blanking period is completed, it is possible to detect that the data signal transfer is started.
[0055]
　In clock lane CL, the receiving unit 2 has a CL-HS circuit 21 for processing HS differential signal. In data lanes DL1, reception unit 2 includes a DL-HS circuit 23 for processing HS differential signal.
[0056]
　DL-HS circuit 23 may be a differential data signal receiving circuit for receiving data signals of the differential via the data signal line 31. CL-HS circuit 21, a clock signal of a differential, a differential blanking signal outputted from the CL-HS circuit 11 described above, in the differential clock signal receiving circuit for receiving via the clock signal line 30 it may be.
[0057]
　The receiving unit 2 in the present embodiment, may not include the circuit corresponding to CL-LP circuit 122 and DL-LP circuit 124 for processing a LP signal in the comparative example.
[0058]
　DL-HS circuit 23, as shown in FIG. 6 may have substantially the same circuit as the DL-HS circuit 123 in FIG. 3. That is, a termination circuit (TERM) 75 as a data signal terminating circuit connected to the data signal line 31, the HS receiver (HS RCV) 76, clock divider and (DIV) 77, word alignment correction circuit (ALN) 78 and may have a. Termination circuit 75 has a termination resistor. Word alignment correction circuit (ALN) 78 outputs the synchronized reception signal RxSyncHS, a reception enable signal RxValidHS, the received data RxDataHS.
[0059]
　CL-HS circuit 21, as shown in FIG. 6 may have substantially the same circuit as the CL-HS circuit 121 in FIG. 3. That, CL-HS circuit 21 includes a terminal circuit (TERM) 56 as a clock signal termination circuit connected to the clock signal line 30, the HS receiver (HS RCV) 57, clock divider and a (DIV) 58 it may have. Termination circuit 56 has a termination resistor.
[0060]
　CL-HS circuit 21 further has a clock (CL) a state determination circuit 59. The clock state discrimination circuit 59, a differential blanking signal of the clock signal and a predetermined first signal value from CL-HS circuit 11 of the transmitter 1 via the HS receiver 57 (e.g., HS-0) (e.g. HS-0) and a predetermined second signal value and the differential signal (e.g., HS-1) is input.
[0061]
　Clock state discrimination circuit 59 has a function as a terminating control circuit, based on the differential blanking signal, the data signal termination circuit (termination circuit 75) and a clock signal terminal circuits each with respect to (termination circuit 56) performs control to turn off the termination resistor. The clock state discrimination circuit 59, in synchronism with the end time of the blanking period of the data signal is output, based on a differential signal of a predetermined second signal value (e.g., HS-1), the termination circuit 75 and performs control to turn on the respective termination resistance to termination circuit 56.
[0062]
　Incidentally, with the terminating resistor on / off, as shown in FIG. 7, the voltage amplitude of the signal changes in the blanking period of the clock lanes CL and data lanes DL1. Further, by turning off the termination control in the blanking period, it is possible to reduce the current flowing through the clock signal line 30 and the data signal line 31.
[0063]
　The clock state discrimination circuit 59, to the outputs received active signal RxActiveHS word alignment correction circuit 78 has a function of performing word alignment control. Blanking period ends, by appropriately detecting the clock state discrimination circuit 59 that of the data signal transfer is started, and detects a synchronization code signal SYNC, the appropriate word alignment control word alignment correction circuit 78 It can be carried out.
[0064]
[Effect]
　As described above, according to this embodiment, in synchronization with the start time of the blanking period of the data signal, a clock signal line 30, a predetermined over more than a predetermined period of time instead of the clock signal since so as to output a differential blanking signal first signal value is continuous, it is possible to reduce the power consumption during data transmission.
[0065]
　Also, via a clock signal line 30, an output clock signal of the differential, as a first signal value of the predetermined blanking and blanking period start time in synchronization with for more than a predetermined period of the data signal is continuous since so as to receive a differential blanking signal, it is possible to reduce the power consumption during data transmission.
[0066]
　Further, according to this embodiment, effectively LP signal portion (blanking period) which have not been utilized also becomes possible to transfer the data signal by HS differential signal in the communication system according to a comparative sequence described above lowers the transfer rate of the data signal by HS differential signal, it is possible to reduce the power consumption as a whole. Further, according to this embodiment, as compared with the communication system according to a comparative sequence described above, the circuit for processing the LP signal is not required, it is possible to reduce the circuit scale.
[0067]
　Incidentally, the advantages described in the specification are not limited to a merely illustrative, and there may be other effects. The same applies to the effect of another embodiment of the later.
[0068]
<2. Second Embodiment>
　Next, a description will be given of a second embodiment of the present disclosure. In the following, the comparative example, portions having substantially the same configuration and operation as the first embodiment is appropriately omitted.
[0069]
　Figure 9 shows a specific circuit configuration example of a communication system according to the present embodiment. Further, FIG. 10 shows an example of each signal waveform in a communication system according to this embodiment is transmitted to the clock lane CL and data lanes DL1. In FIG. 9 and FIG. 10, as the data lanes DL in FIG. 1 shows only one data lane DL1, other data lanes DL2, DL3, DL4 may be substantially similar configuration for. It is to be noted that the block configuration showing an overview of a communication system according to the present embodiment may be substantially similar to FIG. 5.
[0070]
　Also in this embodiment, as in the first embodiment, the blanking control section 20, in synchronism with the end time of the blanking period of the data signal, from the CL-HS circuit 11 to the clock signal line 30 , instead of the differential blanking signal, so that a predetermined differential signal different from the differential blanking signal is output, controls the CL-HS circuit 11. In the first embodiment, as a predetermined differential signal, such that the differential signal predetermined second signal value (e.g., HS-1) is continuous for more than a predetermined period of time is output, CL to control the -HS circuit 11. In contrast, in the present embodiment, as a predetermined differential signals, so that the clock signal is output over a predetermined period or longer, controls the CL-HS circuit 11. A predetermined differential signal, by a clock signal over a predetermined period of time or longer, the clock state discrimination circuit 59 of the receiver 2A, it is possible to detect the change in the signal, terminates the blanking period, the data signal it is possible to detect that the transfer is started.
[0071]
　In this embodiment, as shown in FIG. 7, the clock lane CL, the blanking period, the clock signal line 30 from the transmitting unit 1, a predetermined first signal value (e.g., HS-0 or HS- differential blanking signal 1) and the clock signal are output.
[0072]
　Compared to the circuit configuration of FIG. 6, the circuit of FIG. 9, the signal input to the clock state discrimination circuit 59 in the CL-HS circuit 21 of the receiving portion 2A is different. That is, the receiving unit 2 of the circuit arrangement of FIG. 6, the clock state discrimination circuit 59, the signal from the HS receiver 57 is directly input. In contrast, in the receiving portion 2A of the circuit configuration of FIG. 9, the clock state discrimination circuit 59, the signal from the HS receiver 57 is not directly input, divided signal by the clock divider 58 is input that. As a result, to detect the start time and end time of the blanking period.
[0073]
　Other configurations and operations may be substantially similar to the communication system according to the first embodiment.
[0074]
[2.2 Modification]
　Next, a description Te first to fifth modification Ni'i communication system according to the second embodiment.
[0075]
　11 to 15 show an example of each signal waveform is transmitted to the clock lane CL and data lanes DL1 in the communication system according to a modification of the first to fifth. In FIGS. 11 to 15, as a data lane DL in FIG. 1 shows only one data lane DL1, other data lanes DL2, DL3, DL4 may be substantially same applies. The block structure showing an overview of a communication system according to the present embodiment may be substantially similar to FIG. 5.
[0076]
(First Modification)
　In a first modification shown in FIG. 11, for the example shown in FIG. 10 is different from that signal output from the transmission unit 1 to the data lanes DL1 during the blanking period. In data lanes DL1, the blanking period, the DL-HS circuit 13 of the transmitter 1, firstly, as predetermined data blanking signal, the inversion of the last value of the actual data signal transmitted in a period of HST differential signal value is output. Then, the DL-HS circuit 13, a differential signal of the differential 0 (HS-0) is output.
[0077]
　Blanking control unit 20 in synchronization with the start time of the blanking period, the data signal line 31 from DL-HS circuit 13, so that the differential signal of the inverted value of the last value of the data signal is output, DL controlling the -HS circuit 13. Further, the blanking control section 20, in synchronism with the end time of the blanking period, in place of the differential signal of the inverted value of the last value of the data signal, the data signal line 31 from DL-HS circuit 13, HS as the differential signals -0 is output, controls the DL-HS circuit 13. Note that the clock signal line 30, as in the example of FIG. 10, the blanking period in synchronization with end time of, for more than a predetermined time period from the CL-HS circuit 11 of the transmitter 1 to the clock signal line 30 the clock signal is output. Start time of the respective outputs of the differential signal and the clock signal of the HS-0 output to the blanking period may be different.
[0078]
　According to the first modification, by the last period of the blanking period in data lanes DL1 to differential signal HS-0, the signal value of the last period of the blanking period, subsequent SYNC (synchronous) time T HS-sYNC becomes the signal value and the same value at the start of the synchronization process on the receiving side can be facilitated. In general, TRAIL period T in data lanes DL1 HS-TRAIL signal is a differential signal of the inverted value of the last value of the data signal. Therefore, according to the first modification, the signal value at the beginning of the blanking period TRAIL period T HS-TRAIL can be adapted to signal.
[0079]
　Others may be substantially similar to the signal waveform in FIG. 10.
[0080]
(Second Modification)
　In the second modification shown in FIG. 12, the first modification shown in FIG. 11, is output from CL-HS circuit 11 of the transmitter 1 to the clock signal line 30 signal is different from some that. In clock lane CL, blanking the blanking period, the CL-HS circuit 11 of the transmitter 1, first, as in the first embodiment shown in FIG. 7, the predetermined first signal value (e.g., HS differential signal -0 or HS-1) is outputted. Thereafter, as in the first embodiment, the CL-HS circuit 11, a predetermined second signal value different from the first signal value predetermined (for example HS-1 or HS-0) differential signal is output. Then, after time to turn on the terminating resistor, a clock signal from the CL-HS circuit 11 is output. From CL-HS circuit 11, after outputting a differential signal of a predetermined second signal value, across the time to turn on the terminating resistor, then, that it leaves the clock signal, the first embodiment It is different from the form. Blanking control unit 20, so that the differential signal and the clock signal at appropriate timing from the CL-HS circuit 11 is output, controls the CL-HS circuit 11.
[0081]
　According to the second modification, as compared with the case of turning on the terminating resistor in the output period of the clock signal as in the first modification, the waveform due to reflection of the clock signal at the time of termination resistors off in the clock lane CL it is possible to reduce the influence of disturbances.
[0082]
　Others may be substantially similar to the first modification of FIG. 11.
[0083]
(Third Modification)
　In the third modification shown in FIG. 13, the second modification shown in FIG. 12, signals output from the transmission section 1 to the blanking period in data lanes DL1 It is different. In the third modification, throughout the blanking period, the DL-HS circuit 13 of the transmitter 1, as predetermined data blanking signal, the differential signal of the HS-0 is outputted. Blanking control unit 20, so that the differential signal of the HS-0 at an appropriate timing from the DL-HS circuit 13 is output, controls the DL-HS circuit 13.
[0084]
　Others may be substantially similar to the second modification of FIG. 12.
[0085]
(Fourth Modification)
　In the fourth modification shown in FIG. 14, the first modification shown in FIG. 11, signals output from the transmission section 1 to the blanking period in data lanes DL1 They are different part. In the fourth modified example, the data lanes DL1, the blanking period, the DL-HS circuit 13 of the transmitter 1, firstly, as predetermined data blanking signal, the differential signal of the HS-1 is output that. Then, the DL-HS circuit 13, a differential signal HS-0 is outputted. Blanking control unit 20, so that the differential signal of the differential signal and HS-0 of HS-1 at a proper timing from DL-HS circuit 13 is output, controls the DL-HS circuit 13.
[0086]
　Others may be substantially similar to the first modification of FIG. 11.
[0087]
(Fifth Modification)
　In the fifth modification shown in FIG. 15, the second modification shown in FIG. 12, signals output from the transmission section 1 to the blanking period in data lanes DL1 They are different part. In the fifth modification, in data lanes DL1, the blanking period, the DL-HS circuit 13 of the transmitter 1, firstly, as predetermined data blanking signal, the differential signal of the HS-1 is output that. Then, the DL-HS circuit 13, a differential signal HS-0 is outputted. Blanking control unit 20, so that the differential signal of the differential signal and HS-0 of HS-1 at a proper timing from DL-HS circuit 13 is output, controls the DL-HS circuit 13.
[0088]
　Others may be substantially similar to the second modification of FIG. 12.
[0089]
<3. Third Embodiment>
　Next, a description will be given of a third embodiment of the present disclosure. In the following, the comparative example, portions having substantially the same configuration and operation as the form or in the form of the second embodiment of the first embodiment is appropriately omitted.
[0090]
　Figure 16 shows an overview of a communication system according to a third embodiment of the present disclosure. Communication system according to this embodiment includes a transmitting unit 1B which correspond to the transmission unit TX of Fig. 1 (transmission device), and a receiver 2B (receiving apparatus) which corresponds to the receiver RX of Fig.
[0091]
　The in the communication system according to the first and second embodiments, a signal transmitted in each of the clock lane CL and data lanes DL1, are only to all, including the blanking period HS differential signal. In contrast, the communication system according to this embodiment includes a switching circuit that enables also communication in LP signal, and a mode for communicating only in HS differential signal without using the LP signal, the LP signal using both the HS differential signal is obtained that can be switched to a mode for communication.
[0092]
　In the communication system according to this embodiment, the transmission unit 1B has a blanking control unit 20 to realize the substantially same function as the communication system according to the first and second embodiments.
[0093]
　Also, chromatic transmission section 1B, in the clock lane CL, and CL-HS circuit 11 for processing HS differential signal, and CL-LP circuit 12 for processing LP signal, a changeover switch 15 and a selector 17 are doing.
[0094]
　CL-LP circuit 12 may be a first single-ended signal transmission circuit for outputting a first single-ended signal as an LP signal. CL-LP circuit 12 may have substantially the same function as the CL-LP circuit 112 in FIG. 2. Changeover switch 15, the clock signal line 30, so that the signal output is made from either the CL-HS circuit 11 and CL-LP circuit 12, a first transmission switching circuit for switching a path of the signal output it may be. Selector 17 as the control signal from blanking control unit 20 in a mode to perform communication only in HS differential signal without using the LP signal is input to the CL-HS circuit 11, LP signal and the HS differential signal in a mode in which communication is performed using both the a circuit control signal from blanking control unit 20 from being input to the CL-HS circuit 11.
[0095]
　The transmission unit 1B is used, the number in the data lanes DL1, and DL-HS circuit 13 for processing HS differential signal, a DL-LP circuit 14 for processing LP signal, a changeover switch 16 and a selector 18 are doing.
[0096]
　DL-LP circuit 14 may be a second single-ended signal transmission circuit for outputting a second single-ended signal as an LP signal. DL-LP circuit 14 may have substantially the same function as the DL-LP circuit 114 in FIG. 2. Changeover switch 16, so that one signal output from one of the DL-HS circuit 13 and the DL-LP circuit 14 to the data signal line 31 is performed, even in the second transmission switching circuit for switching a path of the signal output good. The selector 18, as the control signal from blanking control unit 20 in a mode to perform communication only in HS differential signal without using the LP signal is input to the DL-HS circuit 13, LP signal and the HS differential signal in a mode in which communication is performed using both the a circuit control signal from blanking control unit 20 from being input to the DL-HS circuit 13.
[0097]
　The receiver 2B, in the clock lane CL, and CL-HS circuit 21 for processing HS differential signal, and CL-LP circuit 22 for processing LP signal, a selector 25, a selector 27 and a selector 28 It has. CL-LP circuit 22 may be a first single-ended signal receiving circuit for receiving via the clock signal line 30 to the first single-ended signal as an LP signal. CL-LP circuit 22 may have substantially the same function as the CL-LP circuit 122 in FIG. 2.
[0098]
　The selector 25 may be a first reception switching circuit for switching whether to receive a first single-ended signal as an LP signal. Selector 25, as the signal received via the clock signal line 30 is in a mode to perform communication only in HS differential signal without using the LP signal is not input to the CL-LP circuit 22, LP signal and the HS differential signal in a mode in which communication is performed using both the a circuit signal received via the clock signal line 30 is to be input to the CL-LP circuit 22. The selector 27 is in the mode for communicating only in HS differential signal without using the LP signal as signal termination control from CL-HS circuit 21 is input to the DL-HS circuit 23, LP signal and HS difference in a mode in which communication is performed using both the motion signal, a circuit for signal termination control from being input from the HS circuit 21. The selector 28 is in the mode for communicating only in HS differential signal without using the LP signal as signal word alignment control from CL-HS circuit 21 is input to the DL-HS circuit 23, LP signal and HS in a mode in which communication is performed using both the differential signals, a circuit to allow signal word alignment control from the HS circuit 21 is not inputted.
[0099]
　The receiving unit 2B, in the data lanes DL1, and DL-HS circuit 23 for processing HS differential signal, a DL-LP circuit 24 for processing LP signal, and a selector 26. DL-LP circuit 24 may be a second single-ended signal receiving circuit for receiving via a second single-ended signal data signal line 31 as LP signal.
[0100]
　The selector 26 may be a second reception switching circuit for switching whether to receive the second single-ended signal as an LP signal. The selector 26, as the signal received via the data signal line 31 is in a mode to perform communication only in HS differential signal without using the LP signal is not input to the DL-LP circuit 24, LP signal and the HS differential signal in a mode in which communication is performed using both the a circuit signal received via the data signal line 31 is to be input to the DL-LP circuit 24.
[0101]
　Figure 17 illustrates a specific application example of the communication system according to this embodiment.
[0102]
　For example, the communication system according to this embodiment, as shown in FIG. 17 is applicable from the image sensor IS for data transmission to the application processor AP. Transmission unit 1B is provided an image sensor in IS. The receiver 2B is provided in the application processor AP. Between the image sensor IS and the application processor AP is connected by the clock signal line 30 and the data signal line 31. Transmission of a signal by the clock signal line 30 and the data signal line 31 has a one-way.
[0103]
　Further, between the image sensor IS and the application processor AP is connected by a bidirectional control bus 35. Control bus 35, I 2 I is C (Inter-Integrated Circuit) interface and its enhanced version 3 can be used C interface.
[0104]
　Figure 18 shows an example of a data transmission processing in the apparatus including an image sensor IS, and the application processor AP shown in FIG. 17.
[0105]
　Power-on of the device including an image sensor IS, and the application processor AP is made (step S101), the application processor AP is using the control bus 35, reads the register settings of the image sensor IS (Step S102). Thus, the application processor AP, the image sensor IS is determined whether or not the response to communicate without LP signal (step S103). That is, it is determined a mode for communicating only in HS differential signal without using the LP signal, whether in response to either mode the mode for communication with both the LP signal and the HS differential signal .
[0106]
　If it is determined that corresponds to the communication without LP signal; (step S103 Y), the application processor AP is image using the control bus 35, the setting to enable communication without LP signal transmitting the sensor iS (step S104). Next, the application processor AP uses the control bus 35, and outputs a signal of the transmission start command to the image sensor IS (Step S105). If it is determined that no response to communication without LP signal; (step S103 N), the application processor AP is regarded as the mode to communicate using both the LP signal and the HS differential signal, using a control bus 35, and outputs a signal of the transmission start command to the image sensor iS (step S105). Then, the image sensor IS receives a signal of the transmission start instruction, initiating the transmission of the data signal (step S106).
[0107]
<4. Fourth Embodiment>
　Next, a description will be given of a fourth embodiment of the present disclosure. In the following, the comparative example, or, portions having substantially the same configuration and operation as in the above-described first to third embodiment is appropriately omitted.
[0108]
　Figure 19 shows an overview of a communication system according to a fourth embodiment of the present disclosure. Figure 20 shows a first example of each signal waveform in a communication system according to this embodiment is transmitted to the clock lane CL and data lanes DL1. Figure 21 shows a second example of each signal waveform in a communication system according to this embodiment is transmitted to the clock lane CL and data lanes DL1. In none 19 21, as a data lane DL in FIG. 1 shows only one data lane DL1, other data lanes DL2, DL3, DL4 may be substantially similar configuration for.
[0109]
　Communication system according to the present embodiment, the configuration of the communication system shown in FIG. 5, are different portions of the termination control. In the first to third embodiments, in the blanking period, but to perform the control of the terminating resistor on / off, in this embodiment, it is omitted control of the on / off this terminating resistor ing.
[0110]
　In the first example of FIG. 20, normally a termination resistor in the clock lane CL and data lanes DL1 Prefecture, shows an example of a case where the on state. For the first example of FIG. 20, the on / off switchable termination resistor is provided, a terminating resistor at all times, may be in the on state at all times, may be provided a terminating resistor of the on stationary .
[0111]
　In the second example of FIG. 21, normally a termination resistor in the clock lane CL and data lanes DL1 Prefecture, shows an example of a case where the state of off. For the second example of FIG. 21, it may be omitted terminating resistor itself, a switchable termination resistor on / off is provided, a terminating resistor at all times, may be turned off.
[0112]
　In a second example of the first embodiment and FIG. 21 in FIG. 20, the voltage amplitude of the signal is different. When you turn on the terminating resistor, than when turning off the termination resistor, the voltage amplitude decreases. Therefore, the direction of the voltage amplitude in the first example of FIG. 20, is smaller than the voltage amplitude in the second example of FIG. 21.
[0113]
　Others may be substantially similar to the signal waveform of FIG. 11.
[0114]
<5. Application Example>
　Next, a description will be given of application examples of the communication system described in the above embodiments.
[0115]
[5.1 first application example]
　FIG. 22 illustrates an appearance of a smartphone 300 (feature phones) that the communication system of the embodiments is applied. The smartphone 300, various devices are mounted, in a communication system for exchanging data between those devices, the communication system of the embodiments is applied.
[0116]
　Figure 23 is a representation of an example of a configuration of the application processor 310 for use in a smartphone 300. The application processor 310 includes a CPU (Central Processing Unit) 311, a memory controller 312, a power control unit 313, an external interface 314, a GPU (Graphics Processing Unit) 315, a media processing unit 316, the display control unit 317 and, and a MIPI interface 318. CPU 311, memory controller 312, the power supply control unit 313, external interface 314, GPU315, the media processing unit 316, the display control unit 317, in this example, is connected to the system bus 319 via the system bus 319, to each other data thereby making it possible to make the exchange.
[0117]
　CPU311 according to a program, and processes a variety of information handled by the smart phone 300. Memory controller 312, controls the memory 501 to be used when CPU311 processes information. Power supply control unit 313 controls the power of the smartphone 300.
[0118]
　The external interface 314 is an interface for communicating with an external device, in this example, is connected to the radio communication unit 502 and the image sensor 410. Wireless communication unit 502 is for wireless communication with a base station of a cellular phone, for example, a baseband unit and, RF (Radio Frequency) and the like the front end portion. The image sensor 410 is adapted to acquire an image, for example, configured to include a CMOS sensor.
[0119]
　GPU315 is for performing image processing. The media processing unit 316, audio and, or character, is intended to process the information, such as graphics. Display control unit 317, via the MIPI interface 318, and controls the display 504.
[0120]
　MIPI interface 318 is for transmitting an image signal to the display 504. The image signal, for example, may be used a signal, such as YUV format or RGB format. The communication system between the MIPI interface 318 and display 504, for example, the communication system of the above-described embodiments is applied.
[0121]
　Figure 24 shows an example of the configuration of the image sensor 410. The image sensor 410 includes a sensor unit 411, an ISP (Image Signal Processor) 412, a JPEG (Joint Photographic Experts Group) encoder 413, a CPU 414, a RAM (Random Access Memory) 415, a ROM (Read Only Memory) 416 , a power supply control unit 417, I 2 and C (Inter-Integrated Circuit) interface 418, and an MIPI interface 419. Each of these blocks, in this example, is connected to the system bus 420 via the system bus 420, thereby making it possible to exchange data with each other.
[0122]
　Sensor unit 411 is for acquiring an image, for example, is formed using the CMOS sensor. ISP412 is for performing a predetermined process on the image sensor unit 411 has acquired. JPEG encoder 413 is configured to generate an image of the JPEG format to encode the image ISP412 has processed. CPU414 is configured to control each block of the image sensor 410 according to a program. RAM415 is a memory that is used when the CPU414 processes information. ROM416 is for storing a program executed in the CPU 414. Power supply control unit 417 is for controlling the power supply of the image sensor 410. I 2 C interface 418 is to receive the control signal from the application processor 310. Although not shown, the image sensor 410, the application processor 310 is adapted to receive even a clock signal in addition to the control signal. Specifically, the image sensor 410 is configured to operate based on various frequencies of the clock signal.
[0123]
　MIPI interface 419, and transmits the image signal to the application processor 310. The image signal, for example, may be used a signal, such as YUV format or RGB format. The communication system between the MIPI interface 419 and the application processor 310, for example, the communication system of the above-described embodiments is applied.
[0124]
[5.2 second application example]
　in FIGS. 25 and 26, as an application example of the image pickup device, illustrating a configuration example of a vehicle-mounted camera. Figure 25 shows an example of an installation example of a vehicle-mounted camera, FIG. 26 shows an internal configuration example of a vehicle-mounted camera.
[0125]
　For example, as shown in FIG. 25, the in-vehicle camera 401 in front (ahead) of the vehicle 301, vehicle camera 402, the vehicle-mounted camera 404 further to the rear (backward) is installed on the left and right. Each vehicle camera 401-404, ECU 302 via the vehicle network; is connected to a (Electrical Control Unit ECU).
[0126]
　Image capture angle of the in-vehicle camera 401 that is installed in front of the vehicle 301 is a range indicated by a in FIG. 25 for example. Image capture angle of the vehicle-mounted camera 402 is a range indicated by b in FIG. 25 for example. Image capture angle of the vehicle-mounted camera 403 is a range indicated by c in FIG. 25 for example. Image capture angle of the vehicle-mounted camera 404, a range indicated by d in FIG. 25 for example. Each vehicle camera 401-404 outputs an image captured in ECU 302. As a result, the front of the vehicle 301, left and right, rear 360 degree images (omnidirectional) can be incorporated in the ECU 302.
[0127]
　For example, as shown in FIG. 26, respectively have the onboard camera 401-404, an image sensor 431, a DSP (Digital Signal Processing) circuit 432, a selector 433, and a SerDes (SERializer / DESerializer) circuit 444 ing.
[0128]
　DSP circuit 432 performs various image signal processing on the imaging signal output from the image sensor 431. SerDes circuit 444, which performs serial / parallel conversion of the signal, for example, an on-vehicle interface chip such as FPD-Link III.
[0129]
　The selector 433, an image signal output from the image sensor 431, to be output through the DSP circuit 432 is for selecting whether to output without passing through the DSP circuit 432.
[0130]
　The connection interface 441 between the image sensor 431 and the DSP circuit 432, for example, the communication system of the embodiments can be applied. Further, the connection interface 442 between the image sensor 431 and the selector 433, for example, the communication system of the embodiments can be applied.
[0131]
<6. Other Embodiments>
　technique according to the present disclosure can be variously modified without being limited to the description of the above embodiments is.
[0132]
　For example, the present technology may have the following configurations.
(1)
　and a clock signal transmitting circuit for outputting a clock signal to a clock signal line,
　a data signal transmission circuit for outputting a data signal to the data signal line,
　in synchronism with the blanking period of the data signal, the clock signal transmission circuit to the clock signal line from that prescribed blanking signal instead of the clock signal is output, and a blanking control unit that controls the clock signal transmitting circuit
　transmitting device comprising a.
(2)
　the clock signal transmission circuit is a differential clock signal transmitting circuit for outputting a differential clock signal as the clock signal to the clock signal line,
　the data signal transmission circuit of the differential as the data signal a differential data signal transmission circuit for outputting a data signal to the data signal lines,
　the blanking control unit, in synchronization with the start time of the blanking period of said data signal, said from the differential clock signal transmission circuit a clock signal line, said a predetermined blanking signals, such that the differential blanking signal the first signal value of a predetermined for over a predetermined time period are continuous is output, controls the differential clock signal transmission circuit to
　transmission apparatus according to (1).
(3)
　the predetermined period is longer than the clock period of the clock signal
　transmitting apparatus according to (2).
(4)
　the blanking control unit, the synchronization with the end time of the blanking period of the data signal, to the clock signal line from the differential clock signal transmission circuit, instead of the differential blanking signal, the as a predetermined differential signal different from the differential blanking signal is output, controls the differential clock signal transmitting circuit
　transmitting apparatus according to (2) or (3).
(5)
　the blanking control unit, the differential clock signal the clock signal line from the transmission circuit, as the predetermined differential signal, a predetermined second signal value different from the first signal value of the predetermined There so that differential signals continuously for more than the predetermined period is output, and controls the differential clock signal transmitting circuit
　transmitting apparatus according to (4).
(6)
　the blanking control unit, the differential clock signal transmitting circuit and the clock signal line from, as the predetermined differential signals, so that the clock signal for more than the predetermined period is output, the controlling the differential clock signal transmitting circuit
　transmitting apparatus according to (4).
(7)
　the blanking control unit, after the signal of the predetermined second signal value is output, the differential clock from the signal transmitting circuit to said clock signal line, the above (4 within the blanking period transmitting apparatus according to).
As the clock signal is output, controls the differential clock signal transmitting circuit
　transmitting apparatus according to (5).
(8)
　the blanking control unit, further wherein in synchronization with the start time of the blanking period of the data signal, from said data signal transmission circuit to said data signal lines, instead of the data signal, at least certain data blanking so that the ranking signal is output, controls the data signal transmission circuit
　transmitting apparatus according to any one of (2) to (7).
(9)
　the blanking control unit, as the predetermined data blanking signal, so that the inverted signal of the last signal value of the data signal is output, controls the data signal transmission circuit
　in (8) transmitting apparatus according.
(10)
　the blanking control unit, as the predetermined data blanking signals, such that the differential signal value is 1 is output, and controls the differential data signal transmission circuit
　according to (8) the transmission device.
(11)
　the blanking control unit, after the predetermined data blanking signal is output, the data signal in synchronization with the end time of the blanking period, the output from the differential signal value becomes 0 as controls the differential data signal transmission circuit
　transmitting apparatus according to (8).
(12)
　the blanking control unit, as the predetermined data blanking signals, such that the differential signal values throughout is zero in the blanking period is output, the differential data signal transmission circuit controlling
　transmission apparatus according to (8).
(13)
　a first single-ended signal transmission circuit and, for outputting a first single-ended signal
　from one of said to said clock signal line differential clock signal transmitting circuit and the first single-ended signal transmission circuit as the signal output is performed, the first transmission switching circuit for switching a path of the signal output,
　and a second single-ended signal transmission circuit for outputting a second single-ended signal,
　the differential data signal to the data signal line from one of the transmitting circuit and the second single-ended signal transmission circuit so that the signal output is performed, the second transmission switching circuit for switching a path of the signal output
　further comprises
　the above (2) to (12) transmitting apparatus according to any one.
(14)
　and a data signal receiving circuit for receiving via the data signal line a data signal,
　a clock signal and a predetermined blanking signal in synchronism with the blanking period of the data signal output, a clock signal line a clock signal receiving circuit for receiving via
　the receiving device comprising a.
(15)
　the data signal receiving circuit is a differential data signal receiving circuit for receiving a data signal of the differential via the data signal lines as the data signal,
　the clock signal receiver circuit, the difference as the clock signal which receives the clock signal of the dynamic output as the first signal value of the predetermined for over a predetermined period in synchronization as the predetermined blanking signal to the start time of the blanking period of the data signal is continuous a differential clock signal receiving circuit for receiving a differential blanking signal
　receiving apparatus according to (14).
(16)
　the differential data signal receiving circuit
　has a data signal termination circuit comprising the connected terminating resistor to the data signal lines,
　the differential clock signal receiving circuit,
　the clock signal line connected to termination a clock signal termination circuit comprising a resistor,

[Claim 1]
　A clock signal transmitting circuit for outputting a clock signal to a clock signal line,
　a data signal transmission circuit for outputting a data signal to the data signal line,
　in synchronism with the blanking period of the data signal, the clock from said clock signal transmission circuit the signal line, so that a predetermined blanking signal instead of the clock signal is output, and a blanking control unit that controls the clock signal transmitting circuit
　transmitting device comprising a.
[Claim 2]
　It said clock signal transmission circuit is a differential clock signal transmitting circuit for outputting a differential clock signal as the clock signal to the clock signal line,
　the data signal transmission circuit, the data signal of the differential as the data signal wherein a differential data signal transmission circuit for outputting the data signal lines,
　the blanking control unit, in synchronization with the start time of the blanking period of the data signal, the clock signal line from the differential clock signal transmission circuit in the as predetermined blanking signals, such that the differential blanking signal the first signal value of a predetermined for over a predetermined time period are continuous is output, and controls the differential clock signal transmission circuit
　according to claim transmitting apparatus according to 1.
[Claim 3]
　Wherein the predetermined period is longer than the clock period of the clock signal
　transmitting apparatus according to claim 2.
[Claim 4]
　The blanking control unit, the synchronization with the end time of the blanking period of the data signal, to the clock signal line from the differential clock signal transmission circuit, instead of the differential blanking signal, the Sadobu as a predetermined differential signal different from the ranking signal is output, controls the differential clock signal transmitting circuit
　transmitting apparatus according to claim 2.
[Claim 5]
　The blanking control unit, the differential clock signal the clock signal line from the transmission circuit, as the predetermined differential signal, said second signal value different predetermined the predetermined first signal value is predetermined as the differential signals continuously for more than a period is output, and controls the differential clock signal transmitting circuit
　transmitting apparatus according to claim 4.
[Claim 6]
　The blanking control unit, the differential clock signal transmitting circuit and the clock signal line from, as the predetermined differential signals, so that the clock signal for more than the predetermined period is output, the differential clock controlling the signal transmission circuit
　transmitting apparatus according to claim 4.
[Claim 7]
　The blanking control unit, after the signal of the predetermined second signal value is output to the differential clock signal the clock signal line from the transmission circuit, the clock signal is output within the blanking period as controls the differential clock signal transmitting circuit
　transmitting apparatus according to claim 5.
[8.]
　The blanking control unit, further wherein in synchronization with the start time of the blanking period of the data signal, from said data signal transmission circuit to said data signal lines, instead of the data signal, at least a predetermined data blanking signal to but is output, and controls the data signal transmission circuit
　transmitting apparatus according to claim 2.
[Claim 9]
　The blanking control unit, as the predetermined data blanking signal, said to inverted signal of the last signal value of the data signal is output, controls the data signal transmission circuit
　transmitting apparatus according to claim 8 .
[Claim 10]
　The blanking control unit, as the predetermined data blanking signals, such that the differential signal value is 1 is output, and controls the differential data signal transmission circuit
　transmitting apparatus according to claim 8.
[Claim 11]
　The blanking control unit, after the predetermined data blanking signal is output, the data signal in synchronization with the end time of the blanking period, to be output from the differential signal value is 0, the controlling the differential data signal transmission circuit
　transmitting apparatus according to claim 8.
[Claim 12]
　The blanking control unit, as the predetermined data blanking signal, the blanking so that differential signal values throughout is zero ranking period is output, and controls the differential data signal transmission circuit
　according transmitting apparatus according to claim 8.
[Claim 13]
　A first single-ended signal transmission circuit for outputting a first single-ended signal,
　the one signal output from any one of the differential clock signal transmitting circuit and the first single-ended signal transmission circuit to said clock signal line as to be made, the first transmission switching circuit for switching a path of the signal output,
　and a second single-ended signal transmission circuit for outputting a second single-ended signal,
　and the differential data signal transmission circuit to said data signal line the second way in which one signal output from one of the single-ended signal transmission circuit is made, and a second transmission switching circuit for switching a path of the signal output
　further comprising a
　transmission device according to claim 2.
[Claim 14]
　A data signal receiving circuit for receiving a data signal via a data signal line,
　a clock signal and a predetermined blanking signal outputted in synchronism with the blanking period of the data signal, via the clock signal line receiving a clock signal receiving circuit for
　receiving apparatus provided with.
[Claim 15]
　The data signal receiving circuit is a differential data signal receiving circuit for receiving via the data signal line a data signal of the differential as the data signal,
　the clock signal receiver circuit, a differential clock as the clock signal which receives a signal, a first signal value of the predetermined for over a predetermined period in synchronism with the start time of the blanking period of the data signal as the predetermined blanking signal is output so as to continue the difference a differential clock signal receiving circuit for receiving the dynamic blanking signal
　receiving apparatus according to claim 14.
[Claim 16]
　The differential data signal receiving circuit
　has a data signal termination circuit comprising the connected terminating resistor to the data signal lines,
　the differential clock signal receiving circuit,
　including connected terminating resistor to the clock signal line a clock signal termination circuit,
　based on the differential blanking signal, and a termination control circuit for turning off each of the termination resistors on the data signal termination circuit and said clock signal terminal circuits
　having
　of claim 15 the receiving device.
[Claim 17]
　The differential clock signal receiving circuit further
　wherein the end time of the blanking period of the data signal is output in synchronization with, via the clock signal line different predetermined differential signal from said differential blanking signal receiving Te,
　the termination control circuit,
　based on said predetermined differential signal, turning on each of the termination resistors on the data signal termination circuit and said clock signal terminal circuits
　receiving apparatus according to claim 16 .
[Claim 18]
　A first single-ended signal receiving circuit for receiving a first single-ended signal through the clock signal line,
　a first reception switching circuit for switching whether to receive the first single-ended signal,
　the a second single-ended signal receiving circuit for receiving a second single-ended signal through the data signal line,
　a second reception switching circuit for switching whether to receive the second single-ended signal
　further comprises
　the receiving apparatus according to claim 15.
[Claim 19]
　Outputs the clock signal to a clock signal line, and outputs the data signal to the data signal line, in synchronism with the blanking period of the data signal, and a transmitting device for outputting a predetermined blanking signal instead of the clock signal,
　the a data signal received via the data signal line, and a receiver for receiving said clock signal and said predetermined blanking signal via the clock signal line
　communication system comprising a.
[Claim 20]
　Oscillator for supplying said clock signal to said transmitting apparatus
　further comprising a
　communication system according to claim 19.
[Claim 21]
　The transmission apparatus includes
　a first single-ended signal transmission circuit for outputting a first single-ended signal,
　the one of the signal output of the clock signal and the first single-ended signal to the clock signal line is made so that a first transmission switching circuit for switching signals,
　and a second single-ended transmission circuit for outputting a second single-ended signal,
　the data signal and the second single-ended signal to the data signal line either to one of the signal output is performed, the second transmission switching circuit for switching signals
　comprises a,
　the receiving device,
　a first single receiving the first single-ended signal through the clock signal lines and the end signal receiving circuit,
　a first receiving switching circuit for switching whether to receive the first single-ended signal,
　the second thin A second single-ended signal receiving circuit for receiving via the ended signal the data signal line,
　a second reception switching circuit for switching whether to receive the second single-ended signal
　comprises
　in claim 19 communication system described.
[Claim 22]
　And outputting a clock signal to a clock signal line,
　and outputting the data signal to the data signal line,
　in synchronism with the blanking period of the data signal, to the clock signal line, a predetermined instead of the clock signal and outputting a blanking signal
　signal transmission method comprising.
[Claim 23]
　Receiving a data signal via a data signal line,
　a clock signal and a predetermined blanking signal outputted in synchronism with the blanking period of the data signal, comprising: receiving via a clock signal line
　signal receiving method comprising.
[Claim 24]
　And outputting a clock signal to a clock signal line,
　and outputting the data signal to the data signal line,
　in synchronism with the blanking period of the data signal, to the clock signal line, a predetermined instead of the clock signal Bed and outputting the ranking signal,
　comprising: receiving the data signal via the data signal line,
　and receiving the clock signal and the predetermined blanking signal via the clock signal line
　including Communication method.