Technical Field
[0001] The disclosure relates to a transmission device that transmits a signal, a
transmission method used in such a transmission device, and a communication system
including such a transmission device.
Background Art
[0002] In association with high functionality and multi-functionality of electronic
apparatuses in recent years, the electronic apparatuses are mounted with various devices
such as a semiconductor chip, a sensor, and a display device. A lot of pieces of data
are exchanged between these devices, and the amount of such data has been increased
with high functionality and multi-functionality of the electronic apparatuses.
Accordingly, the data are olten exchanged with use of a high-speed interface. The
high-speed interface is able to transmit and receive data at several Gbps, for example.
[0003] There have been disclosed various techniques in order to improve
communication performance at a high-speed interface. For example, PTLl and PTL2
each disclose a communication system that transmits three diJTerential signals by using
three transmission paths. Further, PTL 3 discloses a communication system that
performs pre-emphasis.
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Citation List
Patent Literature
[0004]
H06-261092
PTLl: Japanese Unexamined Patent Application Publication No.
PTL2: U.S. Patent No. 8064535
PTL3: Japanese Unexamined Patent Application Publication No. 2011-142382
Summary of the Invention
[0005] As described, it is desired to improve communication performance, and
further improvement of the communication performance rs expected 111 a
communication system.
[0006] It is desirable to provide a transmission device, a transmission method, and a
communication system that make it possible to improve communication performance.
[0007] A transmission device according to an embodiment of the disclosure
includes a driver section and a control section. The driver section is able to transmit a
data signal by using three or more predetermined number of voltage states and set
voltages in each of the voltage states. The control section sets an emphasis voltage
that is based on a transition among the predetermined number of the voltage states, and
thereby causes the driver section to perform emphasis.
[0008] A transmission method according to an embodiment of the disclosure
includes transmitting a data signal by using three or more predetermined number of
voltage states, and setting an emphasis voltage that is based on a transition among the
predetermined number ofthe voltage states, and thereby performing emphasis.
[0009] A communication system according lo an embodiment of the disclosure
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includes a transmission device and a reception device. The transmission device
includes a driver section and a control section. The driver section is able to transmit a
data signal by using three or more predetermined number of voltage states and set
voltages in each of the voltage stales. The control section sets an emphasis voltage
that is based on a transition among the predetermined number of the voltage states, and
thereby causes the driver section to perform emphasis.
[0010] In the transmission device, the transmission method, and the commw1ication
system according to the respective embodiments of the disclosure, the data signal is
transmitted by using the three or more predetermined number of voltage states. The
voltages in each of the voltage states are each settable. Further, the emphasis voltage
that is based on the transition among the predetermined number of the voltage states is
set, and thereby the emphasis is performed.
[0011] According to the transmission device, the transmission method, and the
communication system according to the respective embodiments of the disclosure, the
emphasis is performed by setting the emphasis voltage that is based on the transition
among the predetermined number of the voltage states, which makes it possible to
improve the communication performance. It is to be noted that the effects described
here are not necessarily limitative, and may have any of the effects described in the
disclosnre.
Brief Description of Drawings
[00 12] [FIG. 1 J FIG. I is a block diagram illustrating a configuration example of a
communication system according to an embodiment of the disclosure.
[FIG. 2] FIG. 2 is a diagram describing a voltage state of a signal transmitted and
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received by the communication system illustrated in FIG. 1.
[FIG. 3] FIG. 3 is another diagram describing a voltage state of a signal transmitted and
received by the communication system illustrated in FIG. 1.
[FIG. 4] FIG. 4 is a diagram describing a transition of a symbol transmitted and received
by the communication system illustrated in FIG. I.
[FIG. 5] FIG. 5 is a block diagram illustrating a configuration example of a transmitter
illustrated in FIG. 1.
[FIG. 6] FIG. 6 is a table illustrating an operation example of a transmission symbol
generator illustrated in FIG. 5.
[FIG. 7] FIG. 7 is a block diagram illustrating a configuration example of an output
section illustrated in FIG. 5.
[FIG. 8] FIG. 8 is a block diagram illustrating a configuration example of a driver
section illustrated in FIG. 7.
[FIG. 9] FIG. 9 is a table illustrating an operation example of an emphasis controller
illustrated in FIG. 7.
[FIG. 1 OA] FIG. 1 OA is a diagram describing an operation example of the driver section
illustrated in FIG. 7.
[FIG. JOB] FIG. lOB is a diagram describing another operation example of the driver
section illustrated in FIG. 7.
[FIG. I OC] FIG. lOC is a diagram describing another operation example of the driver
section illustrated in FIG. 7.
[FIG. 11 A] FIG. II A is a diagram describing another operation example of the driver
section illustrated in FIG. 7.
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[FIG. 11 B] FIG. 11B is a diagram describing another operation example of the driver
section illustrated in FIG. 7.
[FIG. 11 C] FIG. 11 C is a diagram describing another operation example of the driver
section illustrated in FIG. 7.
[FIG. 12A] FIG. 12A is a diagram describing another operation example of the driver
section illustrated in FIG 7.
[FlG. 12B] FIG 12B is a diagram describing another operation example of the driver
section illustrated in FIG. 7.
[FIG. 12C] FIG. 12C is a diagram describing another operation example of the driver
section illustrated in FIG. 7.
[FIG. 13] FlG. 13 is a block diagram illustrating a configuration example of a receiver
illustrated in FIG. 1.
[FIG. 14] FIG. 14 is a diagram describing an example of a receiving operation of the
receiver illustrated in FIG. 13.
[FIG. 15A] FIG. 15A is a timing waveform chart illustrating an operation example of a
transmitter illustrated in FIG. 7.
[FIG. 15B] FIG. 15B is a timing waveform chart illustrating another operation example
of the transmitter illustrated in FIG. 7.
[FIG. 15C] FIG. 15C is a timing wavetom1 chart illustrating another operation example
of the transmitter illustrated in FIG. 7.
[FIG. 16A] FIG. 16A is a timing waveform chmi illustrating an operation example of the
communication system illustrated in FIG. 1.
[FIG. 16B] FIG. 16B is a timing waveform chart illustrating another operation example
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of the communication system illustrated in FIG. 1.
[FIG. 16C] FIG. 16C is a timing waveform chart illustrating another operation example
of the communication system illustrated in FIG. 1.
[FIG. 16D] FIG. 16D is a timing waveform chart illustrating another operation example
of the communication system illustrated in FIG. 1.
[fiG. 16E] FIG. 16E is a timing waveform chart illustrating another operation example
of the communication system illustrated in FIG. 1.
[FIG. 17 A] FIG. 17 A is an eye diagram illustrating an example of a signal in a case
where there is no transmission path, when performing de-emphasis operation.
[FIG. 17B] FIG. 17B is an eye diagram illustrating an example of a signal in a case of
having passed through a transmission path, when performing de-emphasis operation.
[FIG. !SA] FIG. 18A is an eye diagram illustrating an example of a signal in a case
where there is no transmission path, when not performing de-emphasis operation.
[FIG. 18B] FIG. 18B is an eye diagram illustrating an example of a signal in a case of
having passed through a transmission path, when not performing de-emphasis
operation.
(FIG. 19A] FIG. 19A is a timing waveform diagram illustrating an operation exan1plc of
a communication system according to a comparative example.
[FIG. 19B] FIG. 19B is a timing waveform diagram illustrating another operation
example of the communication system according to the comparative example.
[FIG. 1 9C] FIG. 19C is a timing waveform diagram illustrating another operation
example of the communication system according to the comparative example.
[FIG. 19D] FTG. 19D is a timing waveform diagram illustrating another operation
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example of' the communication system according lo the comparative example.
[FIG. 19E] FIG. 19E is a liming waveform diagram illustrating another operation
example ofthe cDmmunication system according to the comparative example.
(FIG. 20] fiG. 20 is a block diagram illustrating a configuration example of a transmitter
according to a modification example.
[FIG. 21] FIG. 21 is a block diagram illustrating a configuration example of an output
section illustrated in FIG. 20.
[FIG. 22] FIG. 22 is a diagram describing a voltage state of a signal transmitted and
received by a communication system according to another modification example.
(FIG. 23] FIG. 23 is a diagram describing a voltage state of a signal transmitted and
received by a communication system according to another modification example.
[FIG. 24] FIG. 24 is a perspective view illustrating an appearance configuration of a
smartphone to which a communication system according to an embodiment is applied.
(FIG. 25] FIG. 25 is a block diagram illustrating a configuration example of an
application processor to which a communication system according to an embodiment is
applied.
[FIG. 26] FIG. 26 is a block diagram illustrating a configuration example of an image
sensor to which a commlmication system according to an embodiment is applied.
[FIG. 27] FIG. 27 is a block diagram illustrating a configuration example of a vehicle
control system to which a communication system according to an embodiment is
applied.
Modes for Carrying Out the Invention
[0013] In the following, some embodiments of the disclosme are described in detail
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with reference to the drawings. l1 is to be noted that descriptions are given in the
following order.
1. Embodiments
2. Application Examples
<1. Embodiments>
[Configuration Example]
[00 14] FIG l illustrates a configuration example of a communication system
(communication system l) according to an embodiment. The communication system 1
achieves the improvement of communication performance by de-emphasis.
[0015] The communication system 1 includes a transmission device 10, a
transmission path lOO, and a reception device 30. The transmission device I 0 includes
three output terminals To utA, ToutB, and ToutC. The transmission path l 00 includes
lines 11 OA, ll OB, and 11 OC. The reception device 30 includes three input terminals
TinA, TinB, and TinC. In addition, the output terminal ToutA of the transmission
device I 0 and the input terminal TinA of the reception device 30 are coupled to each
other via the line 11 OA, the output tennina1 ToutB of the transmission device 10 and the
input terminal TinB of the reception device 30 are coupled to each other via the line
11 OB, and the output terminal ToutC of the transmission device 10 and the input
terminal TinC of the reception device 30 are coupled to each other via the line llOC.
In this example, each of the lines 11 OA to 11 OC has a characteristic impedance of about
50 [OJ.
[00 16] The transmission device 10 outputs a signal SIGA ±rom the output terminal
ToutA, outputs a signal SIGB from the output terminal ToutB, and outputs a signal
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SIGC from the output terminal ToutC. Further, the reception device 30 receives the
signal SlGA via the input terminal TinA, receives the signal SIGB via the input terminal
TinB; and receives the signal SIGC via the input terminal Tin C. Each of the signals
SIGA, SIGB, and SIGC may take three voltage states SH, SM, and SL.
l 00 17] FIG. 2 illustrates the three voltage states SH, SM, and SL. The voltage
state SH is a state that corresponds to three high level voltages VH (VHO, VHl, and
VH2). Among the high level voltages VHO, VHl, and VH2, the high level voltage
VHO is the lowest voltage. The high level voltage VH2 is the highest voltage. The
voltage state SM is a state that corresponds to three intem1ediate level voltages VM
(VMO, VMlplus, and VMlminus). Among the intermediate level voltages VMO,
VMlplus, and VMlminus, the intermediate level voltage VMlminus is the lowest
voltage. The intermediate level voltage VMlplus is the highest voltage. The voltage
state SL is a state that corresponds to three low level voltages VL (VLO, VLl, and VL2).
Among the low level voltages VLO, VLl, and VL2, the low level voltage VLO is the
highest voltage. The low level voltage VL2 is the lowest voltage. The high level
voltage VH2 is a high level voltage in a case of not applying de-emphasis. The
intermediate level voltage VMO is an intermediate level voltage in a case of not
applying de-emphasis. The low level voltage VL2 is a low level voltage in a case of
not applying de-emphasis.
[00 18] FIG. 3 illustrates voltage states of the signals SIGA, SIGB, and SIGC. The
using the three signals SIGA, SIGB, and SIGC. For example, in a case of transmitting
the symbol "+x", the transmission device 10 sets the signal SIGA to the voltage state SH,
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sets the signal SIGB to the voltage state SL, and sets the signal SIGC to the voltage
state SM, In a case of transmitting the symbol "-x", the transmission device 10 sets
the signal" SIGA to the voltage state SL, sets the signal S!GB to the voltage state Sl-1,
and sets the signal SIGC to the voltage state SM, ln a case of transmitting the symbol
"+y", the transmission device 10 sets the signal SIGA to the voltage state SM, sets the
signal SIGB to the voltage state SH, and sets the signal SIGC to the voltage state SL
In a case of transmitting the symbol "-y", the transmission device 10 sets the signal
SIGA to the voltage state SM, sets the signal SIGB to the voltage state SL, and sets the
signal SIGC to the high level voltage SR In a case of transmitting the symbol "+z",
the transmission device !0 sets the signal SIGA to the voltage state SL, sets the signal
SlGB to the voltage state SM, and sets the signal SIGC to the voltage state SH. In a
case of transmitting the symbol "-z", the transmission device 10 sets the signal SIGA to
the voltage state SH, sets the signal SIGB to the voltage state SM, and sets the signal
SIGC to voltage state SL.
[0019] The transmission path 100 transmits a sequence of a symbol, using such
signals SIGA, SIGB, and SIGC In other words, the three lines IIOA, 11 OB, and II OC
function as one lane through which the sequence of the symbol is transmitted,
(Transmission Device I 0)
[0020] As illustrated m FIG I, the transmission device I 0 includes a clock
generator 11, a processor 12, and a transmitter 20,
[0021] The clock generator 11 generates a clock signal TxCK The clock signal
TxCK has a frequency of 2,5 [GHz], for example, It is to be noted that the clock
signal TxCK is not limited thereto, and may also have a frequency of L25 [GHz], for
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example, in a case of using what is called a half rate architecture to configure a circuit in
the transmission device 10. The clock generator ll includes, for example, a PLL
(phase-locked loop), and generates the clock signal TxCK on the basis of a reference
clock (not illustrated) to be supplied fi-om the outside of the transmission device l 0, for
example. Thereafter, the clock generator 11 supplies this clock signal TxCK to the
processor 12 and the transmitter 20.
[0022] The processor 12 generates transition signals TxFO to TxF6, TxRO to TxR6,
and TxPO to TxP6 by performing predetermined processing. Here, a set of transition
signals TxFO, TxRO, and TxPO indicates a transition of a symbol in a sequence of the
symbol to be transmitted by the transmission device 10. Likewise, a set of transition
signals TxFl, TxRl, and TxPl indicates a transition of the symbol, a set of transition
signals TxF2, TxR2, and TxP2 indicates a transition of the symbol, a set of transition
signals TxF3, TxR3, and TxP3 indicates a transition of the symbol, a set of transition
signals TxF4, TxR4, and TxP4 indicates a transition of the symbol, a set of transition
signals TxF5, TxR5, and TxP5 indicates a transition of the symbol, and a set of
transition signals TxF6, TxR6, and TxP6 indicates a transition of the symbol. In other
words, the processor 12 generates seven sets of transition signals. In the following,
transition signals TxF, TxR, and TxP are used as appropriate to represent any set among
the seven sets of transition signals.
[0023] FIG. 4 illustrates a relationship between the transition signals TxF, TxR, and
TxP and the transitions of the symbols. A three-digit numerical value assigned to each
transition indicates values of the transition signals TxF, T xR, and TxP in this order.
roo24J The transition signal TxF (Flip) causes the symbol to make a transition
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bct\vccn 11+X 11 and "-x~~, causes the symbol to n1akc a transition betv..reen 11 +)"1 and "-/1
,
and causes the symbol to make a transition between "+z" and "-z". SpeciJ!cally, in a
case where the transition signal TxF is "!",the symbol is caused to make a transition to
change a polarity thereof (for example, from "+x" to "~x"), and in a case where the
transition signal TxF is "0", such a transition is not performed.
[0025] In a case where the transition signal TxF is "0", the transition signals TxR
(Rotation) and TxP (Polarity) cause the symbol to make a transition between "+x" and
those other than "-x", between "+y" and those other than "-y", and between "+z" and
those other than "-z". Specifically, in a case where the transition signals TxR and TxP
are "l" and "0", the symbol, while keeping the polarity, is caused to make a transition
clockwise (for example, from "+x" to "+y") in FIG 4. In a case where the transition
signals TxR and TxP are "l" and "l ", the symbol is caused to change the polarity and
transition clockwise (for example, from "+x" to "-y") in FIG 4. Further, in a case
where the transition signals TxR and TxP are "0" and "0", the symbol, while keeping the
polarity, is caused to make a transition counterclockwise (for example, from "+x" to
"+z") in FIG 4. In a case where the transition signals TxR and TxP are "0" and "I",
the symbol is caused to change the polarity and transition counterclockwise (for
example, from "+x" to "-z") in FIG. 4.
[0026] The processor l 2 generates seven sets of such transition signals TxF, TxR,
and TxP. Further, the processor 12 supplies these seven sets of transition signals TxF,
TxR, and TxP (transition signals TxFO to TxF6, TxRO to TxR6, and TxPO to TxP6) to
the transmitter 20.
[0027] The transmitter 20 generates the signals SlGA, SIGB, and SJGC on the basis
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of the transition signals TxFO to TxF6, TxRO lo TxR6, and TxPO to TxP6.
[0028] FIG. 5 illustrates a configuration example of lhe lransmiller 20. The
transmitter 20 includes serializers 21 F, 21 R, and 21 P, a transmission symbol generator
22, and an output section 26.
[0029] The serializcr 21 F generates a transition signal TxF9 by serializing the
transition signals TxFO to TxF6 in this order on the basis of the transition signals TxFO
to TxF6 and the clock signal TxCK. The serializer 21 R generates a transition signal
TxR9 by serializing the transition signals TxRO to TxR6 in this order on the basis of the
transition signals TxRO to TxR6 and the clock signal TxCK. The serializer 21P
generates a transition signal TxP9 by serializing the transition signals TxPO to TxP6 in
this order on the basis of the transition signals TxPO to TxP6 and the clock signal TxCK.
[0030] The transmission symbol generator 22 generales symbol signals Txl, Tx2,
and Tx3 and symbol signals Dl, D2, and D3 on the basis of the transition signals TxF9,
TxR9, and TxP9 and the clock signal TxCK. The transmission symbol generator 22
includes a signal generator 23 and a Hip-flop 24.
[0031] The signal generator 23 generates the symbol signals Txl, Tx2, and Tx3
relating to a current symbol NS on the basis of the transition signals TxF9, TxR9, and
TxP9 and symbol signals Dl, D2, and D3. Specifically, the signal generator 23
determines, on the basis of the symbol indicated by the symbol signals Dl, D2, and D3
(a symbol DS that is earlier by one symbol) and the transition signals TxF9, TxR9, and
TxP9, the cnrrent symbol NS as illustrated in FIG 3 and onlputs the symbol NS as the
symbol signals Txl, Tx2, and Tx3.
[0032] The flip-flop 24 performs sampling of the symbol signals Txl, Tx2, and Tx3
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on the basis of the clock signal TxCK, and outputs results of the sampling, respectively,
as the symbol signals D I, D2, and D3.
[0033) FIG. 6 illustrates an operation example of the transmission symbol generator
22. This FIG. 6 illustrates the symbol NS to be generated on the basis of the symbol
DS indicated by the symbol signals Dl, D2, and D3 and the transition signals TxF9,
TxR9, and TxP9. A case where the symbol DS is "+x" is described as an example.
In a case where the transition signals TxF9, TxR9, and TxP9 are "000", the symbol NS
is "+z". In a case where the transition signals TxF9, TxR9, and TxP9 are "001 ", the
symbol NS is "~z". In a case where the transition signals TxF9, TxR9, and TxP9 are
"010", the symbol NS is "+y". In a case where the transition signals TxF9, TxR9, and
T xP9 are "0 11 ", the symbol NS is "~y". In a case where the transition signals TxF9,
TxR9, and TxP9 are "lxx", the symbol NS is "~x". Here, "x" indicates that any one of
"I" and "0" may be adopted. The same applies to a case where tbe symbol DS is any
of !l_x", 11+y'\ ~~-y'\ "+z11
, and ~~-z~~.
[0034] The output section 26 generates the signals SIGA, SIGB, and SIGC on the
basis of the symbol signals Txl, Tx2, and Tx3, the symbol signals Dl, D2, and D3, and
the clock signal TxCK.
[0035] FIG. 7 illnstrates a configuration example of the output section 26. The
output section 26 includes a driver controller 27N, a driver controller 27D, emphasis
controllers 28A, 28B, and 28C, and driver sections 29A, 298, and 29C.
[0036] The driver controller 27N generates signals MAINAN, SUBAN, MAINBN,
SUBBN, MAINCN, and SUBCN on the basis of the symbol signals Txl, Tx2, Tx3, and
the clock signal TxCK relating to the current symbol NS. Specilically, the driver
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controller 27N calculates a voltage state of each of the signals S!GA, SIGB, and SIGC
on the basis of the current symbol NS indicated by the symbol signals Txl, Tx2, and
Tx3, as illustrated in FIG 3. Further, in a case of setting the signal SIGA to the voltage
state SI-l, for example, the driver controller 27N sets the signals MAINAN and SUBAN
to "I" and "0", respectively. In a case of setting the signal SIGA to the voltage state
SL, the driver controller 27N sets the signals MAIN AN and SUB AN to "0" and "1 ",
respectively. In a case of setting the signal SIGA to the voltage state SM, the driver
controller 27N sets both the signals MAINAN and SUBAN to "1" or "0". The same
applies to the signals MAINBN and SUBBN, and the signals MAINCN and SUBCN.
Further, the driver controller 27N supplies the signals MAINAN and SUBAN to the
emphasis controller 28A, supplies the signals MAINBN and SUBBN to the emphasis
controller 28B, and supplies the signals MAINCN and SUBCN to the emphasis
controller 28C.
[0037] The driver controller 27D generates signals MAIN AD, SUBAD, MAINBD,
SUBBD, MAIN CD, and SUBCD on the basis of the symbol signals Dl, D2, and D3
relating to the symbol DS that is earlier by one symbol and the clock signal TxCK.
The driver controller 27D includes the same circuit configuration as that of the driver
controller 27N. Further, the driver controller 27D supplies the signals MAJNAD and
SUBAD to the emphasis controller 28A, supplies the signals MAINBD and SUBBD to
the emphasis controller 28B, and supplies the signals MAINCD and SUBCD to the
emphasis controller 28C.
l 003 8] The emphasis controller 28A generates eight signals UPAAO, UPABO.
UPAAl, UPABI, DNAAO, DNABO, DNAAI, and DNABl on the basis of the signals
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MAINAN and SUBAN and the signals MAINAD and SUBAD. The driver section
69A generates the signal SIGA on the basis of the eight signals UPAAO, UPABO,
UPAAI, UPABl, DNAAO, DNABO, DNAAl, and DNABl.
[0039] The emphasis controller 28B generates eight signals UPBAO, UPBBO,
UPBAl, UPBB I, DNBAO, DNBBO, DNBA I, and DNBB 1 on the basis of the signals
MAINBN and SUBBN and the signals MAINBD and SUBBD. The driver section
69A generates the signal SIGB on the basis of the eight signals UPBAO, UPBBO,
UPBAl, UPBBl, DNBAO, DNBBO, DNBAl, and DNBBI.
[0040] The emphasis controller 28C generates eight signals UPCAO, UPCBO,
UPCAI, UPCBl, DNCAO, DNCBO, DNCAl, and DNCBl on the basis of the signals
MAlNCN and SUBCN and the signals MAINCD and SUBCD. The driver section
69A generates the signal SIGC on the basis of the eight signals UPCAO, UPCBO,
UPCAl, UPCBl, DNCAO, DNCBO, DNCAI, and DNCBI.
[0041] FIG. 8 illustrates a configuration example of the driver section 29A. It is to
be noted that the same applies to the drive sections 298 and 29C. The driver section
29A includes M number of circuits UAO (circuits UA01 to UAOM), N number of circuits
UBO (circuits UB01 to UBON), M number of circuits UAl (circuits UAI 1 to UAlM), N
number of circuits UBI (circuits UB1 1 to UBlN), M number of circuits DAO (circuits
DA01 to DAOM), N number of circuits DBO (circuits DB01 to DBON), M number of
circuits DAI (circuits DAI 1 to DAIM), and N number of circuits DB! (circuits DBI 1 to
DB IN). Here, "M" is greater than "N". It is to be noted that this is non-limiting, and,
"M" may altematively be less than "N", for example.
[0042] Each of the circuits UA01 to UAOM, UB01 to UBON, UAJ 1 to UAIM, and
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UB 11 to UB 1 N includes a transistor 91 and a resister 92. ln this example, the transistor
91 is an N channel MOS (Metal Oxide Semiconductor) type FET (Field Effect
Transistor): ·In each of the circuits UA01 to UAOM, a gate of the transistor 91 is
supplied with the signal UPAAO, a drain thereof is supplied with a voltage Vl; and a
source thereof is coupled to one end of the resistor 92. In each of the circuit UB01 to
UBON, a gate of the transistor 91 is supplied with the signal UP ABO, a drain thereof is
supplied with a voltage Vl, and a source thereof is coupled to one end of the resistor 92.
In each of the circuits UAI1 to UAIM, a gate of the transistor 91 is supplied with the
signal UPAAJ, a drain thereof is supplied with a voltage Vl, and a somcc thereof is
coupled to one end of the resistor 92. In each of the circuits UBI 1to UBIN, a gate of
the transistor 91 is supplied with the signal UPABl, a drain thereof is supplied with a
voltage VI, and a source thereof is coupled to one end of the resistor 92. In each of
the circuits UA01 to UAOM, UB01 to UBON, UAl1 to UAIM, and UB11 to UBIN, one end
of the resistor 92 is coupled to the source of the transistor 91, and the other end thereof
is coupled to an output terminal ToutA. A sum of a resistance value in an ON state of
the transistor 91 and a resistance value of the resistor 92 is "50x(2xM+2xN)" [0], in
this example.
[0043] Each of the circuits DA01 to DAOM, DB01 to DBON, DA1 1 to DAIM, and
DB 11 to DB IN includes a resistor 93 and a transistor 94. In each of the circuits DA01
to DAOM, DB01 to DBON, DAh to DAJM, and DBl1 to DB IN, one end of the resistor 93
is coupled to the output terminal To utA, and the other end thereof is coupled to a drain
of the transistor 94. The transistor 94 is anN channel MOS type FET, in this example.
In each of the circuits DA01 to DAOM, a gate of the transistor 94 is supplied with the
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signal DNAAO, a drain thereof is coupled to the other end of the resistor 93, and a
source thereof is grounded, In each of the circuits DB0 1 to DBON, a gate of the
transistor 94 is supplied with the signal DNABO, a drain thereof is coupled to the other
end of the resistor 93, and a source thereof is grounded, In each of the circuits DA 11
to DA 1M, a gate of the transistor 94 is supplied with the signal DNAAI, a drain thereof
is coupled to the other end of the resistor 93, and a source thereof is grounded, In each
of the circuits DBI 1 to DB!N, a gate of the transistor 94 is supplied with the signal
DNABI, a drain thereof is coupled to the other end of the resistor 93, and a source
thereof is grounded, A sum of a resistance valne of the resistor 93 and a resistance
value in an ON state of the transistor 94 is "50x(2xM+2xN)" [OJ, in this example,
[0044] FlG 9 illustrates an operation example of the emphasis controller 28A
FIGs, lOA to lOC each illustrate an operation example of the driver section 29A when
the signal SIGA is set to a voltage state SR FIGs, !lA to llC each illustrate an
operation example of the driver section 29A when the signal SIGA is set to a voltage
state SM, FIGs, 12A to 12C each illustrate an operation example of the driver section
29A when the signal S!GA is set to a voltage state SL In FIGs, lOA to IOC, !lA to
IJC, and 12A to 12C, among the circuits UA0 1 to UAOM, UB01 to UBON, UAh to
UAIM, and UB1 1 to UBIN, circuits each indicated by a solid line indicate that the
transistor 91 is being turned ON, and circuits each indicated by a broken line indicate
that the transistor 91 is being turned OFF Similarly, among the circuits DA01 to
DAOM, DB01 to DBON, DA! 1 to DA!M, and DB1 1 to DB!N, circuits each indicated by a
solid line indicate that the transistor 94 is being turned ON, and circuits each indicated
by a broken line indicate that the transistor 94 is being turned OFE It is to be noted
18
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that description is given here using the emphasis controller 28A and the driver section
29A as examples. However, the same also applies to the emphasis controller 28B and
· the driver section 29B, and the emphasis controller 28C and the driver section 29C
(0045] In a case where both the signals MAINAN and SUBAN relating to the
culTent symbol NS are "0" or"!", as illustrated in FIGS. llA to llC, the emphasis
controller 28A sets the voltage of the signal SIGA to any of three intermediate level
voltages VMO, VMlplus, and VMlminus.
[0046] Specifically, as illustrated in FIG, 9, for example, in a case where the signals
MAINAD and SUBAD relating to the symbol DS that is earlier by one symbol are "0"
and "0", and the signals MAINAN and SUBAN relating to the current symbol NS are
"0" and "0", the emphasis controller 28A sets the signals UPAAO, UPABO, UPAAl,
UPABJ, DNAAO, DNABO, DNAAl, and DNABl to "11001100". This causes the
transistors 91 in the circuits UA01 to UAOM and UB01 to UBON to be turned ON and the
transistors 94 in the circuits DA01 to DAOM and DB01 to DBON to be turned ON, in the
driver section 29A, as illustrated in FIG. llB. As a result, the voltage of the signal
SIGA becomes the intermediate level voltage VMO, and an output terminating resistor
(output impedance) of the driver section 29A becomes about 50 (0]. The same also
applies to the case where the signals MAIN AD and SUB AD relating to the symbol DS
that is earlier by one symbol are "l" and "I" and the signals MAIN AN and SUB AN
relating to the current symbol NS is "0" and "0". Further, the same also applies to the
case where the signals MA!NAD and SUBAD relating to the symbol DS that is earlier
by one symbol arc "0" and "0" and the signals MAINAN and SUBAN relating to the
current symbol NS are "l " and "1 ". Further, the same also applies to the case where
19
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the signals MAINAD and SUDAD relating to the symbol DS that is earlier by one
symbol are "l" and "1" and the signals MAIN AN and SUB AN relating to the current
·symbol NS are "I" and"!".
[0047] Further, in a case where the signals MAINAD and SUBAD relating to the
symbol DS that is earlier by one symbol are "0" and "l" and the signals MAIN AN and
SUBAN relating to the current symbol NS are "0" and "0", for example, the emphasis
controller 28A sets the signals UPAAO, UPABO, UPAAI, UPABl, DNAAO, DNABO,
DNAAJ, and DNABl to "11011000". This causes the transistors 91 in the circuits
UA01 to UAOM, UB01 to UBON, and UB1 1 to UBIN to be turned ON and the transistors
94 in the circuits DA01 to DAOM to be turned ON in the driver section 29A, as
illnstrated in FIG. l!A. As a result, the voltage of the signal SIGA becomes the
intermediate level voltage VMl plus, and the output terminating resistor (output
impedance) of the driver section 29A becomes about 50 [Q]. The same applies to the
case where the signals MAINAD and SUBAD relating to the symbol DS that is earlier
by one symbol are "0" and "1" and the signals MAINAN and SUBAN relating to the
current symbol NS arc "I" and "1 ".
[0048] Further, in a case where the signals MA!NAD and SUBAD relating to the
symbol DS that is earlier by one symbol are "l" and "0" and the signals MAIN AN and
SUBAN relating to the current symbol NS arc "0" and "0", for example, the emphasis
controller 28A sets the signals UPAAO, UPABO, UPAAl, UPABl, DNAAO, DNABO,
DNAAl, and DNABl to "10001101". This causes the transistors 91 in the circuits
UA01 to UAOM to be turned ON and the transistors 94 in the circuits DA01 to DAOM,
DB01 to DBON, and DB1 1 to DBIN to be turned ON, in the driver section 29A, as
20
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illustrated in FIG. 11C. As a result, the voltage of the signal SIGA becomes the
intermediate level voltage VM1minus, and the output terminating resistor (output
impedance) of the driver section 29A becomes about 50 [!:2]. The same applies to the
case where the signals MAINAD and SUBAD relating to the symbol DS that is earlier
by one symbol are "1" and "0" and the signals MAINAN and SUBAN relating to the
cunentsymholNS are"!" and "1".
[0049] Further, in a case where the signals MAINAN and SUBAN relating to the
cunent symbol NS are "0" and "l ",the emphasis controller 28A sets the voltage of the
signal SIGA to any of the three low level voltages VLO, VL 1, and VL2, as illustrated in
FIGs. 12A to 12C.
[0050] Specifically, in a case where the signals MAINAD and SUBAD relating to
the symbol DS that is earlier by one symbol are "I" and "0" and the signals MAIN AN
and SUBAN relating to the cunent symbol NS are "0" and "1 ", for example, the
emphasis controller 28A sets the signals UPAAO, UPABO, UPAAl, UPABl, DNAAO,
DNABO, DNAAl, and DNABJ to "00001111". This causes the transistors 94 in the
circuits DAOr to DAOM, DB01 to DBON, DAI 1 to DAlM, and DB1 1 to DBJN to be turned
ON, in the driver section 29A, as illustrated in FIG. 12C. As a result, the voltage of the
signal SIGA becomes the low level voltage VL2, and the output terminating resistor
(output impedance) of the driver section 29A becomes about 50 [!:2].
[0051] Further, in a case where the signals MAINAD and SUBAD relating to the
symbol DS that is earlier by one symbol are "0" and "0" and the signals MAINAN and
SUBAN relating to the current symbol NS are "0" and "1 ", for example, the emphasis
controller 28A sets the signals UPAAO, UPABO, UPAAI, UPABI, DNAAO, DNABO,
21
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DNAA!, and DNAB! to "01001110". This causes the transistors 91 in the circuits
UB01 to UBON to be turned ON and the transistors 94 in the circuits DA01 to DAO:v~,
DB01 to DBON, and DA1 1 to DAIM to be turned ON, in the driver section 29A, as
illustrated in FIG. 12B. As a resnlt, the voltage of the signal SIGA becomes the low
level voltage VLI, and the output terminating resistor (output impedance) of the driver
section 29A becomes about 50 [0]. The same applies to the case where the signals
MAlNAD and SUBAD relating to the symbol DS that is earlier by one symbol are "1"
and "1" and the signals MAlNAN and SUB AN relating to the current symbol NS are
11011 and 11 111
•
[0052] Further, in a case where the signals MAINAD and SUBAD relating to the
symbol DS that is earlier by one symbol are "0" and "1" and the signals MATNAN and
SUB AN relating to the cunent symbol NS are "0" and "1 ", for example, the emphasis
controller 28A sets the signals UPAAO, UPABO, UPAAl, UPABl, DNAAO, DNABO,
DNAAl, and DNABl to "01011010". This causes the transistors 91 in the circuits
UB01 to UBON and UB1 1 to UBIN to be turned ON and the transistors 94 in the circuits
DA01 to DAOM and DA1 1 to DAIM to be turned ON, in the driver section 29A, as
illustrated in FlG. 12B. As a result, the voltage of the signal SIGA becomes the low
level voltage VLO, and the ontput terminating resistor (output impedance) of the driver
section 29A becomes about 50 [Q].
[0053] Fmiher, in a case where the signals MAINAN and SUBAN relating to the
current symbol NS are "1" and "0", the emphasis controller 28A sets the voltage of the
signal SlGA to any of the three high level voltages VHO, VI-11, and VI-12, as illustrated
in FIGs. 1 OA to 1 OC.
22
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[0054] Specifically, in a case where the signals MATNAD and SUBAD relating to
the symbol DS that is earlier by one symbol are "0" and "1" and the signals MAIN AN
and SUBAN relating to the current symbol NS are "1" and "0", for example, the
emphasis controller 28A sets the signals UPAAO, UPABO, UPAA1, UPAB1, DNAAO,
DNABO, DNAAl, and DNABl to "11110000". This causes the transistors 91 in the
circuits UA01 to UAOM, UB01 to UBON, UA1 1 to UAlM, and UB1 1 to UBlN to be turned
ON in the driver section 29A, as illustrated in FIG. lOA. As a result, the voltage of the
signal STGA becomes the high level voltage VH2, and the output terminating resistor
(output impedance) of the driver section 29A becomes about 50 [f.!].
[0055] Further, in a case where the signals MAINAD and SUBAD relating to the
symbol DS that is earlier by one symbol are "0" and "0" and the signals MAIN AN and
SUB AN relating to the current symbol NS are "1" and "0", for example, the emphasis
controller 28A sets the signals UPAAO, UPABO, UPAAl, UPABl, DNAAO, DNABO,
DNAAl, and DNABl to "10110001". This causes the transistors 91 in the circuits
UA01 to UAOM, UA1 1 to UA 1M, and UB l1 to UBlN to be turned ON and the transistors
94 in the circuits DB1 1 to DBlN to be turned ON, in the driver section 29A, as
illustrated in FIG. 1 OB. As a result, the voltage of the signal SIGA becomes the high
level voltage VHl, m1d the output terminating resistor (output impedance) of the driver
section 29A becomes about 50 [f.!]. The same applies to the case where the signals
MAIN AD and SUBAD relating to the symbol DS that is earlier by one symbol arc "1"
and "1" and the signals MAIN AN and SUBAN relating to the current symbol NS are
[0056] Further, in a case where the signals MAINAD and SUBAD relating to the
23
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symbol DS that is earlier by one symbol are "1" and "0" and the signals MAIN AN and
SUBAN relating to the cnnent symbol NS are "1" and "0", for example, the emphasis
controller 28A sets the signals UPAAO, UPABO, UPAA1, UPAB1, DNAAO, DNABO,
DNAAI, and DNABl to "10100101'~. This causes the transistors 91 in the circuits
UA01 to UAOM and UAI 1 to UAlM to be turned ON and the transistors 94 in the circuits
DB01 to DBON and DB 11 to DBlN to be turned ON, in the driver section 29A, as
illustrated in FIG. 1 OC. As a result, the voltage of the signal SIGA becomes the high
level voltage VHO, and the output terminating resistor (output impedance) of the driver
section 29A becomes about 50 [Q].
[0057] In this way, the output section 26 sets the voltage states at the output
terminals ToutA, ToutB, and ToutC on the basis of the current symbol NS, and sets the
voltage level at each voltage state on the basis of the current symbol NS and the symbol
DS that is earlier by one symbol. At this time, the transmission device I 0 operates as a
so-called 2-tap FIR (Finite Impulse Response) filter and performs de-emphasis
operation. This allows the communication system 1 to improve communication
performance.
(Reception Device 30)
[0058] As illustrated in FIG. I, the reception device 30 includes a receiver 40 and a
processor 32.
[0059] The receiver 40 receives the signals SIGA, SIGB, and SIGC, and generates
transition signals RxF, RxR, and RxP and a clock signal RxCK on the basis of the
signals SIGA, SIGB, and SlGC
[0060] FIG. 13 illustrates a configuration example of the receiver 40. The receiver
24
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40 includes resistors 41A, 41B, and 41C, switches 42A, 42B, and 42C, amplifiers 43A,
43B, and 43C, a clock generator 44, ilip-f1ops 45 and 46, and a signal generator 47.
[0061] Thercsistors 41A, 41B, and 41C each serve as a lenninatingresistor of the
communication system 1. In this example, the resistance value is about 50 [n J. One
end of the resistor 41 A is coupled to the input terminal TinA and is supplied with the
signal SIGA. The other end of the resistor 41A is coupled to one end of the switch
42A. One end of the resistor 41B is coupled to the input terminal TinB and is supplied
with the signal SIGB. The other end of the resistor 41B is coupled to the switch 42B.
One end of the resistor 41C is coupled to the input terminal TinC and is supplied with
the signal S!GC, and the other end of the resistor 41 C is coupled to one end of the
switch42C.
[0062] One end of the switch 42A is coupled to the other end of the resistor 41A,
and the other end of the switch 42A is coupled to the other ends of the switches 42B and
42C. One end of the switch 42B is coupled to the other end of the resistor 4JB, and
the other end of the switch 42B is coupled to the other ends of the switches 42A and
42C. One end of the switch 42C is conpled to the other end of the resistor 41 C, and
the other end of the switch 42C is coupled to the other ends of the switches 42A and
42B. ln the reception device 30, switches 42A, 42B, and 42C each are set to the ON
state, and the resistors 41 A to 41 C each serve as a terminating resistor.
[0063] A positive input terminal of the amplifier 43A is coupled to a negative input
tem1inal of the amplifier 43C and one end of the resistor 41A, and is supplied with the
signal STGA. A negative input terminal of the amplifier 43A is coupled to a positive
input terminal of the amplifier 43B and one end of the resistor 41B, and is snpplied with
25
SP366204
signal SIGB. The positive input terminal of the amplifier 43B is coupled to the
negative input terminal of the amplifier 43A and the one end of the resistor 41 B, and is
supplied with the signal SIGB. A negative input terminal of the amplifier 43B is
coupled loa positive input terminal of the amplifier 43C and one end of the resistor 41C,
and is supplied with the signal SIGC. The positive input terminal of the amplifier 43C
is coupled to the negative input terminal of the amplifier 43B and the one end of the
resistor 41C, and is supplied with the signal SIGC. The negative input terminal of the
amplifier 43C is coupled to the positive input terminal of the amplifier 43A and the
resistor 41A, and is supplied with the signal SIGA.
[0064] This configuration allows the amplifier 43A to output a signal that is based
on a difference AB (SIGA-SIGB) between the signal S!GA and the signal S!GB, allows
the amplifier 43B to output a signal that is based on a difference BC (SIGB-SIGC)
between the signal SIGB and the signal SIGC, and allows the amplifier 43C to output a
signal that is based on a difference CA (SIGC-SIGA) between the signal SIGC and the
signal SIGA.
[0065] FIG. 14 illustrates an operation example of the amplifiers 43A, 43B, and
43C in a case where the receiver 40 receives a symbol "+x". It is to be noted that the
switches 42A, 42B, and 42C each are in the ON state, and thus the illustrations thereof
are omitted. In this example, the voltage stale of the signal SIGA is the voltage state
SH, the voltage state of the signal SIGB is the voltage slate SL, and the voltage state of
the signal SIGC is the voltage state SM. In this case, an electric current lin flows in
the input tem1inal TinA, the resistor 41A, the resistor 41B, and the input terminal TinB
io this order. Further, a voltage corresponding to the voltage state SH is supplied to the
26
SP366204
positive input terminal of the amplifier 43A, and a voltage .. corresponding to the voltage
state SL is supplied to the negative input terminal of the amplifier 4 3A, thereby the
di±TerenceAB.becomes positive (AB > 0). Therefore, the amplifierJ2A outputs "I".
Further, a voltage corresponding to the voltage state SL is supplied to the positive input
terminal of the amplifier 43B, and a voltage corresponding to the voltage state SM is
supplied to the negative input terminal of the amplifier 43B, thereby the difference BC
becomes negative (BC < 0). Therefore, the amplifier 43B output "0". Fmihcr, a
voltage corresponding to the voltage state SM is supplied to the positive input tenninal
of the amplifier 43C, and a voltage corresponding to the voltage stale SH is supplied to
the negative input terminal of the amplifier 43C, thereby the difference CA becomes
negative (CA < 0). Therefore, the amplifier 43C outputs "0".
[0066] The clock generator 44 generates the clock signal RxCK on the basis of the
output signal from each of the amplifiers 43A, 43B, and 43C.
[0067] The flip-flop 45 delays the output signal from each of the amplifiers 43A,
43B, and 43C by one clock period behind the clock signal RxCK, and outputs each
delayed output signal. The flip- flop 46 delays each of the three output signals from the
flip-flop 45 by one clock period behind the clock signal RxCK, and outputs each
delayed output signal.
[0068] The signal generator 4 7 generates the transition signals RxF, RxR, and RxP
on the basis of the output signal from each of the flip-flops 45 and 46 and the clock
signal RxCK. The transition signals RxF, RxR, and RxP respectively correspond to
the transition signals TxF9, TxR9, and TxP9 in the transmission device 10 (FIG. 5), and
each represent the transition of the symboL The signal generator 4 7 identifies the
27
SP36620~
transition of the symbol (FIG. 4) on the basis of the symbol indicated by the output
signal from the flip-flop 45 and the symbol indicated by the output signal from the
Hip-flop 46, and generates the transition signals RxF,· RxR, and RxP.
[0069] The processor 32 (FIG. 1) performs predetermined processing on the basis of
the transition signals RxF, RxR, and RxP and the clock signal RxCK.
[0070] Here, the driver sections 29A, 29B, and 29C each conespond to a specific
example of "driver section" in the disclosure. The signals SIGA, SIGB, and SIGC
each correspond to a specific example of "data signal" in the disclosure. The driver
controllers 27N and 27D and the emphasis controllers 28A, 28B, and 20C each
correspond to a specific example of "control section" in the disclosure. The
transmission symbol generator 22 conesponds to a specific example of "signal
generation section" in the disclosure. Each of the circuits UA01 to UAOM, UB01 to
UBON, UA1 1 to UA!M, and UB1 1 to UBIN corresponds to a specific example of "first
sub-circuit" in the disclosure. Each of the circuits DA01 to DAOM, DB01 to DBON,
DA1 1 to DAh,1, and DBI 1 to DB!N concsponds to a specific example of "second
sub-circuit" in the disclosure.
[Workings and Effects]
[0071] Next, workings and effects of the commtmication system I according to the
present embodiment are described.
(Overview of Overall Operation)
[0072] First, an overview of an overall operation of the communication system 1 is
described with reference to FIGs. 1, 5, and 7. The clock generator 11 in the
transmission device 10 generates the clock signal TxCK. The processor 12 performs
28
SP366204
the predetermined processing to thereby generate the transition signals TxFO to TxF6,
TxRO to TxR6, and TxPO to TxP6. In the transmitter 20 (FIG.S), the serializer 21 F
generales the transition signal TxF9 on the basis of the transition signals TxFO to TxF6
and the clock signal TxCK. The serializer 21R generales the transition signal TxR9 on
the basis of the transition signals TxRO to TxR6 and the clock signal TxCK. The
serializer 21 P generates the transition signal TxP9 on the basis of the transition signals
TxPO to TxP6 and the clock signal TxCK. The transmission symbol generator 22
generates the symbol signals Tx1, Tx2, and Tx3 relating to the current symbol NS and
the symbol signals D 1, D2, and D3 relating to the symbol DS that is earlier by one
symbol, on the basis of the transition signals TxF9, TxR9, and TxP9 and the clock
signal TxCK.
[0073] In the output section 26 (FIG. 7), the driver controller 27N generates the
signals MAINAN, SUBAN, MAINBN, SUBBN, MAINCN, and SUBCN on the basis
of the symbol signals Txl, Tx2, and Tx3 relating to the ctment symbol NS and the
clock signal TxCK. The driver controller 27D generates the signals MAINAD,
SUBAD, MAINBD, SUBBD, MAINCD, and SUBCD on the basis of the symbol
signals D 1, D2, and D3 relating to the symbol DS that is earlier by one symbol, and the
clock signal TxCK. The emphasis controller 28A generates the signals UPAAO,
UPABO, UPAA!, UPAB!, DNAAO, DNABO, DNAA!, and DNAB! on the basis of the
signals MAINAN, SUBAN, MAINAD, and SUBAD. The emphasis controller 28B
generales the signals UPBAO, UPBBO, UPBAl, UPBB1, DNBAO, DNBBO, DNBAl,
and DNBBl on the basis of the signals MAINBN, SUBBN, MAINBD, and SUBBD.
The emphasis controller 28C generates the signals UPCAO, UPCBO, UPCAl, UPCBI,
29
SP366204
DNCAO, DNCBO, DNCAI, and DNCB I on the basis of the signals MAINCN, SUBCN,
MAINCD, and SUBCD. The driver section 29A generates the signal SIGA on the
basis ofthe signals UPAAO, UPABO, UPAAl, UPABl, DNAAO, DNABO, DNAAI, and
DNAB I. The driver section 29B generates the signal S!GB on the basis of the signals
UPBAO, UPBBO, UPBAl, UPBBl, DNBAO, DNBBO, DNBAl, and DNBBl. The
driver section 29C generates the signal SIGC on the basis of the signals UPCAO,
UPCBO, UPCAl, UPCBI, DNCAO, DNCBO, DNCAl, and DNCBl.
[0074] In the reception device 30 (FIG 1), the receiver 40 receives the signals
SIGA, SIGB, and SIGC, and generates the transition signals RxF, RxR, and RxP and the
clock signal RxCK on the basis of the signals S!GA, S!GB, and SIGC. The processor
32 performs the predetermined processing on the basis of the transition signals RxF,
RxR, and RxP and the clock signal RxCK.
(Detailed Operation)
[0075] Next, description IS g1ven m detail of an operation of the transmission
device 10. In transmission device I 0, the output section 26 sets a voltage state in each
of the output terminals ToutA, ToutB, and ToutC on the basis of the current symbol NS,
and sets voltage levels in each of the voltage states on the basis of the current symbol
NS and the symbol DS that is earlier by one symbol.
[0076] FIG !SA illustrates a voltage change of the signal SIGA in a case where the
voltage stale of the signal SIGA makes a transition from the voltage state SH to another
voltage state. It is to be noted that the same applies to the signals SIGB and S!GC.
In FIG. !SA, lUI (Unit Interval) is a period of transmitting one symbol. Further, 11 Vis
a difference between the high level voltage VHO and the intermediate level voltage
30
SP366204
VMO, and similarly, a difference between the intermediate level voltage VMO and the
low level voltage VLO. The high level voltage Vl-10, the intem1ediate level voltage
VMO, and the low level voltage VLO each are a voltage as a basis for a de-emphasis
operation.
[0077] In a case where the voltage state of the signal SIGA makes a transition from
the voltage state SH to the voltage stale SM. the voltage of the signal SlGA changes
from any ofthe three high level voltages VH (VHO, VHl, and VH2) to the intermediate
level voltage VMlminus. Specifically, in this case, the voltage state in the symbol DS
that is earlier by one symbol is the voltage state SH, and thus the signals MAINAD and
SUBAD are "1" and "0". The voltage state in the current symbol NS is the voltage
state SM, and thus the signals MA!NAN and SUBAN are, for example, "0" and "0".
Accordingly, as illustrated in FIG. 9, the driver section 29A sets the voltage of the signal
SlGA to the intermediate level voltage VMJ minus on the basis of the signal supplied
from the emphasis controller 28A. In other words, in this case, the transition amount
of the signal SIGA is about (-LI. V), and thus, the emphasis controller 28A sets the
voltage of the signal SIGA after the transition to the intem1ediate level voltage
VMlminus, which is lower by one step than the intermediate level voltage VMO as a
basis.
[0078] Further, in a case where the voltage state of the signal SIGA makes a
transition from the voltage state SH to the voltage state SL, the voltage of the signal
SIGA changes from any of the three high level voltages VH (Vl-10, VHI, and VH2) to
the low level voltage VL2. Specifically, in this case, the voltage state in the symbol
DS that is earlier by one symbol is the voltage state SH, and thus the signals MAIN AD
31
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and SUBAD are "1" and "0".. The voltage state in the current symbol NS is the voltage
state SL, and thus the signals MAIN AN and SUBAN are "0" and "1 ". Accordingly, as
illustrated in FIG. 9, the driver section 29A sets the voltage of the signal SIGA to the
low level voltage VL2 on the basis of the signal supplied from the emphasis controller
28A. In other words, in this case, the transition amount of the signal SIGA is about
(-21\.V), and thus, the emphasis controller 28A sets the voltage of the signal SIGA after
the transition to the low level voltage VL2, which is lower by two steps than the low
level voltage VLO as a basis.
[0079] It is to be noted that, in a case where the voltage state of the signal SIGA is
maintained in the voltage state SH, the voltage of the signal SIGA changes from any of
the three high level voltages VH (VHO, VHl, and VI-12) to the high level voltage VHO.
Specifically, in this case, the voltage state in the symbol DS that is earlier by one
symbol is the voltage state SH, and thus the signals MAIN AD and SUB AD are "1" and
"0". The voltage state in the cmTent symbol NS is the voltage state SH, and thus the
signals MAINAN and SUBAN arc "1" and "0". Accordingly, as illustrated in FIG. 9,
the driver section 29A sets the voltage of the signal SIGA to the high level voltage VHO
on the basis of the signal supplied from the emphasis controller 28A. In this way, in a
case where the voltage state of the signal SIGA is maintained in the voltage state SH
over a plurality of unit intervals in the transmission device 10, the voltage of the signal
SIGA is set to the high level voltage VHO in the second and following unit intervals.
In other words, the high level voltage VHO is a de-emphasized voltage.
[0080] FIG. l5B illustrates a voltage change of the signal SIGA in a case where the
voltage state of the signal SIGA makes a transition 11-om the voltage stale SM to another
32
SP366204
voltage slate.
[0081] In a case where the voltage state of the signal SIGA makes a transition from
the voltage state SM to the voltage state SH, the voltage of the signal SIGA changes
from any of the three intermediate level voltages VM (VMO, VMl plus, and VMl minus)
to the high level voltage VHl. Specitlcally, in this case, the voltage state in the
symbol DS that is earlier by one symbol is the voltage state SM, and thus the signals
MAIN AD and SUBAD arc "0" and "0". The voltage state in the current symbol NS is
the voltage state SH, and thus the signals MAIN AN and SUB AN are "I" and "0".
Accordingly, as illustrated in FIG. 9, the driver section29A sets the voltage of the signal
SIGA to the high level voltage VHl on the basis of the signal supplied from the
emphasis controller 28A. In other words, in this case, the transition amount of the
signal SIGA is about (+LI.V), and thus the emphasis controller 28A sets the voltage of
the signal SlGA after the transition to the high level voltage VHI, which is higher by
one step than the high level voltage VHO as a basis.
[0082] Further, in a case where the voltage state of the signal SIGA makes a
transition from the voltage state SM to the voltage state SL, the voltage of the signal
SIGA changes from a11y of the three intermediate level voltages VM (VMO, VM I plus,
and VM!minus) to the low level voltage VLl. Specifically, in this case, the voltage
state in the symbol DS that is earlier by one symbol is the vollage state SM, and thus the
signals MAINAD and SUBAD are "0" and "0". The voltage state in the cunent
symbol NS is the voltage state SL, and thus the signals MAINAN and SUBAN are "0"
and "I". Accordingly, as illustrated in FIG. 9, the driver section 29A sets the voltage of
the signal SIGA to the low level voltage VLI on the basis of the signal supplied from
SP366204
the emphasis controller 28A. ln other words, in this case, the transition amount of the
signal S!GA is about (-11 V). and thus the emphasis controller 28A sets the voltage of the
signal S!GA afterthe transition to the low level voltage VLl, which is lower by one. step
than the low level voltage VLO as a basis.
(0083] It is to be noted that, in a case where the voltage state of the signal SIGA is
maintained in the voltage state SM, the voltage of the signal SlGA changes from any of
the three intermediate level voltages VM (VMO, VM I plus, and VMl minus) to the
intermediate level voltage VMO. Specifically, in this case, the voltage state in the
symbol DS that is earlier by one symbol is the voltage state SM, and thus the signals
MA!NAD and SUBAD are "0" and "0". The voltage state in the current symbol NS is
the voltage state SM, and thus the signals MAINAN and SUBAN are "0" and "0".
Accordingly, as illustrated in FIG. 9, the driver section 29A sets the voltage of the signal
SIGA to the intermediate level voltage VMO on the basis of the signal supplied from the
emphasis controller 28A. In this way, in a case where the voltage state of the signal
SIGA is maintained in the voltage state SM over a plurality of unit intervals in the
transmission device I 0, the voltage of the signal SIGA is set to the intermediate level
voltage VMO in the second and following unit intervals.
(0084] FIG. l5C illustrates a voltage change of the signal SIGA in a case where the
voltage state of the signal SIGA makes a transition from the voltage state SL to another
voltage state.
[0085] In a case where the voltage state of the signal SIGA makes a transition from
the voltage state SL to the voltage state SM, the voltage of the signal SIGA changes
from any of the three low level voltages VL (VLO, VL 1, and VL2) to the intermediate
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level voltage VM!plus. Specifically. in this case, the voltage state in the symbol DS
that is earlier by one symbol is the voltage state SL, and thus the signals MAIN AD and
SUBAD .are· "0" and. ''1 ". The voltage state in the current symbol·NS is the voltage
state SM, and thus the signals MAINAN and SUBAN are "0" and "0". Accordingly, as
illustrated in FIG. 9, the driver section 29A sets the voltage of the signal SIGA to the
intermediate level voltage VJ\111 plus on the basis of the signal supplied from the
emphasis controller 28A. In other words, in this case, the transition amount of the
signal SIGA is about (+ilV), and thus the emphasis controller 28A sets the voltage of
the signal SIGA after the transition to the intermediate voltage VMlplus, which is
higher by one step than the intermediate level voltage VMO as a basis.
[0086] Further, in a case where the voltage state of the signal SIGA makes a
transition from the voltage state SL to the voltage state SH, the voltage of the signal
SIGA changes from any of the three low level voltages VL (VLO, VLI, and VL2) to the
high level voltage VH2. Specifically, in this case, the voltage state in the symbol DS
that is earlier by one symbol is the voltage state SL, and thus the signals MAIN AD and
SUBAD are "0" and "1". The voltage state in the current symbol NS is the voltage
state SH, and thus the signals MAINAN and SUBAN are "1" and "0". Accordingly, as
illustrated in PIG. 9, the driver section 29A sets the voltage of the signal S1GA to the
high level voltage VI-!2 on the basis of the signal supplied from the emphasis controller
28A. In other words, in this case, the transition amount of the signal SIGA is about
( + 2/l V), and thus the emphasis controller 28A sets the voltage of the signal SIGA after
the transition to the high level voltage VI-!2, which is higher by two steps than the high
level voltage VHO as a basis.
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[0087] Tt is to be noted that, in a case where the voltage state of the signal SIGA is
maintained in the voltage state SL, the voltage of the signal SIGA changes from any of
the three low level voltages VL (VLO, VLL and VL2) to the low level voltage VLO.
Specifically, in this case, the voltage state in the symbol DS that is earlier by one
symbol is the voltage state SL, and thus the signals MAIN AD and SUBAD are "0" and
"1 ". The voltage state in the current symbol NS is the voltage state SL, and thus the
signals MAIN AN and SUBAN are "0" and "I". Accordingly, as illustrated in FIG. 9,
the driver section 29A sets the voltage of the signal SIGA to the low level voltage VLO
on the basis of the signal supplied from the emphasis controller 28A. In this way, in a
case where the voltage state of the signal SIGA is maintained in the voltage state SL
over a plurality of unit intervals in the transmission device 10, the voltage of the signal
SIGA is set to the low level voltage VLO in the second and following unit intervals. In
other words, the low level voltage VLO is a de-emphasized voltage.
[0088] In this way, the transmission device 10 sets the voltage after the transition in
accordance with the transition amount of the voltage as a result of the transition of the
voltage state in each of the signals SIGA, SIGB, and SIGC. Specifically, in a case
where the voltage state makes a transition to a higher state by one step, the transmission
device I 0 sets the voltage after the transition to a higher voltage by one step than the
voltage as a basis (for example, the intermediate level voltage VMO or the high level
voltage VHO). In other words, in this case, the transmission device 10 sets a positive
emphasis voltage of one step. Further, in a case where the voltage stale makes a
transition to a higher state by two steps, the transmission device I 0 sets the voltage after
the transition to a higher voltage by two steps than the voltage as a basis (for example,
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the high level voltage VHO). ln other words, in this case, the transmission device l 0
sets a positive emphasis voltage oftwo steps. Fnrthcr, in a case where the voltage stale
. makes aAransition to a lower slate by one step, the transmission device l 0 sets the
voltage after the transition to a lower voltage by one step than the voltage as a basis (for
example, the intc1mediate level voltage VMO or the low level voltage VLO). ln other
words, in this case, the transmission device 10 sets a negative emphasis voltage of one
step. Further, in a case where the voltage state makes a transition to a lower state by
two steps, the transmission device 10 sets the voltage to a lower voltage by two steps
than the voltage as a basis (for example, the low level voltage VLO). ln other words, in
this case, the transmission device 10 sets a negative emphasis voltage of two steps. In
this way, the transmission device !0 sets the emphasis voltage in accordance with the
transition amount of the voltage in such a manner that the emphasis voltage rs m
proportion to the transition amount, in each of the signals SIGA, SIGB, and SIGC.
[0089] FIGs. 16A to 16E each illustrate an operation example of the
communication system I in a case where the symbol makes a transition from "+x" to
any of the symbols other than "+x". PIG. 16A illustrates a case where the symbol
makes a transition from "+x" to "-x". FIG. l6B illustrates a case where the symbol
makes a transition from "+x" to "+y". FIG. 16C illustrates a case where the symbol
makes a transition from "+x" to "-y". FIG. 16D illustrates a case where the symbol
makes a transition from "+x" to "+z". FIG. 16E illustrates a case where the symbol
makes a transition from "+x" to "-z". In each of FIGs. 16A to 16E, (A) illustrates
waveforms of the signals SIGA, SIGB, and SIGC at the output terminals To utA, TnutB,
and ToutC, respectively, of the transmission device 10, and (B) illustrates waveforms of
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diiTerences AB, BC, and CAin the reception .device 30. Further. the solid lines each
illustrate a waveform at the time of performing a de-emphasis operation, and the broken
lines each illustrate a waveform at the time of not performing the de-emphasis operation.
Further, a voltage of the signal SIGA before the transition is any of the three high level
voltages VH. However, in the drawings, the voltage of the signal SIGA is set to the
high level voltage VHO for convenience of description. Similarly, the voltage of the
signal SIGB before the transition is set to the low level voltage VLO, and the voltage of
the signal SIGC before the transition is set to the intermediate level voltage VMO.
[0090) As illustrated in FIG. 16A(A ), in a case where the symbol makes a transition
from "+x" and "-x", the signal SIGA changes from the high level voltage VHO to the
low level voltage VL2. The signal SlGB changes from the low level voltage VLO to
the high level voltage VH2. The signal SIGC is maintained in the intermediate level
voltage VMO. In other words, the transition amount of the signal SIGA is about
(-26.V), and thus, the transmission device 10 sets the voltage of the signal SIGA to the
low level voltage VL2 that is lower by two steps than the low level voltage VLO as a
basis. Further, the transition amount of the signal SIGB is about ( + 26. V), and thus the
transmission device 10 sets the voltage of the signal SIGB to the high level voltage VH2
that is higher by two steps than the high level voltage VHO as a basis. At this time, as
illustrated in FIG. 16A(B), the transmission amount of the difference AB (S!GA-SIGB)
is about ( -46. V), and thus, the difference AB after the transition becomes lower by four
steps, as compared with the case of not perfonning the de-emphasis operation. Further,
the transition amount of the difference BC (SIGB-SIGC) is about ( +26. V), and thus, the
difference BC after the transition becomes higher by two steps, as compared with the
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case of not performing the de-emphasis operation. Further, the transition amount of
the difference CA (SIGC-SIGA) is about (+21'1 V), and thus, the difference CA after the
transition becomes higher by two steps, as compared with the case of not performing the
de-emphasis operation.
[0091] As illustrated in FIG 16B(A), in a case where the symbol makes a transition
from "+x" to "+y", the signal SIGA changes from the high level voltage VHO to the
intermediate level voltage VMlminus. The signal SIGB changes from the low level
voltage VLO to the high level voltage VI-!2. The signal SIGC changes from the
intem1ediatc level voltage VMO to the low level voltage VLl. In other words, the
transition amount of the signal SIGA is about (-L'I V), the transmission device 10 sets the
voltage of the signal SIGA to the intermediate level voltage VMlminus that is lower by
one step than the intermediate level voltage VMO as a basis. Further, the transition of
the signal S!GB is about ( + 2!1 V), the transmission device 10 sets the voltage of the
signal SIGB to the high level voltage VI-!2 that is higher by two steps than the high level
voltage VHO as a basis. Further, the transition amount of the signal SIGC is about
(-1'1 V), the transmission device 10 sets the voltage of the signal SIGC to the low level
voltage VLl that is lower by one step than the low level voltage VLO as a basis. At
this time, as illustrated in FIG 16B(B), the transition amount of the difference AB
(SIGA-SIGB) is about (-31'1 V), the difference AB aller the transition is lower by three
steps, as compared with the case of not performing the de-emphasis operation. Further,
the transition amount of the difference BC (SIGB-SIGC) is about (+3L1V), and thus, the
difference BC after the transition is higher by three steps, as compared with the case of
not perfom1ing the de-emphasis operation.
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[0092 J As illustrated in FIG. 16C(A), in a case where the symbol makes a transition
from "+x" to "-y", the signal STGA changes hom the high level voltage VHO to the
intermediate level voltage VMl minus. The signal SIGB is maintained in !he low level
voltage VLO. The signal SIGC changes from the intermediate level voltage VMO to
the high level voltage VHl. In other words, the transition amount of the signal STGA
is about ( -L'l V), and thus, the transmission device 10 sets the voltage of the signal SIGA
to the intermediate level voltage VMlminus that is lower by one step than the
intermediate level voltage VMO as a basis. Fmiher, the transition amount of the signal
SIGC is about (+L'lV), and tlms, the transmission device 10 sets the voltage of the signal
SIGC to the high level voltage VHJ that is higher by one step than the high level
voltage VHO as a basis. At tins lime, as illustrate in FIG l6C(B), the transition
amount of the difference AB (S!GA-SIGB) is about (-L'lV), and thus, the difference AB
after the transition becomes lower by one step, as compared with the case of not
performing the de-emphasis operation. Further, the transition amount of the difference
BC (SIGB-SIGC) is about (-LI.V), and thus, the difference BC after the transition
becomes lower by one step, as compared with the case of not performing the
de-emphasis operation. Further, the transition amount of the difference CA
(SIGC-STGA) is about ( + 2L'l V), the difference CA after the transition becomes higher by
two steps, as compared with the case of not performing the de-emphasis operation.
[0093] As illustrated in FIG. 16D(A), in a case where the symbol makes a transition
from "+x" to "+z", the signal SIGA changes from the high level voltage VHO to the low
level voltage VL2. The signal SIGB changes from the low level voltage VLO to the
intennediale level voltage VMI plus. The signal SIGC changes from the intem1ediate
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level voltage VMO to the high level voltage VHI. ln other words, the transition
amount of the signal SIGA is about ( -2L'i V), and thus, the transmission device IOscts
the voltage of the signal SIGA to the low level voltage VL2 that is lower by two steps
than the low level voltage VLO as a basis. Further, the transition amount of the signal
SIGB is about (+L'iV), and thus, the transmission device 10 sets the voltage of the signal
SJGB to the intermediate level voltage VMlplus that is higher by one step than the
intermediate level voltage VMO as a basis. Further, the transition amount of the signal
SIGC is about (+L'i V), and thus, the transmission device 10 sets the voltage of the signal
SIGC to the high level voltage VHl that is higher by one step than the high level
voltage VHO as a basis. At this time, as illustrated in FIG. 16D(B), the transition
amount of the difference AB (SIGA-SIGB) is about (-3AV), the difference AB after the
transition becomes lower by three steps, as compared with the case of not perfmming
the de-emphasis operation. Further, the transition amount of the difference CA
(SlGC-SIGA) is about (+3L'i V), the difference CA after the transition becomes higher by
three steps, as compared with the case of not performing the de-emphasis operation.
[0094] As illustrated in FIG. 16E(A), in a case where the symbol makes a transition
from "+x" to "-z", the signal SIGA is maintained in the high level voltage VHO. The
signal SIGB changes from the low level voltage VLO to the intermediate level voltage
VM1 plus. The signal SIGC changes from the intem1ediate level voltage VMO to the
low level voltage VLl. ln other words, the transition amount of the SIGB is about
(+L'i V), and thus, the transmission device 10 sets the voltage of the signal SIGB to the
intermediate level voltage VMlplus thai is higher by one step than the intermediate
level voltage VMO as a basis. Further, the transition amount of the signal SIGC is
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about (-6V), and thus, the transmission device 10 sets the voltage ofthe.signal SIGC to
the low level voltage VLI that is lower by one step than the low level voltage VLO as a
basis. At this time, as illustrated in FG. 16E(B), the transition amount ofthe"difference
AB (SIGA-SIGB) is about (-6 V), and thus, the difference AB after the transition
becomes lower by one step, as compared with the case of not performing the
de-emphasis operation. Further, the transition amount of the difference BC
(SIGB-SIGC) is about (+26V), and thus, the difference BC after the transition becomes
higher by two steps, as compared with the case of not performing the de-emphasis
operation. Further, the transition amount of the difference CA (SIGC-SIGA) is about
( -6 V), the difference CA after the transition becomes lower by one step, as compared
with the case of not performing the de-emphasis operation.
[0095] In this way, the emphasis voltage is set in accordance with the transition
amount of the voltage in each of the signals SIGA, SIGB, and SIGC, in the
communication system l. In other words, the transmission device I 0 performs the
de-emphasis operation to each of the signals SIGA, SIGB, and SIGC (a single end
signal). As a result, in the communication system I, it is possible to improve
waveform quality for each of the signals SlGA, SIGB, and SIGC, and thus, possible to
improve communication performance.
[0096] Further, in the communication system 1, by setting the emphasis voltage to
each of the signals SIGA, SIGB, and SIGC in this way, the emphasis voltage is also set,
in accordance with the transition amount of the voltage, to each of the differences AB,
BC, aud CA each as a differential signal. As a result, in the communication svstem 1. ~ .
it is possible to improve the waveform quality of each of the difierences AB, BC, and
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CA, and thus, possible to improve the communication performance.
[0097] fiGs. 17 A and 17B each illustrate an eye diagram of the difference AB
between the signal SIGA and the signal S!GB, the difference BC between the signal
SIGB and the signal SIGC, and the difference CA between signal SIGC and the signal
SIGA, in a case of having performed the de-emphasis operation. FIGs. 18A and 1 8B
each illustrate an eye diagram of the difference AB between the signal SIGA and the
signal SIGB, the difference BC between the signal SIGB and the signal SIGC, and the
difference CA between the signal SIGC and the signal SIGA, in a case of not
performing the de-emphasis operation. FIGs. 17 A and 18A each illustrate an eye
diagram at the output terminals To utA, ToutB, and ToutC of the transmission device 10
in a case where there is no transmission path 100. FIGs. 17B and l8B each illustrate
an eye diagram at the input terminals TinA, TinB, and TinC of the reception device 30
in a case where there is a transmission path 100. In the communication system 1, as
illustrated in FIGs. 17B and 18B, performing the de-emphasis operation makes it
possible to provide a wider eye opening, a result of which it is possible to improve the
communication performance.
(Comparative Example)
[0098] Next, description rs grven of effects of the present embodiment while
making a comparison with a comparative example. A communication system lR
according to the comparative example includes a transmission device 1 OR. The
transmission device lOR performs pre-emphasis operation. The transmission device
1 OR includes two driver sections 29RA that are coupled to the output terminal To utA,
two driver sections 29RB that are coupled to the output terminal ToutB, and two driver
43
-- -- ~-- -;-..----
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sections 29RC that are coupled to the output terminal ToutC The transmission device
1 OR, for example, allows the two driver sections 29RA to operate together to set the
output impedance to about 25 [Q], allows the two driver sections 29RB to operate
together to set the output impedance to about 25 [Q], and allows the two driver sections
29RC to operate together to set the output impedance to about 25 [Q]. The
transmission de\~ce I OR decreases the output impedance in this way to thereby perform
the pre-emphasis operation.
[0099] FIGs. 19A to 19E each illustrate an operation example of the
communication system lR in a case where a symbol makes a transition from "+x" to
any of the symbols other than "+x". For example, as illustrated in FIG. l9A, in a case
where the symbol makes a transition from "+x" to "-x", the signal S!GA changes from
the high level voltage VHO to the low level voltage VL through a lower voltage than the
low level voltage VLO . The signal SIGB changes from the low level voltage VLO to
the high level voltage VH through a higher voltage than the high level voltage VHO.
The signal SIGC maintains the intermediate level voltage VMO. At this time, in a
former-half period (for example, 0.5 UI) in the period in which the transmission device
1 OR outputs the symbol "-x", the two driver sections 29RA operate together to set the
output impedance to about 25 [f!], the two driver sections 29RB operate together to set
the output impedance to about 25 [Q], and the two driver sections 29RC operate
together to set the output impedance to about 25 [D]. The same applies to the other
symbol transitions illustrated in FIGs. 19B to 19E. It is to be noted that the length of
the former-half period is 0.5 UI; however, this is non-limiting. The length may
alternatively be longer than 0.5 Ul.
44
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[0 l 00] In this way, in tbe communication system lR according to the comparative
example, tbe output impedance is set to about 25 [0] to thereby perform the
pre-emphasis operation. This causes a period in which the outputimpcdance does not
match the characteristic impedance of the transmission path 100. This may possibly
cause the deterioration of waveform quality and thus the deterioration of
communication performance in the communication system I R. Further, in the
communication system I R, the output impedance becomes about 25 [OJ transiently at
the time of outputting the intermediate level voltage VMO, which causes the increase of
a direct electric cunent caused by Thevenin termination, a result of which power
consumption relating to the direct electric current increases. Further, the two driver
sections 29RA, the two driver sections 29RB, and the two driver sections 29RC are
provided in the communication system I R. This leads to the increase of circuit area.
[0101] In contrast, in the communication system l according to the present
embodiment, the number of the transistors 91 and 94 to be turned ON is changed to
thereby perfonn the de-emphasis operation, and thus, it is possible to maintain the
output impedance at about 50 [0]. As a result, the output impedance matches the
characteristic impedance of the transmission path l 00, which makes it possible to
improve waveform quality and thus communication perfom1ance. Fnrthcr, in the
communication system l, it is possible to suppress direct electric cunent caused by
Thevenin termination, as compared with the communication system 1 R according to the
comparative example, which makes it possible to reduce power consumption. Further,
in the communication system 1, the driver sections 29A, 298, and 29C are provided one
by one, which makes it possible to reduce circuit area, as compared with the
45
. -----· ~------- - - - - - - - ---;c-;·---- -
SP36620~
communication system l R according to the comparative example.
[Effects]
·: ·[Oi02 J .: As described above, in the present embodiment; the emphasis voltage is set
in each of the signals S!GA, SIGB, and SIGC, in accordance with the transition an1onnt
of the voltage. Therefore, it is possible to improve waveform quality for each of the
signals SIGA, S!GB, and SIGC, and thus, it is possible to improve communication
performance.
[0103] In the present embodiment, the number of the transistors 91 and 94 to be
turned ON is changed to thereby set the emphasis voltage while maintaining the output
impedance at about 50 [n]. This makes it possible to improve communication
performance and reduce power consumption.
[Modification Example 1]
[0104] In the above-described embodiment, the output section 26 generates the
signals SIGA, SIGB, and SIGC on the basis of the symbol signals Txl, Tx2, and Tx3,
the symbol signals Dl, D2, and D3, and the clock signal TxCK; however, this is
non-limiting. In the following, description is given in detail of a transmission device
I OA according to the present modification example.
[0105] FIG. 20 illustrates a configuration example of a transmitter 20A of a
transmission device 1 OA. The transmitter 20A includes a transmission symbol
generator 22A, and an output section 26A. The transmission symbol generator 22A
generates the symbol signals Txl, Tx2, and Tx3 on the basis of the transition signals
TxF9, TxR9, and TxP9 and the clock signal TxCK. The output section 26A generates
the signals SIGA, SIGB, and SlGC on the basis of the symbol signals Txl, Tx2, and
46
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Tx3 and the clock signal TxCK.
. [0106] flG. 21 illustrates a configuration example of the output section 26A. The
· output section 26A includes a driver controller 27N and flip flops 17 A, l7B, and 17C.
The driver controller 27N generates signals MAINAN, SUBAN, MAINBN, SUBBN,
MAINCN, and SUBCN on the basis of the symbol signals Txl, Tx2, and Tx3 relating to
the current symbol NS and the clock signal TxCK. The flip flop 17 A delays the
signals MAINAN and SUBAN by one clock period behind the clock signal TxCK, to
output them as the signals MAINAD and SUBAD, respectively. The flip flop l7B
delays the signals MAINBN and SUBBN by one clock period behind the clock signal
TxCK, to output them as the signals MAINBD and SUBBD, respectively. The flip
flop l7C delays the signals MAINCN and SUBCN by one clock period behind the
clock signal TxCK, to output them as the signals MAIN CD and SUBCD, respectively.
[0107] With such a configuration, it is still possible to achieve effects similarly to
the effects of the above-described embodiments.
[Modification Example 2]
[0108] In the above-described embodiment, the transmission device 10 performs
the de-emphasis operation; however, this is non-limiting. The transmission device I 0
may perform the pre-emphasis operation. FIG. 22 illustrates three voltage states SJ-1,
SM, and SL. The voltage state SH is a state that corresponds to tln·ec high level
voltages VI-! (VHO, VJ-11, and VJ-12). The voltage state SM is a state that corresponds
to three intermediate level voltages VM (VMO, VMlplus, and VM!minus). The
voltage state SL is a state that corresponds to three low level vollages VL (VLO, VLl,
and VL2). The high level voltage VJ-10 is a high level voltage in a case of not applying
47
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SP366204
pre-emphasis. The intermediate level vollage VMO is an intermediate level voltage in
a case of not applying pre-emphasis. The low level voltage VLO is a low level voltage
in a case of not applying pre-emphasis. With such a configuration, it is still possible to
achieve effects similarly to the effects of the above-described embodiments.
[Modification Example 3]
[0 l 09] In the above-described embodiment, the three voltage states SH, SM, and
SL are provided for each of the signals SIGA, SIGB, and SIGC; however. this is
non-limiting. It is possible to apply the techniques to a communication system that
transmits data by using three or more multiple voltage states.
[0110] FlG. 23 illustrates the n-number of voltage states S(l) to S(n) used in a
communication system according to the present modification example. The voltage
states S each correspond to the n-number of voltages. Specifically, for example, the
voltage state S(l) corresponds to the n-number of voltages V(l)0,V(1)1V(l)2, ... , and
V(l)n-l· The voltage state S(2) corresponds to the n-number of voltages V(2)cn-l)x 05
m;nus,· .. , V(2)1 m;nus, V(2)o, V(2)1 plus.···• and V(2)(n-l)x05 plus· The voltage state S(n-1)
corresponds to then-number of voltages V(n-l)cn-l)xos m;nus.···· V(n-!)1 .,;nus. V(n-l)o,
V(n-!)1 plus,···· and V(n-l)(n-l)xos ph.s· The voltage state S(n) conesponds to the
n-number of voltages V(n)0, V(n)J. V(n)2, ... , and V(n)n-l·
[0 111] Further, in the above-described embodiment, three signals SIGA, SIGB, and
SIGC are used to transmit data; however, this is non-limiting. Data may be transmitted
by using no greater than two signals or no less than four signals.
[Other Modification Examples]
[01121 Further, two or more of these modification examples may be combined.
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<2. Application Example>
[Oll3] Description is given next of application examples of the communication
systems that have been described in the foregoing embodiments and modification
examples.
(Application Example I)
[0114] FIG. 25 illustrates an appearance of a smartphone 300 (a multi-functional
mobile phone) to which the communication system according to any of the foregoing
embodiments, etc. is applied. Various devices are mounted in the smartphone 300.
The communication system according to any of the foregoing embodiments, etc. is
applied to a communication system that exchanges data between these devices.
[0115] FIG 24 illustrates a configuration example of an application processor 310
used in the smartphonc 300. The application processor 310 includes a CPU (central
processing unit) 311, a memory controller 312, a power supply controller 313, an
external interface 314, a GPU (graphics processing unit) 315, a media processor 316, a
display controller 317, and an MlPI (mobile industry processor interface) interface 318.
In this example, the CPU 311, the memory controller 312, the power supply controller
313, the external interface 314, the GPU 315, the media processor 316, and the display
controller 317 are coupled to a system bus 319 to allow for mutual data exchange via
the system bus 319.
[Oil6] The CPU 311 processes vanous preces of infonnation handled in the
smartphone 300 in accordance with a program. The memory controller 312 controls a
memory 501 used at a time when the CPU 311 performs information processing. The
power supply controller 313 controls a power supply of the smartphone 300.
49
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[0117] The extemal interrace 314 is an interface for communication with external
devices. In this example, the external interface 314 is coupled to a wireless
communication section 502. and an image sensor 410. The wireless communication
section 502 performs wireless communication with mobile phone base stations. The
wireless communication section 502 includes, for example, a baseband section, an RF
(radio frequency) front end section, and other components. The image sensor 410
acquires an image, and includes, for example, a CMOS sensor.
[0 118] The GPU 315 performs image processing. The media processor 316
processes information snch as voice, letters, and graphics. The display controller 317
controls the display 504 via the MIP! interface 318. The M!Pl interface 318 transmits
an image signal to the display 504. As the image signal, for example, a YUV-format
signal, an RGB-format signal, or any other format signal may be used. The MIPI
interface 318 operates, on the basis of a reference clock supplied from an oscillator
circuit 330 including a crystal resonator, for example. For example, the
communication system according to any of the foregoing embodiments, etc. is applied
to a communication system between the MIPI interface 318 and the display 504.
[0 119] FIG. 26 illustrates a configuration example of the image sensor 410. The
image sensor 410 includes a sensor section 411, an ISP (image signal processor) 412, a
JPEG (joint photographic experts group) encoder 413, a CPU 414, a RAM (random
access memory) 415, a ROM (read only memory) 416, a power supply controller 417,
an Pc (inter-integrated circuit) interface 418, and an MIPI interface 419. In this
example, these blocks arc coupled to a system bus 420 to allow for mutual data
exchange via the system bus 420.
50
-- - -- --------,-,-----
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[ 0 120] The sensor section 411 acquires an image, and is configured by, for example,
a CMOS sensor. The ISP 412 performs predetermined processing on the rmage
acquired by the sensor section 411. The JPEG encoder 413 encodes the 1mage
processed by the ISP 412 to generate a .!PEG-format image. The CPU 414 controls
respective blocks of the image sensor 410 in accordance with a program. The RAM
415 is a memory used at a time when the CPU 414 perfonm information processing.
The ROM 416 stores a program to be executed in the CPU 414, a setting value obtained
by calibration, and any other information. The power supply controller 417 controls a
power supply of the image sensor 410. The !2C interface 418 receives a control signal
from the application processor 310. Although not illustrated, the image sensor 410
also receives a clock signal from the application processor 310, in addition to the
control signal. Specifically, the image sensor 410 is operable on the basis of clock
signals of various frequencies. The MIPI interface 419 transmits an image signal to
the application processor 310. As the image signal, for example, a YUV-format signal,
an ROB-format signal, or any other format signal may be used. The MIPI interface
419 operates on the basis of a reference clock supplied from an oscillator circuit 430
including a crystal resonator, for example. For example, the communication system
according to any of the foregoing embodiments, etc. is applied to a communication
system between the MIPI interface 419 and the application processor 310.
(Application Example 2)
[0 121 J FIG. 27 illustrates a configuration example of a vehicle control system 600
to which the communication system according to any of the foregoing embodiments, etc.
is applied. The vehicle control system 600 controls operations of an automobile, an
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electric vehicle, a hybrid electric vehicle, a two-wheeled vehicle, and the like. This
vehicle control system 600 includes a driving system control unit 610, a body system
control unit 620,·a battery_ control unit 630, an outside-vehicle information detecting
unit 640, an in-vehicle information detecting unit 650, and an integrated control unit
660. These units are coupled to one another via a communication network 690. As
the communication network 690, for example, a network that complies with any
standard such as a CAN (controller area network), LIN (local interconnect network),
LAN (local area network), and FlexRay (Registered Trademark) may be used. Each of
the units includes, for example, a microcomputer, a storage section, a drive circuit that
drives a device to be controlled, a communication I/F, and the like.
[Ol22J The driving system control unit 610 controls operations of devices related to
a driving system of a vehicle. A vehicle state detecting section 611 is coupled to the
driving system control unit 610. The vehicle state detecting section 611 detects a state
of the vehicle. The vehicle state detecting section 611 includes a gyro sensor, an
acceleration sensor, a sensor that detects an amount of operation of an accelerator pedal
and a brake pedal or a steering angle, or any other sensor, for example. The driving
system control unit 610 controls the operations of the devices related to the driving
system of the vehicle on the basis of information detected by the vehicle state detecting
section 611. For example, the communication system of any of the foregoing
embodiments, etc. is applied to a communication system between the driving system
control unit 610 and the vehicle state detecting section 611.
[0123] The body system control unit 620 controls operations of various devices
mounted on the vehicle, such as a keyless entry system, a power window device, and
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various lamps.
[0 I 24] The battery control unit 630 controls a battery 631. The battery 631 is
coupled t6 the battery control unit 630. The battery 631 supplies power• to a driving
motor, and includes, for example, a secondary battery, a cooling system, and the like.
The battery control unit 630 acquires information such as temperature, an output voltage,
and a remaining battery amount from the battery 631, and controls the cooling system,
etc. of the battery 631 on the basis of the information. For example, the
communication system of any of the foregoing embodiments, etc. is applied to a
communication system between the battery control unit 630 and the battery 63 I.
l 0 125] The outside-vehicle infmmation detecting unit 640 detects information
outside the vehicle. An imaging section 641 and an outside-vehicle information
detecting section 642 are coupled to the outside-vehicle information detecting unit 640.
The imaging section 641 captures an image outside the vehicle, and includes, for
example, a time of flight (ToF) camera, a stereo camera, a monocular camera, an
infrared camera, and the like. The outside-vehicle infmmation detecting section 642
detects information outside the vehicle, and includes, for example, a sensor that detects
weather and climate, a sensor that detects other vehicles around the vehicle, an obstacle,
a pedestrian, etc., and any other sensor. The outside-vehicle infonnation detecting unit
640 recognizes, for example, weather and climate, a road surface condition, etc. on the
basis of the image acquired by the imaging section 641 as well as the information
detected by the outside-vehicle information detecting section 642, and detects objects
such as other vehicles around the vehicle, an obstacle, a pedestrian, a sign, and letters on
a road, or detects a distance between the object and the vehicle. For example, the
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communication system of any of the foregoing embodiments, etc. is applied to a
communication system between the outside-vehicle information detecting unit 640 and
each ofthe imaging section 641 and the outside-vehicle ·information detecting section
642.
[0126] The in-vehicle information detecting unit 650 detects information inside the
vehicle. A driver state detecting section 651 is coupled to the in-vehicle information
detecting unit 650. The driver state detecting section 651 detects a state of a driver,
and includes, for example, a camera, a biosensor, a microphone, and the like. The
in-vehicle information detecting unit 650 monitors, for example, a degree of fatigue of
the driver or a degree of concentration of the driver, whether the driver is dozing, and
any other factor, on the basis of information detected by the driver state detecting
section 651. For exan1plc, the communication system of any of the foregoing
embodiments, etc. is applied to a communication system between the in-vehicle
information detecting unit 650 and the driver state detecting section 651.
[0127] The integrated control unit 660 controls operations of the vehicle control
system 600. An operating section 661, a display section 662, and an instrument panel
663 are coupled to the integrated control unit 660. An occupant operates the operating
section 661. The operating section 661 includes, for example, a touch panel, various
buttons, switches, and the like. The display section 662 displays an image, and is
configured by, for example, a liquid crystal display panel, etc. The instrument panel
663 displays a state of the vehicle, and includes meters such as a speed meter, various
warning lamps, and the like. For example, the communication system of any of the
foregoing embodiments, etc. is applied to a communication system between the
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integrated control unit 660 and each of the operating section 661, the display section
662, and the instrument panel 663 0
Although the technology has been described above refening to
embodiments and modification examples as well as application examples to electronic
apparatuses, the tcclmology is not limited to these embodiments, etc., and may be
modified in a variety of ways"
l 0 129] For example, the voltage levels in each of the voltage states are set on the
basis of the cuncnt symbol NS and the symbol DS that is earlier by one symbol, in the
above-described embodiments, etc", this is non-limiting" Voltage levels of each of the
voltage states may alternatively be set on the basis of, for example, the current symbol
NS, the symbol DS that is earlier by one symbol, and a symbol that is earlier by two
symbols" In this case, the transmission device operates as a so-called 3-tap FIR filter
and performs the de-emphasis operation" It is to be noted that the technique is not
limited thereto, and voltage levels of each of the voltage states may be set on the basis
of four or more symbols including the current symbol NS"
[0130] It is to be noted that effects described herein are merely illustrative and are
not limitative, and may have other effects"
[0131]
[0132]
(1)
It is to be noted that the technology may have the following configurations"
A transmission device including:
a driver section that is able to transmit a dala signal by using tln"ee or more
predetermined number of voltage states and set voltages in each of the voltage states;
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and
a control section that sets an emphasis voltage that is based on a transition
among the predetem1ined number of the voltage statespand thereby causes the driver
section to perform emphasis.
(2)
The transmission device according to ( 1 ), in which
the predetermined number of the voltage states include a first voltage state, a
second voltage state, and a third voltage state that is between the first voltage state and
the second voltage state, and
the emphasis voltage in a case of making a transition from the first voltage
state to the second voltage state is greater than the emphasis voltage in a case of making
a transition from the first voltage state to the third voltage state.
(3)
The transmission device according to (2),
in which the driver section includes:
a first driver section that selectively sets a voltage state at a first output
terminal to any of the first voltage state, the second voltage state, and the third voltage
state;
a second chiver section that selectively sets a voltage state at a second output
terminal to any of the first voltage state, the second voltage state, and the third voltage
stale; and
a third driver section that selectively sets a voltage stale at a third output
terminal to any of the first voltage state, the second voltage state, and the third voltage
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state, and
m which the voltage states at the first output terminal, the second output
terminal, and the third output terminal differ from one another.
(4)
The transmission device according to (3 ), in which
the data signal indicates a sequence of a symbol, and
the control section sets, in accordance with the sequence of the symbol, the
emphasis voltage at each of the first output terminal, the second output terminal, and the
third output terminal.
(5)
The transmission device according to ( 4 ), further including:
a signal generation section that generates, on the basis of a transition signal
indicating symbol transition, a first symbol signal indicating a symbol, and a second
symbol signal indicating a symbol that is earlier by one symbol than the symbol
indicated by the first symbol signal,
in which the control section sets, on the basis of the first symbol signal and the
second symbol signal, the emphasis voltage at each of the first output terminal, the
second output terminal, and the third output terminal.
(6)
The transmission device according to (5), in which the first driver section, the
second driver section, and the third driver section respectively set, on the basis of the
first symbol signal, voltage states at the first output terminal, the second output terminal,
and the third output terminal.
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(7)
The transmission device according to ( 4 ), further including a signal generation
section that generates, on the basis of a transition signal indicating symbol transition, a
symbol signal indicating a symbol,
in which the control section sets, on the basis of a sequence of the symbol
indicated by the symbol signal, the emphasis voltage at each of the first output tem1inal,
the second output terminal, and the third output terminal.
(8)
The transmission device according to any one of (3) to (7), in which
the first driver section includes:
a first circuit that is provided on a path from a first power supply to the
first output terminal; and
a second circuit that is provided ou a path from a second power supply
to the first output terminal, and
the control section sets an impedance ratio of an impedance of the first circuit
to an impedance of the second circuit, and thereby sets the emphasis voltage at the first
output terminal.
(9)
The transmission device according to (8), in which the control section sets the
impedance ratio to cause a parallel impedance of the impedance of the first circuit and
the impedance of the second circuit to be constant.
(l 0)
The transmission device according to (8) or (9), in which
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the first circuit includes a plurality of first sub-circuits ach including a first
resistor and a first transistor that are provided on the path from the first power supply to
the first output terminal,
the second circuit includes a plurality of second sub-circuits each including a
second resistor and a second transistor that are provided on the path from the second
power supply to the first output terminal, and
the control section sets number of first transistors to be turned ON out of the
first transistors that are provided in the first circuit, and sets number of second
transistors to be turned ON out of the second transistors that are provided in the second
circuit, and thereby sets the emphasis voltage at the first output terminal.
(H)
The transmission device according to (1 0), in which
the plurality of first sub-circuits are grouped into a plurality of first groups,
the plurality of second sub-circuits are grouped into a plurality of second
groups, and
the control section causes the first transistors in the first circuit to turn ON and
OFF in a unit of the first group, and causes the second transistors in the second circuit to
turn ON and OFF in a unit of the second group, and thereby sets the emphasis voltage at
the first output terminal.
(12)
The transmission device according to (II), in which
the plurality of first groups include a first sub-group and a second sub-group,
and
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number of the first sub-circuits that belong to the f!rst sub-group dil1ers from
number of the first sub-circuits that belong to the second sub-group.
(13)
The transmission device according to any one of (1) to (12), in which the
voltages in each of the voltage states arc able to he set to have same number of voltages
as the predetermined number, the voltages differing from one another.
(14)
The transmission device according to any one of (I) to (13 ), m which the
emphasis includes de-emphasis.
(15)
The transmission device according to any one of (1) to (13 ), in which the
emphasis includes pre-emphasis.
(16)
A transmission method including:
transmitting a data signal by using three or more predetermined number of
voltage states; and
setting an emphasis voltage that is based on a transition among the
predetermined number of the voltage states, and thereby to perfonn emphasis.
(17)
A communication system provided with a transmission device and a reception
device, the transmission device including:
a driver section that is able to transmit a data signal by using three or more
predetermined number of voltage stales and set voltages in each of the voltage states;
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and
a control section that sets an emphasis voltage that is based on a transition
among the predetermined number of the voltage states, and thereby causes the driver
section to perform emphasis.
[0133] This application claims the benefit of Japanese Priority Patent Application
JP2016-031222 filed with the Japan Patent Office on February 22, 2016, the entire
contents of which are incorporated herein by reference.
[0134] It should be tmderstood by those skilled in the art that various modifications,
combinations, sub-combinations, and alterations may occur depending on design
requirements and other factors insofar as they are within the scope of the appended
claims or the equivalents thereof.

CLAIMS
[Claim 1]
A transmission device comprising:
a driver section that is able to transmit a data signal by using three or more
predetermined number of voltage states and set voltages in each of the voltage states:
and
a control section that sets an emphasis voltage that is based on a transition
among the predetermined number of the voltage states, and thereby causes the driver
section to perfonn emphasis.
[Claim 2]
The transmission device according to claim 1, wherein
the predetermined number of the voltage states include a first voltage state, a
second voltage state, and a third voltage state that is between the first voltage slate and
the second voltage state, and
the emphasis voltage in a case of making a transition from the first voltage
state to the second voltage state is greater than the emphasis voltage in a case of making
a transition from the first voltage state to the third voltage state.
[Claim 3]
The transmission device according to claim 2,
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wherein the driver section includes:
a first driver section that selectively sets a voltage state at a first output
terminal to any of the first voltage state, the second voltage state, and the third voltage
state;
a second driver section that selectively sets a voltage state at a second output
tenninal to any of the first voltage state, the second voltage state, and the third voltage
state; and
a third driver section that selectively sets a voltage state at a third output
terminal to any of the first voltage state, the second voltage state, and the third voltage
state, and
wherein the voltage states at the first output terminal, the second output
terminal, and the third output terminal differ from one another.
[Claim 4]
The transmission device according to claim 3, wherein
the data signal indicates a sequence of a symbol, and
the control section sets, in accordance with the sequence of the symbol, the
emphasis voltage at each of the first output terminal, the second output terminal, and the
third output terminal.
[Claim 5]
The transmission device according to claim 4, further comprising:
a signal generation section that generates, on a basis of a transition signal
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indicating symbol transition, a first symbol signal indicating a symbol, and a second
symbol signal indicating a symbol that is earlier by one symbol than the symbol
indicated by the first symbol signal,
wherein the control section sets, on a basis of the first symbol signal and the
second symbol signal, the emphasis voltage at each of the first output terminal, the
second output tenninal, and the third output terminal.
[Claim 6]
The transmission device according to claim 5, wherein the first driver section,
the second driver section, and the third driver section respectively set, on a basis of the
first symbol signal, voltage states at tbe first output terminal, the second output terminal,
and the third output terminaL
[Claim 7]
The transmission device according to claim 4, further compnsmg a signal
generation section that generates, on a basis of a transition signal indicating symbol
transition, a symbol signal indicating a symbol,
wherein the control section sets, on a basis of a sequence of the symbol
indicated by the symbol signal, the emphasis voltage at each of the first output terminal,
the second output terminal, and the third output tenninal.
[Claim 8]
The transmission device according to claim 3, wherein
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the first driver section includes:
a first circuit that is provided on a path ±rom a first power supply to the
first output terminal: and
a second circuit that is provided on a path from a second power supply
to the iirst output terminal, and
the control section sets an impedance ratio of an impedance of the Jirst circuit
to an impedance of the second circuit, and thereby sets tbe emphasis voltage at the first
output tem1inal.
[Claim 9]
The transmission device according to claim 8, wherein the control section sets
the impedance ratio to cause a parallel impedance of the impedance of the first circuit
and the impedance ofthe second circuit to be constant.
[Claim 10]
The transmission device according to claim 8, wherein
the first circuit includes a plurality of Jirst sub-circuits each including a first
resistor and a first transistor that are provided on the path from the first power supply to
the first output terminal,
the second circuit includes a plurality of second sub-circuits each including a
second resistor and a second transistor that are provided on the path irom the second
power supply to the first output terminal, and
the control section sets number of first transistors lo be turned ON oul of the
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first transistors that are provided in the first circuit, and sets number of second
transistors to be turned ON out of the second transistors that arc provided in the second
circuit, and thereby sets the emphasis voltage at the first output terminal.
[Claim 11]
The transmission device according to claim 10, wherein
the plurality of first sub-circuits are grouped into a plurality of first groups,
the plurality of second sub-circuits are grouped into a plurality of second
groups, and
the control section causes the first transistors in the tlrst circuit to turn ON and
OFF in a unit of the first group, and causes the second transistors in the second circuit to
turn ON and OFF in a unit of the second group, and thereby sets the emphasis voltage at
the first output terminal.
[Claim 12]
The transmission device according to claim 11, wherein
the plurality of first groups include a first sub-group and a second sub-group,
and
number of the first sub-circuits that belong lo the first sub-group differs !rom
number of the tlrst sub-circuits that belong to the second sub-group.
[Claim 13]
The transmission device according to claim 1, wherein the voltages in each of
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the voltage states are able to be set to have same number of voltages as the
predetermined number, the voltages differing from one another.
[Claim 14]
The transmission device according to claim I, wherein the emphasis comprises
de-emphasis.
[Claim 15]
The transmission device according to claim 1, wherein the emphasis comprises
pre-emphasis.
[Claim 16]
A transmission method comprising:
transmitting a data signal by using three or more predetermined number of
voltage states; and
setting an emphasis voltage that is based on a transition among the
predetermined number of the voltage states, and thereby performing emphasis.
[Claim 17]
A communication system provided with a transmission device and a reception
device, the transmission device comprising:
a driver section that is able to transmit a data signal by using three or more
predetermined number of voltage states and set voltages in each of the voltage slates;
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and
a control section that sets an emphasis voltage that is based on a trm1sition
among the predetermined number of the voltage states, and thereby causes the driver
section to perform emphasis.