BACKGROUND OF THE INVENTIt3N FIET.D OF THE INVENTION The present invention relates to -a-roce-ivor, a transmitter-receiver, and a cammuniuaLiou umLhud, and is suitably applied to, for example, a radio communication system such as a portable telephone system. DESCRIPTION OF THE RELATED ART In a radio communication system, including so-called cellular system, an area for providing communication services is divided into cells of prescribed sizes: in each of the cells a base station as a fixed radio station is located, and a portable telephone serving as a mobile radio station radio-communicates with the base station in the cell in which the telephone exists. Various systems are proposed for the communication systems between a portable telephone and a base station, and a typical one is a time division multiple connection system referred to as a time division multiple access (TDMA) system. As shown in Figs. 1A and IB, for example, in the TDMA system, a predetermined frequency channel is temporally partitioned into frames FO, Fl, etc. of a predetermined time width, each of the frames is divided into time slots TSO to TS3 of a predetermined time width, and a transmission signal is transmitted by using the frequency channel for the timing of the time slot TSO assigned to the local station. A system of plural communication (so-called multiplex communication) is realized by using the same frequency channel for the efficient use of frequencies. In the following description, the time slot TSO assigned for transmission is referred to as a transmission slot TX, and the data block (that is, information unit) to be transmitted by one transmission slot TX is referred to as a slot. A transmitter and a receiver of a radio communication system for performing transmission and reception by using the TDMA system are described below with reference to Figs. 2 and 3. The transmitter and the receiver, for example, as shown in Figs. 2 and 3 are mounted on a portable telephone and a base station of a portable telephone system, and used for the communication from the portable telephone to the base station (so-called up-link communication) and the communication from the base station to the portable telephone (so-called down-link communication). As shown in Fig. 2, a transmitter 1 comprises a convolution coding circuit 2, an interleaving buffer 3, a slotting circuit 4, a modulation circuit 5, a pilot-symbol addition circuit 6, a transmission circuit 7 and an antenna 8. First, an information bit series S1 serving as transmission data is inputted to the convolution coding circuit 2. The convolution coding circuit 2, which comprises shift registers of a predetermined number of stages and exclusive OR circuits, applies convolution-coding to the inputted information bit series S1, and outputs the resulting coded bit series S2 to the interleaving buffer 3. The interleaving buffer 3 stores the coded bit series S2 in its internal storage area successively. When the coded bit series S2 are stored in the entire storage area (that is, when a desired volume of coded bit series S2 is stored) , the buffer 3 re-sequences the order in the coded bit series S2 at random (the re-sequencing of the order is hereafter referred to as interleaving) and outputs coded bit series S3 obtained by interleaving the coded bit series S2 to the slotting circuit 4. In this connection, the interleaving buffer 3 has a storage capacity for a plurality of slots so that coded bit series is dispersed to a plurality of transmission slots TX. The slotting circuit 4 partitions the coded bit series S3 for every predetermined number of bits so as to assign the coded bit series S3 to the transmission slots TX and successively outputs coded bit groups S4 obtained by assigning the coded bit series S3 to the transmission slots TX to the modulation circuit 5. The modulation circuit 5 applies predetermined modulation (e.g. synchronous-detection-based modulation such as QPSK) to each of supplied coded bit groups S4 and outputs the resulting information symbol groups S5 to the pilot symbol addition circuit 6. As shown in Fig. 4, the pilot symbol addition circuit 6 adds pilot symbols P to the head position of each symbol group (that is, the head of information symbols I) of the information symbol groups S5 partitioned correspondingly to the transmission slots TX as headers and outputs the resulting transmission symbol groups S6 to the transmission circuit 7. In this connection, the pilot symbols P added in this case are symbols of patterns previously known to the receiver side, and the receiver side estimates transmission-line characteristics (e.g. the state of fading) in accordance with the pilot symbols P. The transmission circuit 7 applies filtering to the pilot-symbol -added transmission symbol groups S6 in sequence and applies digital-analog conversion to the resulting groups S6 to generate a transmission signal. Then, the transmission circuit 7 generates a transmission signal S7 of a predetermined frequency channel by applying frequency conversion to the transmission signal, amplifies the signal S7 up to predetermined power, and transmits the signal S7 via the antenna 8. Thus, the transmission signal S7 is transmitted from the transmitter 1 synchronously with the timing of the transmission slots TX. As shown in Fig. 3, a receiver 10 comprises an antenna 11, a reception circuit 12, a transmission line estimation circuit 13, a demodulation circuit 14, a slot connection circuit 15, a deinterleaving buffer 16, and a Viterbi decoding circuit 17. The receiver 10 receives the transmission signal S7 transmitted from the transmitter 1 via the antenna 11 and inputs the signal S7 to the reception circuit 12 as a reception signal Sll. The reception circuit 12 amplifies the input reception signal Sll and fetches a base band signal by applying frequency conversion to the reception signal Sll. Then, the circuit 12 applies filtering to the base band signal, obtains reception symbol groups S12 corresponding to the above transmission symbol groups S6 by applying analog-digital conversion to the base band signal, and outputs the groups S12 to the transmission line estimation circuit 13. The transmission line estimation circuit 13, which is a circuit for examining characteristics of a transmission line and performing equalization corresponding to the examination results, estimates characteristics of a transmission line by referring to the pilot symbols P in the reception symbol groups S13 and calculates inverse characteristics of the transmission line in accordance with the estimation result. Moreover, the transmission line estimation circuit 13 convolution-multiplies respective information symbol portions of the reception symbol groups S12 in a time domain by the values of the inverse characteristics of the transmission line by using an equivalent circuit comprising an equalizer so as to eliminate such influence as fading caused in the transmission line. According to this processing, the transmission line estimation circuit 13 restores the transmitted information symbol groups S5 and outputs them to the demodulation circuit 14 as the reception information symbol groups S13. The demodulation circuit 14 restores coded bit groups S14 corresponding to the coded bit groups S4 in the transmission side by applying predetermined demodulation to the reception information symbol groups S13 and outputs the groups S14 to the slot connection circuit 15. In this connection, each bit of the coded bit group S14 is not a binary signal having a value of 0 or 1 but a multi-valued signal due to noise components added in the transmission line. The slot connection circuit 15 is a circuit for connecting the coded bit groups S14 fragmentarily obtained in slots one another to make a continuous signal. The circuit 15 connects the coded bit groups S14 when they are accumulated up to the storage capacity of the deinterleaving buffer 16 at the rear stage and outputs the resulting coded bit series S15 to the deinterleaving buffer 16. The deinterleaving buffer 16, which has a storage capacity for a plurality of slots, successively stores the supplied coded bit series S15 in its internal storage area, restores the order of the coded bit series S15 to the original order by performing the backward process of the re-sequencing performed in the interleaving buffer 3 of the transmitter 1, and outputs the resulting coded bit series S16 to the Viterbi decoding circuit 17 (hereinafter, the restoring to the original order is referred to as deinterleaving). The Viterbi decoding circuit 17, which comprises a soft decision Viterbi decoding circuit, determines a possible trellis of the convolution code in use based on the input coded bit series S16, estimates a maximum-likelihood state (so-called maximum-likelihood series estimation) out of all state transitions which can be used as data to restore and output transmitted information bit series S18. In the conventional receiver 10, sent symbols are temporally arranged within each slot. Therefore, influences caused in a transmission line are eliminated by performing convolution multiplication in a time domain by an equivalent circuit comprising an equalizer, resulting in highly complicated structures of the receivers. Moreover, in the aforesaid TDMA system, the communication quality may vary depending on the timing of a transmission slot TX. In the conventional receiver 10, the reliability, which shows the communication quality of a transmission slot TX, is not reflected on any coded bits sent via the slot. Therefore, there are problems that maximum-likelihood series estimation by the Viterbi decoding circuit 17 cannot be accurately performed, and transmitted information bit series cannot be accurately restored. SUMMARY OF THE INVENTION In view of the foregoing, an object of the present invention is to provide a receiver, a transmitter-receiver, and a communication method in which transmitted information bit series are restored accurately with a simple structure by performing maximum-likelihood series estimation with a high degree of accuracy. The nature, principle and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by like reference numerals or characters. Accordingly, the present invention relates to a receiver comprising receiving means for receiving a transmission signal and outputting reception symbol groups, wherein the transmission signal has been generated by partitioning a coded bit series obtained by coding an information bit series for each prescribed information unit to generate coded bit groups,/applying prescribed modulation to each of said coded bit groups to generate/information symbol groups, inserting pilot symbols of known amplitude and phases into each of said information symbol groups to generate transmission symbol groups, and dispersedly superimposing respective symbols of said transmission symbol groups on a plurality of subcarriers which/form a frequency channel, (pi-\ transmission line estimation means for extracting said pilot symbols from each of said reception symbol groups and estimating characteristics of the transmission line for each symbol in accordance with the amplitude and phases of said pilot symbols, weighting means for extracting said information symbol groups from said reception symbol groups, calculating weighting factors showing the reliability of the transmission line for respective symbols in accordance with the estimation result of said transmission line estimation means and said reception symbol groups, and multiplying respective symbols of said extracted inforrmation symbol groups by said weighting factors to reflect the reliability of said transmission line on the respective symbols, demodulation means for restoring said coded bit groups by applying prescribed demodulation to said information symbol groups on which reliability of said transmission line obtained by said weighting means is reflected and decoding means for applying maximum-likelihood series_estimation to each of said coded bit groups obtained by said demedulation means to restore said information bit series. Accordingly, the present invention also relates to a transmitter-receiver comprising transmission means for partitioning a coded bit series obtained by coding an information bit series for each prescribed information unit to generate coded bit groups, applying prescribed modulation to each of said coded bit groups to generate information symbol groups, inserting pilot symbols of known amplitude and phases into each of said information symbol groups to generate transmission symbol groups, dispersedly superimposing the symbols of said transmission symbol groups on a plurality of subcarriers which form a frequency channel to generate a transmission signal, and transmitting said transmission signal to the communication counterpart, reception means for receiving said transmission signal from the communication and outputting reception symbol groups, transmission line estimation means for extracting said pilot symbols from each of said reception symbol groups and estimating the characteristics of the transmission line for each symbol in accordance with the amplitude and phases of said pilot symbols, weighting means for extracting said information symbol groups from said reception symbol groups, calculating weighting factors showing the reliability of the transmission line for respective symbols in accordance with the estimation result of said transmission line estimation means and said reception symbol groups, multiplying respective symbols of said extracted information symbol groups by said weighting factors to reflect the reliability of said transmission line on the respective symbols, demodulation means for applying prescribed demodulation to said information symbol groups on which the reliability of said transmission line obtained by said weighting means is reflected to restore said coded bit groups and decoding means for applying maximum-likelihood series estimation to each of said coded bit groups obtained by said demodulation means to restore said information bit seres.Accordingly the present invention also method comprising the steps of partitioning a coded bit series obtained by coding an information bit series for each prescribed information unit to generating coded bit groups, applying prescribed modulation to each of said coded bit groups to generate information symbol groups, inserting pilot symbols of known amplitude and phases into each of said information symbol groups to generate transmission symbol groups, dispersedly superimposing respective symbols of said transmission symbol groups on a plurality of subcarriers which form a frequency channel to generate a transmission signal, and transmitting said transmission signal to the communication counterpart and in the reception side, receiving a transmission signal from the communication counterpart to obtain reception symbol groups, estimating the characteristics of he transmission line for each symbol in accordance with the amplitude and phases of said pilot symbols extracted from said reception symbol groups, calculating weighting factors showing the reliability of the transmission line for respective symbols in accordance with said estimation result and said reception symbol groups, multiplying respective symbols of said information symbol groups extracted from said reception symbol groups by the weighting factors to reflect the reliability of the transmission line on the respective symbols, applying prescribed demodulation to said information symbol groups on which the reliabilty of said transmission line is reflected to restore said coded bit groups, and applying maximum-likelihood series estimation to each of said coded bit groups to restore said information bit series. BRIEF DESCRIPTION OF THE EMBODIMENT In the accompanying drawings: Figs. 1A and 1B are schematic diagrams for explaining the theory of TDMA system; Fig. 2 is a block diagram showing the structure of a conventional transmitter; Fig. 3 is a block diagram showing the structure of a conventional receiver; Fig. 4 is a schematic diagram showing the arrangement of conventional pilot symbols; Fig. 5 is a block diagram showing the structure of the radio communication system of an embodiment of the present invention; Fig. 6 is a block diagram showing the structure of a transmitter of the radio communication system in Fig. 5; Fig. 7 is a signal point arrangement diagram for explaining the theory of QPSK modulation; Fig. 8 is a signal point arrangement diagram for explaining the theory of 8PSK modulation; Fig. 9 is a signal point arrangement diagram for explaining the theory of 16QAM modulation; Fig. 10 is a signal point arrangement diagram for explaining the theory of 64QAM modulation; Fig. 11 is a schematic diagram for explaining the arrangement of pilot symbols; Fig. 12 is a schematic diagram for explaining a transmission symbol after inverse Fourier transform; Fig. 13 is a block diagram showing the structure of a receiver of the radio communication system in Fig. 5; Fig. 14 is a block diagram showing the structure of a transmission line estimation circuit; Fig. 15 is a schematic diagram for explaining the theory of a multiplier 51 in a transmission line estimation circuit; Fig. 16 is a schematic diagram for explaining a symbol series S40 in a transmission line estimation circuit; Fig. 17 is a schematic diagram for explaining a method for generating a reference symbol series in a transmission line estimation circuit; Fig. 18 is a schematic diagram for explaining a method for generating a reference symbol series in a transmission line estimation circuit; Fig. 19 is a schematic diagram for explaining a method for generating a reference symbol series in a transmission line estimation circuit; Fig. 20 is a block diagram showing the structure of a weighting circuit; Fig. 21 is a block diagram showing the structure of a demodulation circuit corresponding to QPSK modulation; Fig. 22 is a block diagram showing the structure of a demodulation circuit corresponding to 8PSK modulation; Fig. 23 is a block diagram showing the structure of a demodulation circuit corresponding to 16QAM modulation; and Fig. 24 is a block diagram showing the structure of a demodulation circuit corresponding to 64QAM modulation. DETAILED DESCRIPTION OF THE EMBODIMENT Preferred embodiments of the present invention will be described with reference to the accompanying drawings: (1) General Structure of Radio Communication System In Fig. 5, symbol 20 denotes a radio communication system, for example, such as a portable telephone system to which the present invention is applied as a whole. The system is constituted with a base station system 21 set in each cell formed by dividing an area for providing communication services and a portable telephone 22 serving as a mobile station for communicating with the base station system 21. The base station system 21 comprises a transmitter 23 for transmitting information bit series to the portable telephone 22 by using a predetermined frequency channel, a receiver 24 for receiving information bit series transmitted from the portable telephone 22 by using a predetermined frequency channel, and a controller 25 for controlling operations of the transmitter 23 and receiver 24. Similarly, the portable telephone 22 comprises a transmitter 26 for transmitting information bit series to the base station system 21 by using a predetermined frequency channel, a receiver 27 for receiving the information bit series transmitted from the base station system 21 by using a predetermined frequency channel, and a controller 28 for controlling operations of the transmitter 26 and receiver 27. In the radio communication system 20, a plurality of frequency channels are provided for the communication between the base station system 21 and the portable telephone 22, and an arbitrary pair of frequency channels out of the frequency channels are used for the communication from the base station system 21 to the portable telephone 22 and/or the communication from the portable telephone 22 to the base station system 21. In this case, each frequency channel consists of, for example, 24 subcarriers so as to perform so-called multicarrier communication by dispersedly superimposing information bit series to be transmitted on the subcarriers for communication. In the radio communication system 20, information bit series to be transmitted is partitioned into slots and the resulting series in a slot is dispersedly superimposed on the above subcarriers. Moreover, in the radio communication system 20, frequency channels used for respective slots are changed at random in accordance with a prescribed pattern. This changing of frequency channels (so-called frequency hopping) reduces the influence of interference waves from other communication. The transmitters 23, 26, and the receivers 24, 27 mounted on the base station system 21, and the portable telephone 22 will be described in detail, thereinafter. Since the transmitters 23, 26 have the same structure and the receivers 24, 27 have the same structure, only the transmitter 23 and the receiver 27 are described below. (2) Structure of Transmitter Firstly, the structure of the transmitter 23 is described. As shown in Fig. 6, in which a portion corresponding to that in Fig. 2 is provided with the same reference numeral, the transmitter 23 comprises a convolution coding circuit 2, an interleaving buffer 3, a slotting circuit 4, a modulation circuit 5, a pilot symbol addition circuit 31, an inverse fast Fourier transform circuit (IFFT) 32, a transmission circuit 33, and an antenna 8. The transmitter 23 has almost the same structure as the transmitter 1 shown in Fig. 2 except that the inverse fast Fourier transform circuit 32 is added and the processing in the pilot symbol addition circuit 31 and the transmission circuit 33 is changed. In the transmitter 23, coded bit groups S4 partitioned by the slotting circuit 4 are input to the modulation circuit 5. The circuit 5 applies synchronous-detection-based modulation to the input coded bit groups S4. Various modulation methods are applicable to the above modulation, including quadrature phase shift keying modulation (QPSK, or so-called four-phase modulation) , 8 phase shift keying modulation (8PSK, or so-called eight-phase modulation), 16 quadrature amplitude modulation (16QAM, or so-called 16-valued quadrature amplitude modulation), and 64 quadrature amplitude modulation (64QAM, or so-called 64-valued quadrature amplitude modulation). The above referenced modulation methods will be briefly described below. As literally represented, the QPSK modulation is a phase modulation method of four phase states, as shown in Fig. 7, wherein two-bit information is represented by four types of signal points (symbols) at the phase values of π/4, 3π/4, 5 π /4, or 7 π /4 As shown in Fig. 8, the 8PSK modulation is a phase modulation method of eight phase states, wherein three-bit information is represented by eight types of signal points, whose phase values are separate from each other by π/4 on a concentric circle having an amplitude of 1. As shown in Fig. 9, the 16QAM modulation is a modulation method of 16 types of signal points in different amplitudes, wherein four-bit information is represented by 16 types of signal points generated by dividing each of the magnitudes of components I and Q by threshold value of ± √2/5 . As shown in Fig. 10, the 64QAM modulation is a modulation method of 64 types of signal points in different amplitudes, wherein six-bit information is represented by 64 types of signal points generated by dividing each of the magnitudes of components I and Q by threshold values of ± √2 / 21 , ± 2 x √2 / 21 , and ± 3 x √2 / 21 . In Figs. 7 to 10, each of numerical values accompanying to the signal points is the bit information represented by the point. The modulation circuit 5 applies one of these modulations to the coded bit groups S4 and outputs the resulting information symbol groups S5 to the following pilot symbol addition circuit 31. The pilot symbol addition circuit 31 is a circuit for adding pilot symbols P to each of the information symbol groups S5. In the transmitter 23, respective pilot symbols P are not added to the head portion of a symbol group, but inserted between information symbols I constituting a symbol group at equal intervals as shown in Fig. 11. In this connection, since symbols in a slot are dispersed on 24 subcarriers as described above, one slot has 24 symbols consisting of pilot symbols P and information symbols I. A pilot symbol P is a symbol of patterns known at the receiver side: its amplitude value is 1 and phase value is set at random. However, the phase value is set to differ from other communication system so that a transmission line is properly estimated. This is because the transmission line estimation at the receiver side is based on pilot symbols P: if the same pilot symbol P is used in other communication system, the transmission line for other communication system should be estimated. Transmission symbol groups S20 generated by adding the pilot symbols P are output to the following inverse fast Fourier transform circuit 32. The circuit 32 applies inverse Fourier transform to each of the transmission symbol groups S20 so as to dispersedly-superimpose the respective symbols in each of the groups on the aforesaid 24 subcarriers (that is, so as to arrange the symbols on a frequency axis for transmitting). Thus, a signal arranged on a frequency axis is generated from inputted symbol groups arranged on a time axis. Fig. 12 shows the state of a transmission symbol group S21 generated by applying inverse Fourier transform to the group S20, based on the frequency. Fig. 12 shows that 24 symbols consisting of pilot symbols P and information symbols I are arranged on a frequency axis and the 24 symbols are assigned to of 24 subcarriers respectively by applying inverse Fourier transform to the group S21. Moreover, the inverse fast Fourier transform circuit 32 applies so-called windowing to the transmission symbol group S21 generated by applying inverse Fourier transform to the group S21 so as to control unnecessary out-of-band spurious. Specifically, the windowing is realized by applying a cosine roll-off filter to the transmission symbol groups S21 on a time base. Then, the transmission symbol groups S21 generated through the processing via the inverse fast Fourier transform circuit 32 are output to the following transmission circuit 33. The transmission circuit 33 applies filtering to the transmission symbol groups S21 and thereafter, applies digital-to-analog conversion to the transmission symbol groups S21 to generate a transmission signal. Then, the transmission circuit 33 generates a transmission signal S22 of a prescribed frequency channel by applying frequency conversion to the former transmission signal, amplifies the signal S22 up to predetermined power, and transmits the signal S22 via the antenna 8. Moreover, the transmission circuit 33 changes frequency channels used for each slot at random in accordance with a prescribed pattern, thereby reducing the influence of interference waves received from other communication. Thus, the transmitter 23 performs multicarrier communication for transmitting information bit series to be transmitted via a plurality of subcarriers by dispersedly superimposing coded bit groups which are partitioned in slots on the subcarriers. (3) Structure of Receiver As shown in Fig. 13, in which a portion corresponding to that in Fig. 3 is provided with the same reference numeral, the receiver 27 comprises an antenna 11, a reception circuit 40, a fast Fourier transform circuit (FFT) 41, a demodulation section 42, a slot connection circuit 15, a deinterleaving buffer 16, and a Viterbi decoding circuit 17. The receiver 27 has almost the same structure as the receiver 10 shown in Fig. 3 except that the fast Fourier transform circuit 41 is added and the processing in the reception circuit 40 and the demodulation section 42 is changed. First, the antenna 11 receives the transmission signal S22 transmitted from the transmitter 23 and inputs the signal to the reception circuit 40 as a reception signal S30. The reception circuit 40 amplifies the input reception signal S30, fetches a base band signal by applying frequency conversion to the reception signal S30, filters the base band signal, obtains the reception symbol groups S31 by applying analog-to-digital conversion to the base band signal, and outputs the reception symbol groups S31 to the fast Fourier transform circuit 41. In this connection, the reception circuit 40 alters frequency channels to receive in accordance with the same pattern as used in the transmission side so as to follow the alteration of the frequency channels in the transmission side, thereby performing accurate reception. The fast Fourier transform circuit 41 obtains signal components for one slot by applying so-called windowing to the input reception symbol groups S31, and applies Fourier transform to the obtained signal components. This arranges the components of the signal group, which are previously arranged on a frequency axis, on a time base. Thus, the reception symbol groups S32 obtained by being applied the Fourier transform are input to the following demodulation section 42. In this connection, the fast Fourier transform circuit 41 performs windowing by applying a cosine roll-off filter to the reception symbol group S31 on a time base, similarly to the case of the inverse fast Fourier transform circuit 32 at the transmission side. The demodulation section 42 comprises a transmission line estimation circuit 43, a weighting circuit 44, and a demodulation circuit 45. First, the supplied reception symbol groups S32 are input to the transmission line estimation circuit 43 and the weighting circuit 44. The transmission line estimation circuit 43 extracts pilot symbols P from the reception symbol groups S32, estimates the characteristics of the transmission line for each symbol in accordance with the amplitude and the phases of the pilot symbols P, and outputs a symbol series S33 showing the above estimation result to the following weighting circuit 44. The weighting circuit 44 calculates the reliability (that is, quality) of the transmission line for each symbol in accordance with the reception symbol groups S32 and the symbol series S33 showing the characteristics of the transmission line. The circuit 44 multiplies each information symbol I in the reception symbol group S32 by a weighting factor showing the calculated reliability so that the each information symbol I reflects the reliability of the transmission line. Then, the weighting circuit 44 outputs the reception information symbol groups S34 on which the reliability of the transmission line is reflected to the demodulation circuit 45, and also outputs the weighting factors S35 showing the transmission-line reliability calculated in symbols to the demodulation circuit 45. The demodulation circuit 45 fetches coded bit groups S36 from the reception information symbol groups S34 by applying prescribed demodulation (that is, demodulation corresponding to the modulation performed in the transmission side, such as QPSK, 8PSK, 16QAM, or 64QAM) to the symbol groups S34, and outputs the coded bit groups S36 to the following slot connection circuit 15. In this connection, in performing amplitude-modulation-based demodulation such as 16QAM or 64QAM, the demodulation circuit 45 uses the weighting factor S35 as a decision threshold for demodulation, and thereby obtain each soft decision bit constituting the coded bit group S36 from the reception information symbol group S34. Each soft decision bit constituting the coded bit group S36 is not a binary signal of 0 or 1 but a multi-valued signal because noise is added to each soft decision bit in the transmission line. The slot connection circuit 15, which is a circuit for connecting the coded bit groups S36 fragmentarily obtained in slots one another so as to make a continuous signal, connects the coded bit groups S36 when they are accumulated up to the storage capacity of the deinterleaving buffer 16 at the rear stage, and outputs the resulting coded bit series S37 to the buffer 16. The deinterleaving buffer 16, which has a storage capacity for a plurality of slots, successively stores the supplied coded bit series S37 in its internal storage area, restores the order of the series S37 to the original order by performing the backward process of the re-sequencing performed in the interleaving buffer 3 of the transmitter 23, and outputs the resulting coded bit series S38 to the Viterbi decoding circuit 17. The Viterbi decoding circuit 17, which is constituted with a soft-decision Viterbi decoding circuit, restores transmitted information bit series S39 by applying maximum-likelihood series estimation to the input coded bit series S38. In this case, the front-stage weighting circuit 44 has reflected the reliability (that is, quality) of a transmission line on the signal level of each received information symbol I by calculating the reliability of the transmission line for each symbol and multiplying the information symbol I by a weighting factor showing the reliability. Thus, the signal levels of the coded bit series S38 input to the Viterbi decoding circuit 17 reflect the reliability of the transmission line. Therefore, the inputting of the above series S38 allows the Viterbi decoding circuit 17 to perform maximum-likelihood series estimation upon consideration of the reliability of the transmission line for each symbol, resulting in the accurate restoration of information bit series S40. (4) Structure of Transmission Line Estimation Circuit Hereinafter, the transmission line estimation circuit 43 will be described in detail. In the subsequent description, a pilot symbol P and an information symbol I included in the received reception symbol group S32 are referred to respectively as a pilot symbol P' and an information symbol I' . As shown in Fig. 14, in the transmission line estimation circuit 43, the reception symbol groups S32 supplied from the fast Fourier transform circuit 41 are input to a signal separation switch 50. A pilot signal P' is extracted from the reception symbol group S32 by switching on the signal separation switch 50 at the timing of the symbol P', and output to a multiplier 51. A reference pilot symbol Pref read from a pilot symbol storage circuit 52 is input to the multiplier 51. The multiplier 51 complex-multiplies the value of the pilot symbol P' by the conjugate value of the reference pilot symbol Pref so as to obtain a value of the symbol P' divided by the value of the symbol Pref. In this connection, a reference pilot symbol Praf is the same symbol as a pilot symbol P transmitted from the transmission side: its amplitude value is 1 and its phase value is equal to that of the pilot symbol P. Therefore, as shown in Fig. 15, the division performed by the multiplier 51 theoretically corresponds to the processing for restoring the phase value of the received pilot symbol P' to 0, and every symbols in the resulting symbol series S40 has a amplitude value of 1 and a phase value of 0. However, the reception symbol group S32, in fact, includes undesirable signal components due to influence of noise, fading, interference waves, and deviation of the windowing in the fast Fourier transform circuit 41. Therefore, the received pilot symbol P' does not completely agree with the transmitted pilot symbol P. As shown in Fig. 16, all of the symbols in the symbol series S40 output from the multiplier 51 do not have amplitude values of 1 and phase values of 0. Therefore, by observing symbol series S45 output from the multiplier 51, it is possible to estimate transmission-line characteristics such as noise, fading, influence of interference waves, and deviation of windowing. Thus, the transmission line estimation circuit 43 estimates transmission-line characteristics by analyzing the symbol series S40. The symbol series S40 obtained thus are input to the following multiplier 53 and delay circuit 54. The delay circuit 54 successively delays the symbols of the symbol series S40 and outputs the resulting delay symbol series S41 to the multiplier 53. The multiplier 53 calculates a phase difference signal S42 between the present symbol and the preceding symbol by complex-multiplying the conjugate value of the present symbol supplied as the symbol series S40 by the conjugate value of the preceding symbol supplied as the delay symbol series S41, and outputs the signal S42 to the following phase value calculation circuit 55. The phase value calculation circuit 55 obtains the phase difference S43 between the present symbol and the preceding symbol by calculating the inverse tangent function (so-called arc tangent) of the phase difference signal S42, and outputs the phase difference S43 to the following adder 56. The adder 56, which is a circuit for calculating the absolute phase value of the present symbol by adding the phase difference S43 to the absolute phase value of the resulting preceding symbol, calculates the absolute phase value S45 of the present symbol by adding the phase difference S43 to the absolute phase value S44 of the preceding symbol delayed by a delay circuit 57, and outputs the absolute phase value S45 to the delay circuit 57, a multiplier 58, and an accumulative addition circuit 59. In this connection, by obtaining the phase difference between the present symbol and the preceding symbol as described above, adding the phase difference to the absolute phase value of the preceding symbol, and obtaining the absolute phase value of the present symbol, it is possible to determine the rotational direction of a phase when the phase difference between the symbols is less than π even if the phase rotation of the symbol series S40 is 2 π or more as a whole. Therefore, it is possible to securely calculate the absolute phase value of each symbol. The absolute phase value described above is an index for pointing an actual rotation value. For example, when a phase rotation is 5π /2, it is not assumed as π/2 but assumed as 5π/2 which is the actual rotation value. The accumulative addition circuit 59, which is a circuit for accumulatively adding absolute phase values obtained from the symbol series S40 for one slot, accumulatively adds the input absolute phase values S45 and outputs the resulting accumulated phase value S46 to a calculation section 60. The multiplier 58 obtains a multiplication value S48 between the absolute phase value and the symbol number of each symbol by multiplying the absolute phase value S45 supplied from the adder 56 by a symbol number S47 supplied from a symbol counter 61 to be described later, and outputs the value S48 to an accumulative addition circuit 62. The accumulative addition circuit 62 accumulatively adds the multiplication values S48 obtained from the symbol series S40 for one slot and outputs the resulting accumulated value S49 to the calculation section 60. Moreover, the above symbol series S40 is also supplied to an amplitude calculation circuit 63. The amplitude calculation circuit 63 squares each symbol of the symbol series S40, calculates the amplitude of each symbol of the symbol series S40 by obtaining the square root of the squared result, and outputs the amplitude of each symbol as an amplitude value S50 to an accumulative addition circuit 64 and a multiplier 65. The accumulative addition circuit 64 accumulates the amplitude values of the respective symbols by accumulatively adding the amplitude values S50 obtained from the symbol series S40 for one slot and outputs the resulting accumulative amplitude value S51 to the calculation section 60. The multiplier 65 obtains a multiplication value S52 between the amplitude value and the symbol number of each symbol by multiplying the amplitude value S50 supplied from the amplitude calculation circuit 63 by the symbol number S47 supplied from the symbol counter 61 to be described later, and outputs the value S52 to an accumulative addition circuit 66. The accumulative addition circuit 66 accumulatively adds the multiplication values S52 obtained from the symbol series S40 for one slot and outputs the resulting accumulated value S53 to the calculation section 60. The transmission line estimation circuit 43 inputs the reception symbol group S32 also to the symbol counter 61. The symbol counter 61 is a circuit for counting the number of symbols in the reception symbol group S32 in accordance with a symbol clock so as to examine at which position in a slot the currently-input pilot symbol P' is present. The circuit 43 outputs the resulting symbol number S47 to the above multipliers 58 and 65, and outputs the symbol number S47 to an accumulative addition circuit 67 and a square circuit 68. The accumulative addition circuit 67 accumulatively adds the symbol numbers S47 obtained from the pilot symbols P' for one slot and outputs the resulting accumulated value S54 of the symbol numbers to the calculation section 60. The square circuit 68, in the meantime, calculates a square value S55 of the symbol number S47 and outputs the value S55 to the following accumulative addition circuit 69. The accumulative addition circuit 69 accumulatively adds the square values S55 for one slot and outputs the resulting accumulated value S56 of the value S55 to the calculation section 60. The calculation section 60 calculates the symbol series S33 showing the aforesaid transmission-line characteristics in accordance with the resulting values (S46, S49, S51, S53, S54, and S56) , and outputs the resulting symbol series S33 to the following weighting circuit 44. In this connection, the symbol series S33 calculated by the calculation section 60 comprises the symbols showing the fluctuation amplitude values of the reception symbol group S32 suffering amplitude fluctuation and the phase rotation values of the reception symbol group S32. In the following description, the symbol series S33 is referred to as a reference symbol series S33. (5) Reference Symbol Series Generation Method The reference symbol series generation method by the calculation section 60 will be described below. First, the theory of the generation method will be described before the describing of a specific reference symbol series generation method. As shown in Fig. 17, the transmitter 23 transmits the transmission symbol group S5 in one slot by superimposing the respective symbols of the group S5 on 24 subcarriers. The subcarriers on which the transmission symbol groups S5 are superimposed are processed by prescribed transmission processing such as frequency conversion, and transmitted via the antenna 8. The transmission signal S22 transmitted from the antenna 8 is influenced, for example, by frequency selective fading or the like in the transmission line before arriving to the receiver 27. The receiver 27 receives the transmission signal S22, fetches the base band signal, and then obtains the reception symbol group S32 corresponding to the transmission symbol group S5 by applying Fourier transform to the signal S22. Since the reception symbol group S32 is influenced by frequency selective fading in the transmission line, interference waves, and/or errors in windowing when applied Fourier transform as described above, the group S32 fluctuates in amplitude and rotates in phase against the transmission symbol group S5. Figs. 18 and 19 show examples of the amplitude fluctuation and the phase rotation of the reception symbol group S32. As shown in Fig. 18, amplitude values of each symbol of the reception symbol group S32 are changed in symbols due to the amplitude fluctuation. The amplitude value of each symbol with fluctuation is generally expressed in an amplitude function rn, and the amplitude function rn is normally a function of degree m using a symbol number n as a parameter. However, this amplitude function rn may be expressed in a linear function of symbol number n as shown in the following equation (1) for approximation with practical accuracy, assuming the primary coefficient as Φ r and the degree zero coefficient (that is, initial value) as £r. rn=Φr • n+ £ r (1) By obtaining the amplitude function rn shown in the equation (1) from the actually-received reception symbol group S32, it is possible to generate the reference symbol series S33 showing the amplitude value of each symbol with fluctuation by using the amplitude function rn. Thus, as described above, the reference symbol series S33 is generated by obtaining the primary coefficient Φ r and degree zero coefficient € r of the amplitude function rn by using the values (S51, S53, S54, and S56) obtained from the pilot symbols P' in the reception symbol group S32. Similarly, phase rotation values are changed for each symbol of the reception symbol group S32 as shown in Fig. 19. The phase rotation value of each symbol is generally expressed in a phase function n, and the phase function n is normally a function of degree m using symbol number n as a parameter. However, this phase function  n may be expressed in a linear function of symbol number n as shown in the following Equation (2) for approximation with practical accuracy, assuming the primary coefficient as Φ  and degree zero coefficient (that is, initial value) as £ 6 . n=Φ • n+£  (2) By obtaining the phase function n shown in the equation (2) from the actually-received reception symbol groups S32, it is possible to generate the reference symbol series S33 showing the phase rotation value of each symbol of the reception symbol group S32 by the phase function n. Therefore, as described above, the reference symbol series S33 is generated by obtaining the primary coefficient Φ 6 and degree zero coefficient £  of the phase function  n by using the values (S46, S49, S54, and S56) obtained from pilot symbols P' included in the reception symbol group S32. Hereinafter, a specific method for generating the reference symbol series S33 will be described below. The calculation section 60 obtains the primary coefficient Φ r and the degree zero coefficient r of the amplitude function rn and the primary coefficient Φ  and the degree zero coefficient  9 of the phase function 6 n by assuming the accumulated phase value S46 obtained by accumulating the absolute phase value of each symbol as A , the accumulated value S49 obtained by accumulating the multiplication value between each absolute phase value and symbol number as B , the amplitude accumulated value S51 obtained by accumulating the amplitude value of each symbol as C , the accumulated value S53 obtained by accumulating the multiplication value between each amplitude value and symbol number as D , the accumulated value S54 of symbol numbers as E , the accumulated value S56 obtained by accumulating each square value of a symbol number as F , and the total number of pilot symbols P' in one slot as G, and substituting respective values for the following equations (3)-(6) according to the least-square method. Φr=(G x D-C x E)/(G x F-E x E) (3) £r=(C-ΦrXE)/G (4) Φ0 =